[llvm] [Mips] Support mips1 and singlethread ATOMIC_FENCE (PR #190129)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-mips

Author: yingopq

<details>
<summary>Changes</summary>

Fix #<!-- -->61166.

---
Full diff: https://github.com/llvm/llvm-project/pull/190129.diff


2 Files Affected:

- (modified) llvm/lib/Target/Mips/MipsISelLowering.cpp (+16-2) 
- (added) llvm/test/CodeGen/Mips/fence.ll (+37) 


``````````diff
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index c29f1b616356a..751d3f2a42d20 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -2667,8 +2667,22 @@ SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
   // FIXME: Set SType for weaker fences where supported/appropriate.
   unsigned SType = 0;
   SDLoc DL(Op);
-  return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
-                     DAG.getConstant(SType, DL, MVT::i32));
+  SyncScope::ID FenceSSID =
+      static_cast<SyncScope::ID>(Op.getConstantOperandVal(2));
+
+  if (Subtarget.hasMips2() && FenceSSID == SyncScope::System)
+    return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
+                       DAG.getConstant(SType, DL, MVT::i32));
+
+  // singlethread fences only synchronize with signal handlers on the same
+  // thread and thus only need to preserve instruction order, not actually
+  // enforce memory ordering.
+  if ((Subtarget.hasMips1() && !Subtarget.hasMips2()) ||
+      FenceSSID == SyncScope::SingleThread)
+    // MEMBARRIER is a compiler barrier; it codegens to a no-op.
+    return DAG.getNode(ISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
+
+  return Op;
 }
 
 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
diff --git a/llvm/test/CodeGen/Mips/fence.ll b/llvm/test/CodeGen/Mips/fence.ll
new file mode 100644
index 0000000000000..ff38b98e862f1
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/fence.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=mipsel-linux-gnu -mcpu=mips1 < %s | FileCheck %s --check-prefix=MIPS1
+; RUN: llc --mtriple=mipsel-linux-gnu -mcpu=mips2 < %s | FileCheck %s --check-prefix=MIPS2
+
+define void @fence_singlethread() {
+; MIPS1-LABEL: fence_singlethread:
+; MIPS1:       # %bb.0:
+; MIPS1-NEXT:    #MEMBARRIER
+; MIPS1-NEXT:    jr $ra
+; MIPS1-NEXT:    nop
+
+; MIPS2-LABEL: fence_singlethread:
+; MIPS2:       # %bb.0:
+; MIPS2-NEXT:    #MEMBARRIER
+; MIPS2-NEXT:    jr $ra
+; MIPS2-NEXT:    nop
+
+  fence syncscope("singlethread") seq_cst
+  ret void
+}
+
+define void @fence() {
+; MIPS1-LABEL: fence:
+; MIPS1:       # %bb.0:
+; MIPS1-NEXT:    #MEMBARRIER
+; MIPS1-NEXT:    jr $ra
+; MIPS1-NEXT:    nop
+
+; MIPS2-LABEL: fence:
+; MIPS2:       # %bb.0:
+; MIPS2-NEXT:    sync
+; MIPS2-NEXT:    jr $ra
+; MIPS2-NEXT:    nop
+
+  fence seq_cst
+  ret void
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/190129