[llvm] [DAG] computeKnownFPClass - Add handling for AssertNoFPClass (PR #190070)
Joao Victor Amorim Vieira via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 1 14:50:57 PDT 2026
https://github.com/joaovam created https://github.com/llvm/llvm-project/pull/190070
Resolves #189478
Adds code to handle AssertNoFPClass in computeKnownFPClass and adds IR test coverage for X86.
>From 6b2f74e9d0c2837700ce6789e0288514b3689bc9 Mon Sep 17 00:00:00 2001
From: joaovam <amorimvictorjoao3 at gmail.com>
Date: Wed, 1 Apr 2026 18:45:47 -0300
Subject: [PATCH] [DAG] computeKnownFPClass - Add handling for AssertNoFPClass
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 1067 +++++++++--------
llvm/test/CodeGen/X86/known-fpclass.ll | 29 +
2 files changed, 604 insertions(+), 492 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 3716de880cce3..cb4a0d6d11e8a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -18,6 +18,7 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseSet.h"
+#include "llvm/ADT/FloatingPointMode.h"
#include "llvm/ADT/FoldingSet.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
@@ -92,8 +93,8 @@ static SDVTList makeVTList(const EVT *VTs, unsigned NumVTs) {
}
// Default null implementations of the callbacks.
-void SelectionDAG::DAGUpdateListener::NodeDeleted(SDNode*, SDNode*) {}
-void SelectionDAG::DAGUpdateListener::NodeUpdated(SDNode*) {}
+void SelectionDAG::DAGUpdateListener::NodeDeleted(SDNode *, SDNode *) {}
+void SelectionDAG::DAGUpdateListener::NodeUpdated(SDNode *) {}
void SelectionDAG::DAGUpdateListener::NodeInserted(SDNode *) {}
void SelectionDAG::DAGNodeDeletedListener::anchor() {}
@@ -101,13 +102,14 @@ void SelectionDAG::DAGNodeInsertedListener::anchor() {}
#define DEBUG_TYPE "selectiondag"
-static cl::opt<bool> EnableMemCpyDAGOpt("enable-memcpy-dag-opt",
- cl::Hidden, cl::init(true),
- cl::desc("Gang up loads and stores generated by inlining of memcpy"));
+static cl::opt<bool> EnableMemCpyDAGOpt(
+ "enable-memcpy-dag-opt", cl::Hidden, cl::init(true),
+ cl::desc("Gang up loads and stores generated by inlining of memcpy"));
-static cl::opt<int> MaxLdStGlue("ldstmemcpy-glue-max",
- cl::desc("Number limit for gluing ld/st of memcpy."),
- cl::Hidden, cl::init(0));
+static cl::opt<int>
+ MaxLdStGlue("ldstmemcpy-glue-max",
+ cl::desc("Number limit for gluing ld/st of memcpy."),
+ cl::Hidden, cl::init(0));
static cl::opt<unsigned>
MaxSteps("has-predecessor-max-steps", cl::Hidden, cl::init(8192),
@@ -128,12 +130,11 @@ unsigned SelectionDAG::getHasPredecessorMaxSteps() { return MaxSteps; }
/// it returns true for things that are clearly not equal, like -0.0 and 0.0.
/// As such, this method can be used to do an exact bit-for-bit comparison of
/// two floating point values.
-bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const {
+bool ConstantFPSDNode::isExactlyValue(const APFloat &V) const {
return getValueAPF().bitwiseIsEqual(V);
}
-bool ConstantFPSDNode::isValueValidForType(EVT VT,
- const APFloat& Val) {
+bool ConstantFPSDNode::isValueValidForType(EVT VT, const APFloat &Val) {
assert(VT.isFloatingPoint() && "Can only convert between FP types");
// convert modifies in place, so make a copy.
@@ -189,7 +190,8 @@ bool ISD::isConstantSplatVectorAllOnes(const SDNode *N, bool BuildVectorOnly) {
return isConstantSplatVector(N, SplatVal) && SplatVal.isAllOnes();
}
- if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
+ if (N->getOpcode() != ISD::BUILD_VECTOR)
+ return false;
unsigned i = 0, e = N->getNumOperands();
@@ -198,7 +200,8 @@ bool ISD::isConstantSplatVectorAllOnes(const SDNode *N, bool BuildVectorOnly) {
++i;
// Do not accept an all-undef vector.
- if (i == e) return false;
+ if (i == e)
+ return false;
// Do not accept build_vectors that aren't all constants or which have non-~0
// elements. We have to be a bit careful here, as the type of the constant
@@ -235,7 +238,8 @@ bool ISD::isConstantSplatVectorAllZeros(const SDNode *N, bool BuildVectorOnly) {
return isConstantSplatVector(N, SplatVal) && SplatVal.isZero();
}
- if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
+ if (N->getOpcode() != ISD::BUILD_VECTOR)
+ return false;
bool IsAllUndef = true;
for (const SDValue &Op : N->op_values()) {
@@ -622,20 +626,20 @@ ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) {
// operation.
unsigned OldL = (Operation >> 2) & 1;
unsigned OldG = (Operation >> 1) & 1;
- return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits
- (OldL << 1) | // New G bit
- (OldG << 2)); // New L bit.
+ return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits
+ (OldL << 1) | // New G bit
+ (OldG << 2)); // New L bit.
}
static ISD::CondCode getSetCCInverseImpl(ISD::CondCode Op, bool isIntegerLike) {
unsigned Operation = Op;
if (isIntegerLike)
- Operation ^= 7; // Flip L, G, E bits, but not U.
+ Operation ^= 7; // Flip L, G, E bits, but not U.
else
- Operation ^= 15; // Flip all of the condition bits.
+ Operation ^= 15; // Flip all of the condition bits.
if (Operation > ISD::SETTRUE2)
- Operation &= ~8; // Don't let N and U bits get set.
+ Operation &= ~8; // Don't let N and U bits get set.
return ISD::CondCode(Operation);
}
@@ -654,17 +658,21 @@ ISD::CondCode ISD::GlobalISel::getSetCCInverse(ISD::CondCode Op,
/// does not depend on the sign of the input (setne and seteq).
static int isSignedOp(ISD::CondCode Opcode) {
switch (Opcode) {
- default: llvm_unreachable("Illegal integer setcc operation!");
+ default:
+ llvm_unreachable("Illegal integer setcc operation!");
case ISD::SETEQ:
- case ISD::SETNE: return 0;
+ case ISD::SETNE:
+ return 0;
case ISD::SETLT:
case ISD::SETLE:
case ISD::SETGT:
- case ISD::SETGE: return 1;
+ case ISD::SETGE:
+ return 1;
case ISD::SETULT:
case ISD::SETULE:
case ISD::SETUGT:
- case ISD::SETUGE: return 2;
+ case ISD::SETUGE:
+ return 2;
}
}
@@ -675,15 +683,15 @@ ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
// Cannot fold a signed integer setcc with an unsigned integer setcc.
return ISD::SETCC_INVALID;
- unsigned Op = Op1 | Op2; // Combine all of the condition bits.
+ unsigned Op = Op1 | Op2; // Combine all of the condition bits.
// If the N and U bits get set, then the resultant comparison DOES suddenly
// care about orderedness, and it is true when ordered.
if (Op > ISD::SETTRUE2)
- Op &= ~16; // Clear the U bit if the N bit is set.
+ Op &= ~16; // Clear the U bit if the N bit is set.
// Canonicalize illegal integer setcc's.
- if (IsInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT
+ if (IsInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT
Op = ISD::SETNE;
return ISD::CondCode(Op);
@@ -702,12 +710,21 @@ ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
// Canonicalize illegal integer setcc's.
if (IsInteger) {
switch (Result) {
- default: break;
- case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT
- case ISD::SETOEQ: // SETEQ & SETU[LG]E
- case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE
- case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE
- case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE
+ default:
+ break;
+ case ISD::SETUO:
+ Result = ISD::SETFALSE;
+ break; // SETUGT & SETULT
+ case ISD::SETOEQ: // SETEQ & SETU[LG]E
+ case ISD::SETUEQ:
+ Result = ISD::SETEQ;
+ break; // SETUGE & SETULE
+ case ISD::SETOLT:
+ Result = ISD::SETULT;
+ break; // SETULT & SETNE
+ case ISD::SETOGT:
+ Result = ISD::SETUGT;
+ break; // SETUGT & SETNE
}
}
@@ -719,7 +736,7 @@ ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
//===----------------------------------------------------------------------===//
/// AddNodeIDOpcode - Add the node opcode to the NodeID data.
-static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) {
+static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) {
ID.AddInteger(OpC);
}
@@ -730,8 +747,7 @@ static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) {
}
/// AddNodeIDOperands - Various routines for adding operands to the NodeID data.
-static void AddNodeIDOperands(FoldingSetNodeID &ID,
- ArrayRef<SDValue> Ops) {
+static void AddNodeIDOperands(FoldingSetNodeID &ID, ArrayRef<SDValue> Ops) {
for (const auto &Op : Ops) {
ID.AddPointer(Op.getNode());
ID.AddInteger(Op.getResNo());
@@ -739,16 +755,15 @@ static void AddNodeIDOperands(FoldingSetNodeID &ID,
}
/// AddNodeIDOperands - Various routines for adding operands to the NodeID data.
-static void AddNodeIDOperands(FoldingSetNodeID &ID,
- ArrayRef<SDUse> Ops) {
+static void AddNodeIDOperands(FoldingSetNodeID &ID, ArrayRef<SDUse> Ops) {
for (const auto &Op : Ops) {
ID.AddPointer(Op.getNode());
ID.AddInteger(Op.getResNo());
}
}
-static void AddNodeIDNode(FoldingSetNodeID &ID, unsigned OpC,
- SDVTList VTList, ArrayRef<SDValue> OpList) {
+static void AddNodeIDNode(FoldingSetNodeID &ID, unsigned OpC, SDVTList VTList,
+ ArrayRef<SDValue> OpList) {
AddNodeIDOpcode(ID, OpC);
AddNodeIDValueTypes(ID, VTList);
AddNodeIDOperands(ID, OpList);
@@ -761,7 +776,8 @@ static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
case ISD::ExternalSymbol:
case ISD::MCSymbol:
llvm_unreachable("Should only be used on nodes with operands");
- default: break; // Normal nodes don't need extra info.
+ default:
+ break; // Normal nodes don't need extra info.
case ISD::TargetConstant:
case ISD::Constant: {
const ConstantSDNode *C = cast<ConstantSDNode>(N);
@@ -1021,10 +1037,11 @@ static bool doNotCSE(SDNode *N) {
return true; // Never CSE anything that produces a glue result.
switch (N->getOpcode()) {
- default: break;
+ default:
+ break;
case ISD::HANDLENODE:
case ISD::EH_LABEL:
- return true; // Never CSE these nodes.
+ return true; // Never CSE these nodes.
}
// Check that remaining values produced are not flags.
@@ -1042,7 +1059,7 @@ void SelectionDAG::RemoveDeadNodes() {
// to the root node, preventing it from being deleted.
HandleSDNode Dummy(getRoot());
- SmallVector<SDNode*, 128> DeadNodes;
+ SmallVector<SDNode *, 128> DeadNodes;
// Add all obviously-dead nodes to the DeadNodes worklist.
for (SDNode &Node : allnodes())
@@ -1077,7 +1094,7 @@ void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes) {
// Next, brutally remove the operand list. This is safe to do, as there are
// no cycles in the graph.
- for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) {
+ for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E;) {
SDUse &Use = *I++;
SDNode *Operand = Use.getNode();
Use.set(SDValue());
@@ -1091,8 +1108,8 @@ void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes) {
}
}
-void SelectionDAG::RemoveDeadNode(SDNode *N){
- SmallVector<SDNode*, 16> DeadNodes(1, N);
+void SelectionDAG::RemoveDeadNode(SDNode *N) {
+ SmallVector<SDNode *, 16> DeadNodes(1, N);
// Create a dummy node that adds a reference to the root node, preventing
// it from being deleted. (This matters if the root is an operand of the
@@ -1137,7 +1154,7 @@ void SDDbgInfo::erase(const SDNode *Node) {
DbgValMapType::iterator I = DbgValMap.find(Node);
if (I == DbgValMap.end())
return;
- for (auto &Val: I->second)
+ for (auto &Val : I->second)
Val->setIsInvalidated();
DbgValMap.erase(I);
}
@@ -1239,7 +1256,8 @@ void SelectionDAG::InsertNode(SDNode *N) {
bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
bool Erased = false;
switch (N->getOpcode()) {
- case ISD::HANDLENODE: return false; // noop.
+ case ISD::HANDLENODE:
+ return false; // noop.
case ISD::CONDCODE:
assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] &&
"Cond code doesn't exist!");
@@ -1281,7 +1299,7 @@ bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
// Verify that the node was actually in one of the CSE maps, unless it has a
// glue result (which cannot be CSE'd) or is one of the special cases that are
// not subject to CSE.
- if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Glue &&
+ if (!Erased && N->getValueType(N->getNumValues() - 1) != MVT::Glue &&
!N->isMachineOpcode() && !doNotCSE(N)) {
N->dump(this);
dbgs() << "\n";
@@ -1295,8 +1313,7 @@ bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
/// maps and modified in place. Add it back to the CSE maps, unless an identical
/// node already exists, in which case transfer all its users to the existing
/// node. This transfer can potentially trigger recursive merging.
-void
-SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N) {
+void SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N) {
// For node types that aren't CSE'd, just act as if no identical node
// already exists.
if (!doNotCSE(N)) {
@@ -1332,7 +1349,7 @@ SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op,
if (doNotCSE(N))
return nullptr;
- SDValue Ops[] = { Op };
+ SDValue Ops[] = {Op};
FoldingSetNodeID ID;
AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops);
AddNodeIDCustom(ID, N);
@@ -1346,13 +1363,12 @@ SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op,
/// were replaced with those specified. If this node is never memoized,
/// return null, otherwise return a pointer to the slot it would take. If a
/// node already exists with these operands, the slot will be non-null.
-SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
- SDValue Op1, SDValue Op2,
+SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op1, SDValue Op2,
void *&InsertPos) {
if (doNotCSE(N))
return nullptr;
- SDValue Ops[] = { Op1, Op2 };
+ SDValue Ops[] = {Op1, Op2};
FoldingSetNodeID ID;
AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops);
AddNodeIDCustom(ID, N);
@@ -1444,7 +1460,8 @@ SDNode *SelectionDAG::FindNodeOrInsertPos(const FoldingSetNodeID &ID,
SDNode *N = CSEMap.FindNodeOrInsertPos(ID, InsertPos);
if (N) {
switch (N->getOpcode()) {
- default: break;
+ default:
+ break;
case ISD::Constant:
case ISD::ConstantFP:
llvm_unreachable("Querying for Constant and ConstantFP nodes requires "
@@ -1521,21 +1538,18 @@ SelectionDAG::getStrictFPExtendOrRound(SDValue Op, SDValue Chain,
}
SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {
- return VT.bitsGT(Op.getValueType()) ?
- getNode(ISD::ANY_EXTEND, DL, VT, Op) :
- getNode(ISD::TRUNCATE, DL, VT, Op);
+ return VT.bitsGT(Op.getValueType()) ? getNode(ISD::ANY_EXTEND, DL, VT, Op)
+ : getNode(ISD::TRUNCATE, DL, VT, Op);
}
SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {
- return VT.bitsGT(Op.getValueType()) ?
- getNode(ISD::SIGN_EXTEND, DL, VT, Op) :
- getNode(ISD::TRUNCATE, DL, VT, Op);
+ return VT.bitsGT(Op.getValueType()) ? getNode(ISD::SIGN_EXTEND, DL, VT, Op)
+ : getNode(ISD::TRUNCATE, DL, VT, Op);
}
SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {
- return VT.bitsGT(Op.getValueType()) ?
- getNode(ISD::ZERO_EXTEND, DL, VT, Op) :
- getNode(ISD::TRUNCATE, DL, VT, Op);
+ return VT.bitsGT(Op.getValueType()) ? getNode(ISD::ZERO_EXTEND, DL, VT, Op)
+ : getNode(ISD::TRUNCATE, DL, VT, Op);
}
SDValue SelectionDAG::getBitcastedAnyExtOrTrunc(SDValue Op, const SDLoc &DL,
@@ -1554,7 +1568,7 @@ SDValue SelectionDAG::getBitcastedAnyExtOrTrunc(SDValue Op, const SDLoc &DL,
}
SDValue SelectionDAG::getBitcastedSExtOrTrunc(SDValue Op, const SDLoc &DL,
- EVT VT) {
+ EVT VT) {
assert(!VT.isVector());
auto Type = Op.getValueType();
SDValue DestOp;
@@ -1569,7 +1583,7 @@ SDValue SelectionDAG::getBitcastedSExtOrTrunc(SDValue Op, const SDLoc &DL,
}
SDValue SelectionDAG::getBitcastedZExtOrTrunc(SDValue Op, const SDLoc &DL,
- EVT VT) {
+ EVT VT) {
assert(!VT.isVector());
auto Type = Op.getValueType();
SDValue DestOp;
@@ -1747,8 +1761,7 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, const SDLoc &DL,
unsigned ViaEltSizeInBits = ViaEltVT.getSizeInBits();
// For scalable vectors, try to use a SPLAT_VECTOR_PARTS node.
- if (VT.isScalableVector() ||
- TLI->isOperationLegal(ISD::SPLAT_VECTOR, VT)) {
+ if (VT.isScalableVector() || TLI->isOperationLegal(ISD::SPLAT_VECTOR, VT)) {
assert(EltVT.getSizeInBits() % ViaEltSizeInBits == 0 &&
"Can only handle an even split!");
unsigned Parts = EltVT.getSizeInBits() / ViaEltSizeInBits;
@@ -1951,7 +1964,7 @@ SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, const SDLoc &DL,
auto *N = newSDNode<GlobalAddressSDNode>(
Opc, DL.getIROrder(), DL.getDebugLoc(), GV, VTs, Offset, TargetFlags);
CSEMap.InsertNode(N, IP);
- InsertNode(N);
+ InsertNode(N);
return SDValue(N, 0);
}
@@ -2084,14 +2097,15 @@ SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) {
}
SDValue SelectionDAG::getValueType(EVT VT) {
- if (VT.isSimple() && (unsigned)VT.getSimpleVT().SimpleTy >=
- ValueTypeNodes.size())
- ValueTypeNodes.resize(VT.getSimpleVT().SimpleTy+1);
+ if (VT.isSimple() &&
+ (unsigned)VT.getSimpleVT().SimpleTy >= ValueTypeNodes.size())
+ ValueTypeNodes.resize(VT.getSimpleVT().SimpleTy + 1);
- SDNode *&N = VT.isExtended() ?
- ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT().SimpleTy];
+ SDNode *&N = VT.isExtended() ? ExtendedValueTypeNodes[VT]
+ : ValueTypeNodes[VT.getSimpleVT().SimpleTy];
- if (N) return SDValue(N, 0);
+ if (N)
+ return SDValue(N, 0);
N = newSDNode<VTSDNode>(VT);
InsertNode(N);
return SDValue(N, 0);
@@ -2099,7 +2113,8 @@ SDValue SelectionDAG::getValueType(EVT VT) {
SDValue SelectionDAG::getExternalSymbol(const char *Sym, EVT VT) {
SDNode *&N = ExternalSymbols[Sym];
- if (N) return SDValue(N, 0);
+ if (N)
+ return SDValue(N, 0);
N = newSDNode<ExternalSymbolSDNode>(false, Sym, 0, getVTList(VT));
InsertNode(N);
return SDValue(N, 0);
@@ -2123,7 +2138,8 @@ SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, EVT VT,
unsigned TargetFlags) {
SDNode *&N =
TargetExternalSymbols[std::pair<std::string, unsigned>(Sym, TargetFlags)];
- if (N) return SDValue(N, 0);
+ if (N)
+ return SDValue(N, 0);
N = newSDNode<ExternalSymbolSDNode>(true, Sym, TargetFlags, getVTList(VT));
InsertNode(N);
return SDValue(N, 0);
@@ -2137,7 +2153,7 @@ SDValue SelectionDAG::getTargetExternalSymbol(RTLIB::LibcallImpl Libcall,
SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) {
if ((unsigned)Cond >= CondCodeNodes.size())
- CondCodeNodes.resize(Cond+1);
+ CondCodeNodes.resize(Cond + 1);
if (!CondCodeNodes[Cond]) {
auto *N = newSDNode<CondCodeSDNode>(Cond);
@@ -2236,9 +2252,9 @@ SDValue SelectionDAG::getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1,
// Validate that all indices in Mask are within the range of the elements
// input to the shuffle.
int NElts = Mask.size();
- assert(llvm::all_of(Mask,
- [&](int M) { return M < (NElts * 2) && M >= -1; }) &&
- "Index out of range");
+ assert(
+ llvm::all_of(Mask, [&](int M) { return M < (NElts * 2) && M >= -1; }) &&
+ "Index out of range");
// Copy the mask so we can do any needed cleanup.
SmallVector<int, 8> MaskVec(Mask);
@@ -2247,7 +2263,8 @@ SDValue SelectionDAG::getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1,
if (N1 == N2) {
N2 = getUNDEF(VT);
for (int i = 0; i != NElts; ++i)
- if (MaskVec[i] >= NElts) MaskVec[i] -= NElts;
+ if (MaskVec[i] >= NElts)
+ MaskVec[i] -= NElts;
}
// Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
@@ -2315,8 +2332,10 @@ SDValue SelectionDAG::getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1,
// If Identity shuffle return that node.
bool Identity = true, AllSame = true;
for (int i = 0; i != NElts; ++i) {
- if (MaskVec[i] >= 0 && MaskVec[i] != i) Identity = false;
- if (MaskVec[i] != MaskVec[0]) AllSame = false;
+ if (MaskVec[i] >= 0 && MaskVec[i] != i)
+ Identity = false;
+ if (MaskVec[i] != MaskVec[0])
+ AllSame = false;
}
if (Identity && NElts)
return N1;
@@ -2367,12 +2386,12 @@ SDValue SelectionDAG::getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1,
SDVTList VTs = getVTList(VT);
FoldingSetNodeID ID;
- SDValue Ops[2] = { N1, N2 };
+ SDValue Ops[2] = {N1, N2};
AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, VTs, Ops);
for (int i = 0; i != NElts; ++i)
ID.AddInteger(MaskVec[i]);
- void* IP = nullptr;
+ void *IP = nullptr;
if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP))
return SDValue(E, 0);
@@ -2441,7 +2460,7 @@ SDValue SelectionDAG::getEHLabel(const SDLoc &dl, SDValue Root,
SDValue SelectionDAG::getLabelNode(unsigned Opcode, const SDLoc &dl,
SDValue Root, MCSymbol *Label) {
FoldingSetNodeID ID;
- SDValue Ops[] = { Root };
+ SDValue Ops[] = {Root};
AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), Ops);
ID.AddPointer(Label);
void *IP = nullptr;
@@ -2553,7 +2572,8 @@ SDValue SelectionDAG::getFreeze(SDValue V, const APInt &DemandedElts,
SDValue SelectionDAG::getShiftAmountOperand(EVT LHSTy, SDValue Op) {
EVT OpTy = Op.getValueType();
EVT ShTy = TLI->getShiftAmountTy(LHSTy, getDataLayout());
- if (OpTy == ShTy || OpTy.isVector()) return Op;
+ if (OpTy == ShTy || OpTy.isVector())
+ return Op;
return getZExtOrTrunc(Op, SDLoc(Op), ShTy);
}
@@ -2583,7 +2603,7 @@ SDValue SelectionDAG::expandVAArg(SDNode *Node) {
// Increment the pointer, VAList, to the next vaarg
Tmp1 = getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
getConstant(getDataLayout().getTypeAllocSize(
- VT.getTypeForEVT(*getContext())),
+ VT.getTypeForEVT(*getContext())),
dl, VAList.getValueType()));
// Store the incremented VAList to the legalized pointer
Tmp1 =
@@ -2693,11 +2713,14 @@ SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1, SDValue N2,
// These setcc operations always fold.
switch (Cond) {
- default: break;
+ default:
+ break;
case ISD::SETFALSE:
- case ISD::SETFALSE2: return getBoolConstant(false, dl, VT, OpVT);
+ case ISD::SETFALSE2:
+ return getBoolConstant(false, dl, VT, OpVT);
case ISD::SETTRUE:
- case ISD::SETTRUE2: return getBoolConstant(true, dl, VT, OpVT);
+ case ISD::SETTRUE2:
+ return getBoolConstant(true, dl, VT, OpVT);
case ISD::SETOEQ:
case ISD::SETOGT:
@@ -2749,58 +2772,69 @@ SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1, SDValue N2,
if (N1CFP && N2CFP) {
APFloat::cmpResult R = N1CFP->getValueAPF().compare(N2CFP->getValueAPF());
switch (Cond) {
- default: break;
- case ISD::SETEQ: if (R==APFloat::cmpUnordered)
- return GetUndefBooleanConstant();
- [[fallthrough]];
- case ISD::SETOEQ: return getBoolConstant(R==APFloat::cmpEqual, dl, VT,
- OpVT);
- case ISD::SETNE: if (R==APFloat::cmpUnordered)
- return GetUndefBooleanConstant();
- [[fallthrough]];
- case ISD::SETONE: return getBoolConstant(R==APFloat::cmpGreaterThan ||
- R==APFloat::cmpLessThan, dl, VT,
- OpVT);
- case ISD::SETLT: if (R==APFloat::cmpUnordered)
- return GetUndefBooleanConstant();
- [[fallthrough]];
- case ISD::SETOLT: return getBoolConstant(R==APFloat::cmpLessThan, dl, VT,
- OpVT);
- case ISD::SETGT: if (R==APFloat::cmpUnordered)
- return GetUndefBooleanConstant();
- [[fallthrough]];
- case ISD::SETOGT: return getBoolConstant(R==APFloat::cmpGreaterThan, dl,
- VT, OpVT);
- case ISD::SETLE: if (R==APFloat::cmpUnordered)
- return GetUndefBooleanConstant();
- [[fallthrough]];
- case ISD::SETOLE: return getBoolConstant(R==APFloat::cmpLessThan ||
- R==APFloat::cmpEqual, dl, VT,
- OpVT);
- case ISD::SETGE: if (R==APFloat::cmpUnordered)
- return GetUndefBooleanConstant();
- [[fallthrough]];
- case ISD::SETOGE: return getBoolConstant(R==APFloat::cmpGreaterThan ||
- R==APFloat::cmpEqual, dl, VT, OpVT);
- case ISD::SETO: return getBoolConstant(R!=APFloat::cmpUnordered, dl, VT,
- OpVT);
- case ISD::SETUO: return getBoolConstant(R==APFloat::cmpUnordered, dl, VT,
- OpVT);
- case ISD::SETUEQ: return getBoolConstant(R==APFloat::cmpUnordered ||
- R==APFloat::cmpEqual, dl, VT,
- OpVT);
- case ISD::SETUNE: return getBoolConstant(R!=APFloat::cmpEqual, dl, VT,
- OpVT);
- case ISD::SETULT: return getBoolConstant(R==APFloat::cmpUnordered ||
- R==APFloat::cmpLessThan, dl, VT,
- OpVT);
- case ISD::SETUGT: return getBoolConstant(R==APFloat::cmpGreaterThan ||
- R==APFloat::cmpUnordered, dl, VT,
- OpVT);
- case ISD::SETULE: return getBoolConstant(R!=APFloat::cmpGreaterThan, dl,
- VT, OpVT);
- case ISD::SETUGE: return getBoolConstant(R!=APFloat::cmpLessThan, dl, VT,
- OpVT);
+ default:
+ break;
+ case ISD::SETEQ:
+ if (R == APFloat::cmpUnordered)
+ return GetUndefBooleanConstant();
+ [[fallthrough]];
+ case ISD::SETOEQ:
+ return getBoolConstant(R == APFloat::cmpEqual, dl, VT, OpVT);
+ case ISD::SETNE:
+ if (R == APFloat::cmpUnordered)
+ return GetUndefBooleanConstant();
+ [[fallthrough]];
+ case ISD::SETONE:
+ return getBoolConstant(R == APFloat::cmpGreaterThan ||
+ R == APFloat::cmpLessThan,
+ dl, VT, OpVT);
+ case ISD::SETLT:
+ if (R == APFloat::cmpUnordered)
+ return GetUndefBooleanConstant();
+ [[fallthrough]];
+ case ISD::SETOLT:
+ return getBoolConstant(R == APFloat::cmpLessThan, dl, VT, OpVT);
+ case ISD::SETGT:
+ if (R == APFloat::cmpUnordered)
+ return GetUndefBooleanConstant();
+ [[fallthrough]];
+ case ISD::SETOGT:
+ return getBoolConstant(R == APFloat::cmpGreaterThan, dl, VT, OpVT);
+ case ISD::SETLE:
+ if (R == APFloat::cmpUnordered)
+ return GetUndefBooleanConstant();
+ [[fallthrough]];
+ case ISD::SETOLE:
+ return getBoolConstant(
+ R == APFloat::cmpLessThan || R == APFloat::cmpEqual, dl, VT, OpVT);
+ case ISD::SETGE:
+ if (R == APFloat::cmpUnordered)
+ return GetUndefBooleanConstant();
+ [[fallthrough]];
+ case ISD::SETOGE:
+ return getBoolConstant(
+ R == APFloat::cmpGreaterThan || R == APFloat::cmpEqual, dl, VT, OpVT);
+ case ISD::SETO:
+ return getBoolConstant(R != APFloat::cmpUnordered, dl, VT, OpVT);
+ case ISD::SETUO:
+ return getBoolConstant(R == APFloat::cmpUnordered, dl, VT, OpVT);
+ case ISD::SETUEQ:
+ return getBoolConstant(
+ R == APFloat::cmpUnordered || R == APFloat::cmpEqual, dl, VT, OpVT);
+ case ISD::SETUNE:
+ return getBoolConstant(R != APFloat::cmpEqual, dl, VT, OpVT);
+ case ISD::SETULT:
+ return getBoolConstant(R == APFloat::cmpUnordered ||
+ R == APFloat::cmpLessThan,
+ dl, VT, OpVT);
+ case ISD::SETUGT:
+ return getBoolConstant(R == APFloat::cmpGreaterThan ||
+ R == APFloat::cmpUnordered,
+ dl, VT, OpVT);
+ case ISD::SETULE:
+ return getBoolConstant(R != APFloat::cmpGreaterThan, dl, VT, OpVT);
+ case ISD::SETUGE:
+ return getBoolConstant(R != APFloat::cmpLessThan, dl, VT, OpVT);
}
} else if (N1CFP && OpVT.isSimple() && !N2.isUndef()) {
// Ensure that the constant occurs on the RHS.
@@ -3136,8 +3170,8 @@ bool SelectionDAG::isSplatValue(SDValue V, bool AllowUndefs) const {
// Since the number of lanes in a scalable vector is unknown at compile time,
// we track one bit which is implicitly broadcast to all lanes. This means
// that all lanes in a scalable vector are considered demanded.
- APInt DemandedElts
- = APInt::getAllOnes(VT.isScalableVector() ? 1 : VT.getVectorNumElements());
+ APInt DemandedElts =
+ APInt::getAllOnes(VT.isScalableVector() ? 1 : VT.getVectorNumElements());
return isSplatValue(V, DemandedElts, UndefElts) &&
(AllowUndefs || !UndefElts);
}
@@ -3150,11 +3184,11 @@ SDValue SelectionDAG::getSplatSourceVector(SDValue V, int &SplatIdx) {
switch (Opcode) {
default: {
APInt UndefElts;
- // Since the number of lanes in a scalable vector is unknown at compile time,
- // we track one bit which is implicitly broadcast to all lanes. This means
- // that all lanes in a scalable vector are considered demanded.
- APInt DemandedElts
- = APInt::getAllOnes(VT.isScalableVector() ? 1 : VT.getVectorNumElements());
+ // Since the number of lanes in a scalable vector is unknown at compile
+ // time, we track one bit which is implicitly broadcast to all lanes. This
+ // means that all lanes in a scalable vector are considered demanded.
+ APInt DemandedElts = APInt::getAllOnes(
+ VT.isScalableVector() ? 1 : VT.getVectorNumElements());
if (isSplatValue(V, DemandedElts, UndefElts)) {
if (VT.isScalableVector()) {
@@ -3346,7 +3380,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
unsigned Depth) const {
unsigned BitWidth = Op.getScalarValueSizeInBits();
- KnownBits Known(BitWidth); // Don't know anything.
+ KnownBits Known(BitWidth); // Don't know anything.
if (auto OptAPInt = Op->bitcastToAPInt()) {
// We know all of the bits for a constant!
@@ -3354,7 +3388,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
}
if (Depth >= MaxRecursionDepth)
- return Known; // Limit search depth.
+ return Known; // Limit search depth.
KnownBits Known2;
unsigned NumElts = DemandedElts.getBitWidth();
@@ -3365,7 +3399,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
"Unexpected vector size");
if (!DemandedElts)
- return Known; // No demanded elts, better to assume we don't know anything.
+ return Known; // No demanded elts, better to assume we don't know anything.
unsigned Opcode = Op.getOpcode();
switch (Opcode) {
@@ -3600,8 +3634,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
SubDemandedElts.setBit(i * SubScale);
for (unsigned i = 0; i != SubScale; ++i) {
- Known2 = computeKnownBits(N0, SubDemandedElts.shl(i),
- Depth + 1);
+ Known2 = computeKnownBits(N0, SubDemandedElts.shl(i), Depth + 1);
unsigned Shifts = IsLE ? i : SubScale - 1 - i;
Known.insertBits(Known2, SubBitWidth * Shifts);
}
@@ -3664,8 +3697,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
// with itself is non-negative. Only do this if we didn't already computed
// the opposite value for the sign bit.
if (Op->getFlags().hasNoSignedWrap() &&
- Op.getOperand(0) == Op.getOperand(1) &&
- !Known.isNegative())
+ Op.getOperand(0) == Op.getOperand(1) && !Known.isNegative())
Known.makeNonNegative();
break;
}
@@ -3748,21 +3780,21 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
}
case ISD::SELECT:
case ISD::VSELECT:
- Known = computeKnownBits(Op.getOperand(2), DemandedElts, Depth+1);
+ Known = computeKnownBits(Op.getOperand(2), DemandedElts, Depth + 1);
// If we don't know any bits, early out.
if (Known.isUnknown())
break;
- Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth+1);
+ Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
// Only known if known in both the LHS and RHS.
Known = Known.intersectWith(Known2);
break;
case ISD::SELECT_CC:
- Known = computeKnownBits(Op.getOperand(3), DemandedElts, Depth+1);
+ Known = computeKnownBits(Op.getOperand(3), DemandedElts, Depth + 1);
// If we don't know any bits, early out.
if (Known.isUnknown())
break;
- Known2 = computeKnownBits(Op.getOperand(2), DemandedElts, Depth+1);
+ Known2 = computeKnownBits(Op.getOperand(2), DemandedElts, Depth + 1);
// Only known if known in both the LHS and RHS.
Known = Known.intersectWith(Known2);
@@ -3844,7 +3876,8 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
break;
case ISD::FSHL:
case ISD::FSHR:
- if (ConstantSDNode *C = isConstOrConstSplat(Op.getOperand(2), DemandedElts)) {
+ if (ConstantSDNode *C =
+ isConstOrConstSplat(Op.getOperand(2), DemandedElts)) {
unsigned Amt = C->getAPIntValue().urem(BitWidth);
// For fshl, 0-shift returns the 1st arg.
@@ -4103,7 +4136,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits());
Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
Known.Zero |= (~InMask);
- Known.One &= (~Known.Zero);
+ Known.One &= (~Known.Zero);
break;
}
case ISD::AssertAlign: {
@@ -4256,12 +4289,13 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
break;
}
case ISD::EXTRACT_ELEMENT: {
- Known = computeKnownBits(Op.getOperand(0), Depth+1);
+ Known = computeKnownBits(Op.getOperand(0), Depth + 1);
const unsigned Index = Op.getConstantOperandVal(1);
const unsigned EltBitWidth = Op.getValueSizeInBits();
// Remove low part of known bits mask
- Known.Zero = Known.Zero.getHiBits(Known.getBitWidth() - Index * EltBitWidth);
+ Known.Zero =
+ Known.Zero.getHiBits(Known.getBitWidth() - Index * EltBitWidth);
Known.One = Known.One.getHiBits(Known.getBitWidth() - Index * EltBitWidth);
// Remove high part of known bit mask
@@ -4530,7 +4564,8 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
}
/// Convert ConstantRange OverflowResult into SelectionDAG::OverflowKind.
-static SelectionDAG::OverflowKind mapOverflowResult(ConstantRange::OverflowResult OR) {
+static SelectionDAG::OverflowKind
+mapOverflowResult(ConstantRange::OverflowResult OR) {
switch (OR) {
case ConstantRange::OverflowResult::MayOverflow:
return SelectionDAG::OFK_Sometime;
@@ -4933,20 +4968,21 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
}
if (Depth >= MaxRecursionDepth)
- return 1; // Limit search depth.
+ return 1; // Limit search depth.
if (!DemandedElts)
- return 1; // No demanded elts, better to assume we don't know anything.
+ return 1; // No demanded elts, better to assume we don't know anything.
unsigned Opcode = Op.getOpcode();
switch (Opcode) {
- default: break;
+ default:
+ break;
case ISD::AssertSext:
Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
- return VTBits-Tmp+1;
+ return VTBits - Tmp + 1;
case ISD::AssertZext:
Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
- return VTBits-Tmp;
+ return VTBits - Tmp;
case ISD::FREEZE:
if (isGuaranteedNotToBeUndefOrPoison(Op.getOperand(0), DemandedElts,
/*PoisonOnly=*/false))
@@ -5077,12 +5113,12 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
return VTBits - Tmp + 1;
case ISD::SIGN_EXTEND:
Tmp = VTBits - Op.getOperand(0).getScalarValueSizeInBits();
- return ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth+1) + Tmp;
+ return ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1) + Tmp;
case ISD::SIGN_EXTEND_INREG:
// Max of the input and what this extends.
Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getScalarSizeInBits();
- Tmp = VTBits-Tmp+1;
- Tmp2 = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth+1);
+ Tmp = VTBits - Tmp + 1;
+ Tmp2 = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
return std::max(Tmp, Tmp2);
case ISD::SIGN_EXTEND_VECTOR_INREG: {
if (VT.isScalableVector())
@@ -5091,7 +5127,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
EVT SrcVT = Src.getValueType();
APInt DemandedSrcElts = DemandedElts.zext(SrcVT.getVectorNumElements());
Tmp = VTBits - SrcVT.getScalarSizeInBits();
- return ComputeNumSignBits(Src, DemandedSrcElts, Depth+1) + Tmp;
+ return ComputeNumSignBits(Src, DemandedSrcElts, Depth + 1) + Tmp;
}
case ISD::SRA:
Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
@@ -5132,11 +5168,11 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
break;
case ISD::AND:
case ISD::OR:
- case ISD::XOR: // NOT is handled here.
+ case ISD::XOR: // NOT is handled here.
// Logical binary ops preserve the number of sign bits at the worst.
- Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth+1);
+ Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
if (Tmp != 1) {
- Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth+1);
+ Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth + 1);
FirstAnswer = std::min(Tmp, Tmp2);
// We computed what we know about the sign bits as our first
// answer. Now proceed to the generic code that uses
@@ -5146,14 +5182,16 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
case ISD::SELECT:
case ISD::VSELECT:
- Tmp = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth+1);
- if (Tmp == 1) return 1; // Early out.
- Tmp2 = ComputeNumSignBits(Op.getOperand(2), DemandedElts, Depth+1);
+ Tmp = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth + 1);
+ if (Tmp == 1)
+ return 1; // Early out.
+ Tmp2 = ComputeNumSignBits(Op.getOperand(2), DemandedElts, Depth + 1);
return std::min(Tmp, Tmp2);
case ISD::SELECT_CC:
- Tmp = ComputeNumSignBits(Op.getOperand(2), DemandedElts, Depth+1);
- if (Tmp == 1) return 1; // Early out.
- Tmp2 = ComputeNumSignBits(Op.getOperand(3), DemandedElts, Depth+1);
+ Tmp = ComputeNumSignBits(Op.getOperand(2), DemandedElts, Depth + 1);
+ if (Tmp == 1)
+ return 1; // Early out.
+ Tmp2 = ComputeNumSignBits(Op.getOperand(3), DemandedElts, Depth + 1);
return std::min(Tmp, Tmp2);
case ISD::SMIN:
@@ -5179,7 +5217,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
// Fallback - just get the minimum number of sign bits of the operands.
Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
if (Tmp == 1)
- return 1; // Early out.
+ return 1; // Early out.
Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth + 1);
return std::min(Tmp, Tmp2);
}
@@ -5187,7 +5225,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
case ISD::UMAX:
Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
if (Tmp == 1)
- return 1; // Early out.
+ return 1; // Early out.
Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth + 1);
return std::min(Tmp, Tmp2);
case ISD::SSUBO_CARRY:
@@ -5243,14 +5281,16 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
// If we aren't rotating out all of the known-in sign bits, return the
// number that are left. This handles rotl(sext(x), 1) for example.
- if (Tmp > (RotAmt + 1)) return (Tmp - RotAmt);
+ if (Tmp > (RotAmt + 1))
+ return (Tmp - RotAmt);
}
break;
case ISD::ADD:
case ISD::ADDC:
// TODO: Move Operand 1 check before Operand 0 check
Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
- if (Tmp == 1) return 1; // Early out.
+ if (Tmp == 1)
+ return 1; // Early out.
// Special case decrementing a value (ADD X, -1):
if (ConstantSDNode *CRHS =
@@ -5271,14 +5311,16 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
}
Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth + 1);
- if (Tmp2 == 1) return 1; // Early out.
+ if (Tmp2 == 1)
+ return 1; // Early out.
// Add can have at most one carry bit. Thus we know that the output
// is, at worst, one more bit than the inputs.
return std::min(Tmp, Tmp2) - 1;
case ISD::SUB:
Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth + 1);
- if (Tmp2 == 1) return 1; // Early out.
+ if (Tmp2 == 1)
+ return 1; // Early out.
// Handle NEG.
if (ConstantSDNode *CLHS =
@@ -5302,7 +5344,8 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
// Sub can have at most one carry bit. Thus we know that the output
// is, at worst, one more bit than the inputs.
Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
- if (Tmp == 1) return 1; // Early out.
+ if (Tmp == 1)
+ return 1; // Early out.
return std::min(Tmp, Tmp2) - 1;
case ISD::MUL: {
// The output of the Mul can be at most twice the valid bits in the inputs.
@@ -5340,7 +5383,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
case ISD::EXTRACT_ELEMENT: {
if (VT.isScalableVector())
break;
- const int KnownSign = ComputeNumSignBits(Op.getOperand(0), Depth+1);
+ const int KnownSign = ComputeNumSignBits(Op.getOperand(0), Depth + 1);
const int BitWidth = Op.getValueSizeInBits();
const int Items = Op.getOperand(0).getValueSizeInBits() / BitWidth;
@@ -5590,15 +5633,13 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
}
// Allow the target to implement this method for its nodes.
- if (Opcode >= ISD::BUILTIN_OP_END ||
- Opcode == ISD::INTRINSIC_WO_CHAIN ||
- Opcode == ISD::INTRINSIC_W_CHAIN ||
- Opcode == ISD::INTRINSIC_VOID) {
+ if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::INTRINSIC_WO_CHAIN ||
+ Opcode == ISD::INTRINSIC_W_CHAIN || Opcode == ISD::INTRINSIC_VOID) {
// TODO: This can probably be removed once target code is audited. This
// is here purely to reduce patch size and review complexity.
if (!VT.isScalableVector()) {
unsigned NumBits =
- TLI->ComputeNumSignBitsForTargetNode(Op, DemandedElts, *this, Depth);
+ TLI->ComputeNumSignBitsForTargetNode(Op, DemandedElts, *this, Depth);
if (NumBits > 1)
FirstAnswer = std::max(FirstAnswer, NumBits);
}
@@ -6112,6 +6153,16 @@ KnownFPClass SelectionDAG::computeKnownFPClass(SDValue Op,
}
break;
}
+
+ case ISD::AssertNoFPClass: {
+ Known = computeKnownFPClass(Op.getOperand(0), DemandedElts,
+ InterestedClasses, Depth + 1);
+ FPClassTest AssertedClasses =
+ static_cast<FPClassTest>(Op->getConstantOperandVal(1));
+ Known.KnownFPClasses &= ~AssertedClasses;
+ break;
+ }
+
default:
if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::INTRINSIC_WO_CHAIN ||
Opcode == ISD::INTRINSIC_W_CHAIN || Opcode == ISD::INTRINSIC_VOID) {
@@ -6332,8 +6383,7 @@ bool SelectionDAG::isKnownNeverNaN(SDValue Op, const APInt &DemandedElts,
}
bool SelectionDAG::isKnownNeverZeroFloat(SDValue Op) const {
- assert(Op.getValueType().isFloatingPoint() &&
- "Floating point type expected");
+ assert(Op.getValueType().isFloatingPoint() && "Floating point type expected");
// If the value is a constant, we can obviously see if it is a zero or not.
return ISD::matchUnaryFpPredicate(
@@ -6645,12 +6695,14 @@ bool SelectionDAG::canIgnoreSignBitOfZero(SDValue Op) const {
bool SelectionDAG::isEqualTo(SDValue A, SDValue B) const {
// Check the obvious case.
- if (A == B) return true;
+ if (A == B)
+ return true;
// For negative and positive zero.
if (const ConstantFPSDNode *CA = dyn_cast<ConstantFPSDNode>(A))
if (const ConstantFPSDNode *CB = dyn_cast<ConstantFPSDNode>(B))
- if (CA->isZero() && CB->isZero()) return true;
+ if (CA->isZero() && CB->isZero())
+ return true;
// Otherwise they may not be equal.
return false;
@@ -6727,8 +6779,7 @@ static SDValue FoldSTEP_VECTOR(const SDLoc &DL, EVT VT, SDValue Step,
return SDValue();
}
-static SDValue FoldBUILD_VECTOR(const SDLoc &DL, EVT VT,
- ArrayRef<SDValue> Ops,
+static SDValue FoldBUILD_VECTOR(const SDLoc &DL, EVT VT, ArrayRef<SDValue> Ops,
SelectionDAG &DAG) {
int NumOps = Ops.size();
assert(NumOps != 0 && "Can't build an empty vector!");
@@ -6764,8 +6815,7 @@ static SDValue FoldBUILD_VECTOR(const SDLoc &DL, EVT VT,
/// Try to simplify vector concatenation to an input value, undef, or build
/// vector.
static SDValue foldCONCAT_VECTORS(const SDLoc &DL, EVT VT,
- ArrayRef<SDValue> Ops,
- SelectionDAG &DAG) {
+ ArrayRef<SDValue> Ops, SelectionDAG &DAG) {
assert(!Ops.empty() && "Can't concatenate an empty list of vectors!");
assert(llvm::all_of(Ops,
[Ops](SDValue Op) {
@@ -6941,7 +6991,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
case ISD::TokenFactor:
case ISD::MERGE_VALUES:
case ISD::CONCAT_VECTORS:
- return N1; // Factor, merge or concat of one node? No need.
+ return N1; // Factor, merge or concat of one node? No need.
case ISD::BUILD_VECTOR: {
// Attempt to simplify BUILD_VECTOR.
SDValue Ops[] = {N1};
@@ -6949,11 +6999,13 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
return V;
break;
}
- case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node");
+ case ISD::FP_ROUND:
+ llvm_unreachable("Invalid method to make FP_ROUND node");
case ISD::FP_EXTEND:
assert(VT.isFloatingPoint() && N1.getValueType().isFloatingPoint() &&
"Invalid FP cast!");
- if (N1.getValueType() == VT) return N1; // noop conversion.
+ if (N1.getValueType() == VT)
+ return N1; // noop conversion.
assert((!VT.isVector() || VT.getVectorElementCount() ==
N1.getValueType().getVectorElementCount()) &&
"Vector element count mismatch!");
@@ -6978,7 +7030,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
assert(VT.isVector() == N1.getValueType().isVector() &&
"SIGN_EXTEND result type type should be vector iff the operand "
"type is vector!");
- if (N1.getValueType() == VT) return N1; // noop extension
+ if (N1.getValueType() == VT)
+ return N1; // noop extension
assert((!VT.isVector() || VT.getVectorElementCount() ==
N1.getValueType().getVectorElementCount()) &&
"Vector element count mismatch!");
@@ -7019,7 +7072,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
assert(VT.isVector() == N1.getValueType().isVector() &&
"ZERO_EXTEND result type type should be vector iff the operand "
"type is vector!");
- if (N1.getValueType() == VT) return N1; // noop extension
+ if (N1.getValueType() == VT)
+ return N1; // noop extension
assert((!VT.isVector() || VT.getVectorElementCount() ==
N1.getValueType().getVectorElementCount()) &&
"Vector element count mismatch!");
@@ -7064,7 +7118,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
assert(VT.isVector() == N1.getValueType().isVector() &&
"ANY_EXTEND result type type should be vector iff the operand "
"type is vector!");
- if (N1.getValueType() == VT) return N1; // noop extension
+ if (N1.getValueType() == VT)
+ return N1; // noop extension
assert((!VT.isVector() || VT.getVectorElementCount() ==
N1.getValueType().getVectorElementCount()) &&
"Vector element count mismatch!");
@@ -7096,7 +7151,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
assert(VT.isVector() == N1.getValueType().isVector() &&
"TRUNCATE result type type should be vector iff the operand "
"type is vector!");
- if (N1.getValueType() == VT) return N1; // noop truncate
+ if (N1.getValueType() == VT)
+ return N1; // noop truncate
assert((!VT.isVector() || VT.getVectorElementCount() ==
N1.getValueType().getVectorElementCount()) &&
"Vector element count mismatch!");
@@ -7156,7 +7212,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
case ISD::BITCAST:
assert(VT.getSizeInBits() == N1.getValueSizeInBits() &&
"Cannot BITCAST between types of different sizes!");
- if (VT == N1.getValueType()) return N1; // noop conversion.
+ if (VT == N1.getValueType())
+ return N1; // noop conversion.
if (OpOpcode == ISD::BITCAST) // bitconv(bitconv(x)) -> bitconv(x)
return getNode(ISD::BITCAST, DL, VT, N1.getOperand(0));
if (N1.isUndef())
@@ -7263,27 +7320,48 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
static std::optional<APInt> FoldValue(unsigned Opcode, const APInt &C1,
const APInt &C2) {
switch (Opcode) {
- case ISD::ADD: return C1 + C2;
- case ISD::SUB: return C1 - C2;
- case ISD::MUL: return C1 * C2;
- case ISD::AND: return C1 & C2;
- case ISD::OR: return C1 | C2;
- case ISD::XOR: return C1 ^ C2;
- case ISD::SHL: return C1 << C2;
- case ISD::SRL: return C1.lshr(C2);
- case ISD::SRA: return C1.ashr(C2);
- case ISD::ROTL: return C1.rotl(C2);
- case ISD::ROTR: return C1.rotr(C2);
- case ISD::SMIN: return C1.sle(C2) ? C1 : C2;
- case ISD::SMAX: return C1.sge(C2) ? C1 : C2;
- case ISD::UMIN: return C1.ule(C2) ? C1 : C2;
- case ISD::UMAX: return C1.uge(C2) ? C1 : C2;
- case ISD::SADDSAT: return C1.sadd_sat(C2);
- case ISD::UADDSAT: return C1.uadd_sat(C2);
- case ISD::SSUBSAT: return C1.ssub_sat(C2);
- case ISD::USUBSAT: return C1.usub_sat(C2);
- case ISD::SSHLSAT: return C1.sshl_sat(C2);
- case ISD::USHLSAT: return C1.ushl_sat(C2);
+ case ISD::ADD:
+ return C1 + C2;
+ case ISD::SUB:
+ return C1 - C2;
+ case ISD::MUL:
+ return C1 * C2;
+ case ISD::AND:
+ return C1 & C2;
+ case ISD::OR:
+ return C1 | C2;
+ case ISD::XOR:
+ return C1 ^ C2;
+ case ISD::SHL:
+ return C1 << C2;
+ case ISD::SRL:
+ return C1.lshr(C2);
+ case ISD::SRA:
+ return C1.ashr(C2);
+ case ISD::ROTL:
+ return C1.rotl(C2);
+ case ISD::ROTR:
+ return C1.rotr(C2);
+ case ISD::SMIN:
+ return C1.sle(C2) ? C1 : C2;
+ case ISD::SMAX:
+ return C1.sge(C2) ? C1 : C2;
+ case ISD::UMIN:
+ return C1.ule(C2) ? C1 : C2;
+ case ISD::UMAX:
+ return C1.uge(C2) ? C1 : C2;
+ case ISD::SADDSAT:
+ return C1.sadd_sat(C2);
+ case ISD::UADDSAT:
+ return C1.uadd_sat(C2);
+ case ISD::SSUBSAT:
+ return C1.ssub_sat(C2);
+ case ISD::USUBSAT:
+ return C1.usub_sat(C2);
+ case ISD::SSHLSAT:
+ return C1.sshl_sat(C2);
+ case ISD::USHLSAT:
+ return C1.ushl_sat(C2);
case ISD::UDIV:
if (!C2.getBoolValue())
break;
@@ -7356,8 +7434,11 @@ SDValue SelectionDAG::FoldSymbolOffset(unsigned Opcode, EVT VT,
case ISD::ADD:
case ISD::PTRADD:
break;
- case ISD::SUB: Offset = -uint64_t(Offset); break;
- default: return SDValue();
+ case ISD::SUB:
+ Offset = -uint64_t(Offset);
+ break;
+ default:
+ return SDValue();
}
return getGlobalAddress(GA->getGlobal(), SDLoc(C2), VT,
GA->getOffset() + uint64_t(Offset));
@@ -7377,9 +7458,9 @@ bool SelectionDAG::isUndef(unsigned Opcode, ArrayRef<SDValue> Ops) {
return true;
return ISD::isBuildVectorOfConstantSDNodes(Divisor.getNode()) &&
- llvm::any_of(Divisor->op_values(),
- [](SDValue V) { return V.isUndef() ||
- isNullConstant(V); });
+ llvm::any_of(Divisor->op_values(), [](SDValue V) {
+ return V.isUndef() || isNullConstant(V);
+ });
// TODO: Handle signed overflow.
}
// TODO: Handle oversized shifts.
@@ -7904,11 +7985,12 @@ SDValue SelectionDAG::foldConstantFPMath(unsigned Opcode, const SDLoc &DL,
return getConstantFP(minimumnum(C1, C2), DL, VT);
case ISD::FMAXIMUMNUM:
return getConstantFP(maximumnum(C1, C2), DL, VT);
- default: break;
+ default:
+ break;
}
}
if (N1CFP && Opcode == ISD::FP_ROUND) {
- APFloat C1 = N1CFP->getValueAPF(); // make copy
+ APFloat C1 = N1CFP->getValueAPF(); // make copy
bool Unused;
// This can return overflow, underflow, or inexact; we don't care.
// FIXME need to be more flexible about rounding mode.
@@ -8072,8 +8154,7 @@ void SelectionDAG::canonicalizeCommutativeBinop(unsigned Opcode, SDValue &N1,
SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
SDValue N1, SDValue N2, const SDNodeFlags Flags) {
assert(N1.getOpcode() != ISD::DELETED_NODE &&
- N2.getOpcode() != ISD::DELETED_NODE &&
- "Operand is DELETED_NODE!");
+ N2.getOpcode() != ISD::DELETED_NODE && "Operand is DELETED_NODE!");
canonicalizeCommutativeBinop(Opcode, N1, N2);
@@ -8086,14 +8167,18 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
isConstOrConstSplat(N2, /*AllowUndefs*/ false, /*AllowTruncation*/ true);
switch (Opcode) {
- default: break;
+ default:
+ break;
case ISD::TokenFactor:
assert(VT == MVT::Other && N1.getValueType() == MVT::Other &&
N2.getValueType() == MVT::Other && "Invalid token factor!");
// Fold trivial token factors.
- if (N1.getOpcode() == ISD::EntryToken) return N2;
- if (N2.getOpcode() == ISD::EntryToken) return N1;
- if (N1 == N2) return N1;
+ if (N1.getOpcode() == ISD::EntryToken)
+ return N2;
+ if (N2.getOpcode() == ISD::EntryToken)
+ return N1;
+ if (N1 == N2)
+ return N1;
break;
case ISD::BUILD_VECTOR: {
// Attempt to simplify BUILD_VECTOR.
@@ -8110,8 +8195,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
}
case ISD::AND:
assert(VT.isInteger() && "This operator does not apply to FP types!");
- assert(N1.getValueType() == N2.getValueType() &&
- N1.getValueType() == VT && "Binary operator types must match!");
+ assert(N1.getValueType() == N2.getValueType() && N1.getValueType() == VT &&
+ "Binary operator types must match!");
// (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's
// worth handling here.
if (N2CV && N2CV->isZero())
@@ -8125,8 +8210,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
case ISD::PTRADD:
case ISD::SUB:
assert(VT.isInteger() && "This operator does not apply to FP types!");
- assert(N1.getValueType() == N2.getValueType() &&
- N1.getValueType() == VT && "Binary operator types must match!");
+ assert(N1.getValueType() == N2.getValueType() && N1.getValueType() == VT &&
+ "Binary operator types must match!");
// The equal operand types requirement is unnecessarily strong for PTRADD.
// However, the SelectionDAGBuilder does not generate PTRADDs with different
// operand types, and we'd need to re-implement GEP's non-standard wrapping
@@ -8151,8 +8236,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
break;
case ISD::MUL:
assert(VT.isInteger() && "This operator does not apply to FP types!");
- assert(N1.getValueType() == N2.getValueType() &&
- N1.getValueType() == VT && "Binary operator types must match!");
+ assert(N1.getValueType() == N2.getValueType() && N1.getValueType() == VT &&
+ "Binary operator types must match!");
if (VT.getScalarType() == MVT::i1)
return getNode(ISD::AND, DL, VT, N1, N2);
if (N2CV && N2CV->isZero())
@@ -8174,8 +8259,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
case ISD::UADDSAT:
case ISD::USUBSAT:
assert(VT.isInteger() && "This operator does not apply to FP types!");
- assert(N1.getValueType() == N2.getValueType() &&
- N1.getValueType() == VT && "Binary operator types must match!");
+ assert(N1.getValueType() == N2.getValueType() && N1.getValueType() == VT &&
+ "Binary operator types must match!");
if (VT.getScalarType() == MVT::i1) {
// fold (add_sat x, y) -> (or x, y) for bool types.
if (Opcode == ISD::SADDSAT || Opcode == ISD::UADDSAT)
@@ -8201,30 +8286,30 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
case ISD::AVGCEILS:
case ISD::AVGCEILU:
assert(VT.isInteger() && "This operator does not apply to FP types!");
- assert(N1.getValueType() == N2.getValueType() &&
- N1.getValueType() == VT && "Binary operator types must match!");
+ assert(N1.getValueType() == N2.getValueType() && N1.getValueType() == VT &&
+ "Binary operator types must match!");
break;
case ISD::ABDS:
case ISD::ABDU:
assert(VT.isInteger() && "This operator does not apply to FP types!");
- assert(N1.getValueType() == N2.getValueType() &&
- N1.getValueType() == VT && "Binary operator types must match!");
+ assert(N1.getValueType() == N2.getValueType() && N1.getValueType() == VT &&
+ "Binary operator types must match!");
if (VT.getScalarType() == MVT::i1)
return getNode(ISD::XOR, DL, VT, N1, N2);
break;
case ISD::SMIN:
case ISD::UMAX:
assert(VT.isInteger() && "This operator does not apply to FP types!");
- assert(N1.getValueType() == N2.getValueType() &&
- N1.getValueType() == VT && "Binary operator types must match!");
+ assert(N1.getValueType() == N2.getValueType() && N1.getValueType() == VT &&
+ "Binary operator types must match!");
if (VT.getScalarType() == MVT::i1)
return getNode(ISD::OR, DL, VT, N1, N2);
break;
case ISD::SMAX:
case ISD::UMIN:
assert(VT.isInteger() && "This operator does not apply to FP types!");
- assert(N1.getValueType() == N2.getValueType() &&
- N1.getValueType() == VT && "Binary operator types must match!");
+ assert(N1.getValueType() == N2.getValueType() && N1.getValueType() == VT &&
+ "Binary operator types must match!");
if (VT.getScalarType() == MVT::i1)
return getNode(ISD::AND, DL, VT, N1, N2);
break;
@@ -8234,16 +8319,14 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
case ISD::FDIV:
case ISD::FREM:
assert(VT.isFloatingPoint() && "This operator only applies to FP types!");
- assert(N1.getValueType() == N2.getValueType() &&
- N1.getValueType() == VT && "Binary operator types must match!");
+ assert(N1.getValueType() == N2.getValueType() && N1.getValueType() == VT &&
+ "Binary operator types must match!");
if (SDValue V = simplifyFPBinop(Opcode, N1, N2, Flags))
return V;
break;
- case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match.
- assert(N1.getValueType() == VT &&
- N1.getValueType().isFloatingPoint() &&
- N2.getValueType().isFloatingPoint() &&
- "Invalid FCOPYSIGN!");
+ case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match.
+ assert(N1.getValueType() == VT && N1.getValueType().isFloatingPoint() &&
+ N2.getValueType().isFloatingPoint() && "Invalid FCOPYSIGN!");
break;
case ISD::SHL:
if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) {
@@ -8288,7 +8371,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
VT.bitsLE(N1.getValueType()) && N2C &&
(N2C->getZExtValue() == 0 || N2C->getZExtValue() == 1) &&
N2.getOpcode() == ISD::TargetConstant && "Invalid FP_ROUND!");
- if (N1.getValueType() == VT) return N1; // noop conversion.
+ if (N1.getValueType() == VT)
+ return N1; // noop conversion.
break;
case ISD::AssertNoFPClass: {
assert(N1.getValueType().isFloatingPoint() &&
@@ -8311,7 +8395,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
"AssertSExt/AssertZExt type should be the vector element type "
"rather than the vector type!");
assert(EVT.bitsLE(VT.getScalarType()) && "Not extending!");
- if (VT.getScalarType() == EVT) return N1; // noop assertion.
+ if (VT.getScalarType() == EVT)
+ return N1; // noop assertion.
break;
}
case ISD::SIGN_EXTEND_INREG: {
@@ -8326,7 +8411,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
EVT.getVectorElementCount() == VT.getVectorElementCount()) &&
"Vector element counts must match in SIGN_EXTEND_INREG");
assert(EVT.getScalarType().bitsLE(VT.getScalarType()) && "Not extending!");
- if (EVT == VT) return N1; // Not actually extending
+ if (EVT == VT)
+ return N1; // Not actually extending
break;
}
case ISD::FP_TO_SINT_SAT:
@@ -8407,7 +8493,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
if (VT == N1.getOperand(1).getValueType())
return N1.getOperand(1);
if (VT.isFloatingPoint()) {
- assert(VT.getSizeInBits() > N1.getOperand(1).getValueType().getSizeInBits());
+ assert(VT.getSizeInBits() >
+ N1.getOperand(1).getValueType().getSizeInBits());
return getFPExtendOrRound(N1.getOperand(1), DL, VT);
}
return getSExtOrTrunc(N1.getOperand(1), DL, VT);
@@ -8435,8 +8522,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!");
assert(!N1.getValueType().isVector() && !VT.isVector() &&
(N1.getValueType().isInteger() == VT.isInteger()) &&
- N1.getValueType() != VT &&
- "Wrong types for EXTRACT_ELEMENT!");
+ N1.getValueType() != VT && "Wrong types for EXTRACT_ELEMENT!");
// EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding
// 64-bit integers into 32-bit parts. Instead of building the extract of
@@ -8644,8 +8730,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
const SDNodeFlags Flags) {
assert(N1.getOpcode() != ISD::DELETED_NODE &&
N2.getOpcode() != ISD::DELETED_NODE &&
- N3.getOpcode() != ISD::DELETED_NODE &&
- "Operand is DELETED_NODE!");
+ N3.getOpcode() != ISD::DELETED_NODE && "Operand is DELETED_NODE!");
// Perform various simplifications.
switch (Opcode) {
case ISD::BUILD_VECTOR: {
@@ -8902,7 +8987,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
SDValue N1, SDValue N2, SDValue N3, SDValue N4,
const SDNodeFlags Flags) {
- SDValue Ops[] = { N1, N2, N3, N4 };
+ SDValue Ops[] = {N1, N2, N3, N4};
return getNode(Opcode, DL, VT, Ops, Flags);
}
@@ -8917,7 +9002,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
SDValue N1, SDValue N2, SDValue N3, SDValue N4,
SDValue N5, const SDNodeFlags Flags) {
- SDValue Ops[] = { N1, N2, N3, N4, N5 };
+ SDValue Ops[] = {N1, N2, N3, N4, N5};
return getNode(Opcode, DL, VT, Ops, Flags);
}
@@ -8962,7 +9047,8 @@ static SDValue getMemsetValue(SDValue Value, EVT VT, SelectionDAG &DAG,
assert(C->getAPIntValue().getBitWidth() == 8);
APInt Val = APInt::getSplat(NumBits, C->getAPIntValue());
if (VT.isInteger()) {
- bool IsOpaque = VT.getSizeInBits() > 64 ||
+ bool IsOpaque =
+ VT.getSizeInBits() > 64 ||
!DAG.getTargetLoweringInfo().isLegalStoreImmediate(C->getSExtValue());
return DAG.getConstant(Val, dl, VT, false, IsOpaque);
}
@@ -9013,10 +9099,10 @@ static SDValue getMemsetStringVal(EVT VT, const SDLoc &dl, SelectionDAG &DAG,
APInt Val(NumVTBits, 0);
if (DAG.getDataLayout().isLittleEndian()) {
for (unsigned i = 0; i != NumBytes; ++i)
- Val |= (uint64_t)(unsigned char)Slice[i] << i*8;
+ Val |= (uint64_t)(unsigned char)Slice[i] << i * 8;
} else {
for (unsigned i = 0; i != NumBytes; ++i)
- Val |= (uint64_t)(unsigned char)Slice[i] << (NumVTBytes-i-1)*8;
+ Val |= (uint64_t)(unsigned char)Slice[i] << (NumVTBytes - i - 1) * 8;
}
// If the "cost" of materializing the integer immediate is less than the cost
@@ -9076,10 +9162,10 @@ static bool shouldLowerMemFuncForSize(const MachineFunction &MF,
return DAG.shouldOptForSize();
}
-static void chainLoadsAndStoresForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
- SmallVector<SDValue, 32> &OutChains, unsigned From,
- unsigned To, SmallVector<SDValue, 16> &OutLoadChains,
- SmallVector<SDValue, 16> &OutStoreChains) {
+static void chainLoadsAndStoresForMemcpy(
+ SelectionDAG &DAG, const SDLoc &dl, SmallVector<SDValue, 32> &OutChains,
+ unsigned From, unsigned To, SmallVector<SDValue, 16> &OutLoadChains,
+ SmallVector<SDValue, 16> &OutStoreChains) {
assert(OutLoadChains.size() && "Missing loads in memcpy inlining");
assert(OutStoreChains.size() && "Missing stores in memcpy inlining");
SmallVector<SDValue, 16> GluedLoadChains;
@@ -9089,14 +9175,14 @@ static void chainLoadsAndStoresForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
}
// Chain for all loads.
- SDValue LoadToken = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
- GluedLoadChains);
+ SDValue LoadToken =
+ DAG.getNode(ISD::TokenFactor, dl, MVT::Other, GluedLoadChains);
for (unsigned i = From; i < To; ++i) {
StoreSDNode *ST = dyn_cast<StoreSDNode>(OutStoreChains[i]);
- SDValue NewStore = DAG.getTruncStore(LoadToken, dl, ST->getValue(),
- ST->getBasePtr(), ST->getMemoryVT(),
- ST->getMemOperand());
+ SDValue NewStore =
+ DAG.getTruncStore(LoadToken, dl, ST->getValue(), ST->getBasePtr(),
+ ST->getMemoryVT(), ST->getMemOperand());
OutChains.push_back(NewStore);
}
}
@@ -9189,7 +9275,7 @@ static SDValue getMemcpyLoadsAndStores(
if (VTSize > Size) {
// Issuing an unaligned load / store pair that overlaps with the previous
// pair. Adjust the offset accordingly.
- assert(i == NumMemOps-1 && i != 0);
+ assert(i == NumMemOps - 1 && i != 0);
SrcOff -= VTSize - Size;
DstOff -= VTSize - Size;
}
@@ -9256,8 +9342,8 @@ static SDValue getMemcpyLoadsAndStores(
Size -= VTSize;
}
- unsigned GluedLdStLimit = MaxLdStGlue == 0 ?
- TLI.getMaxGluedStoresPerMemcpy() : MaxLdStGlue;
+ unsigned GluedLdStLimit =
+ MaxLdStGlue == 0 ? TLI.getMaxGluedStoresPerMemcpy() : MaxLdStGlue;
unsigned NumLdStInMemcpy = OutStoreChains.size();
if (NumLdStInMemcpy) {
@@ -9273,11 +9359,10 @@ static SDValue getMemcpyLoadsAndStores(
} else {
// Ld/St less than/equal limit set by target.
if (NumLdStInMemcpy <= GluedLdStLimit) {
- chainLoadsAndStoresForMemcpy(DAG, dl, OutChains, 0,
- NumLdStInMemcpy, OutLoadChains,
- OutStoreChains);
+ chainLoadsAndStoresForMemcpy(DAG, dl, OutChains, 0, NumLdStInMemcpy,
+ OutLoadChains, OutStoreChains);
} else {
- unsigned NumberLdChain = NumLdStInMemcpy / GluedLdStLimit;
+ unsigned NumberLdChain = NumLdStInMemcpy / GluedLdStLimit;
unsigned RemainingLdStInMemcpy = NumLdStInMemcpy % GluedLdStLimit;
unsigned GlueIter = 0;
@@ -9561,7 +9646,7 @@ static SDValue getMemsetStores(SelectionDAG &DAG, const SDLoc &dl,
if (VTSize > Size) {
// Issuing an unaligned load / store pair that overlaps with the previous
// pair. Adjust the offset accordingly.
- assert(i == NumMemOps-1 && i != 0);
+ assert(i == NumMemOps - 1 && i != 0);
DstOff -= VTSize - Size;
}
@@ -9808,7 +9893,7 @@ SDValue SelectionDAG::getMemcpy(
.setDiscardResult()
.setTailCall(IsTailCall);
- std::pair<SDValue,SDValue> CallResult = TLI->LowerCallTo(CLI);
+ std::pair<SDValue, SDValue> CallResult = TLI->LowerCallTo(CLI);
return CallResult.second;
}
@@ -9914,7 +9999,7 @@ SDValue SelectionDAG::getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst,
.setDiscardResult()
.setTailCall(IsTailCall);
- std::pair<SDValue,SDValue> CallResult = TLI->LowerCallTo(CLI);
+ std::pair<SDValue, SDValue> CallResult = TLI->LowerCallTo(CLI);
return CallResult.second;
}
@@ -9977,8 +10062,9 @@ SDValue SelectionDAG::getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst,
// Then check to see if we should lower the memset with target-specific
// code. If the target chooses to do this, this is the next best.
if (TSI) {
- SDValue Result = TSI->EmitTargetCodeForMemset(
- *this, dl, Chain, Dst, Src, Size, Alignment, isVol, AlwaysInline, DstPtrInfo);
+ SDValue Result = TSI->EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src,
+ Size, Alignment, isVol,
+ AlwaysInline, DstPtrInfo);
if (Result.getNode())
return Result;
}
@@ -9999,7 +10085,7 @@ SDValue SelectionDAG::getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst,
// Emit a library call.
auto &Ctx = *getContext();
- const auto& DL = getDataLayout();
+ const auto &DL = getDataLayout();
TargetLowering::CallLoweringInfo CLI(*this);
// FIXME: pass in SDLoc
@@ -10088,7 +10174,7 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
dl.getIROrder(), Opcode, VTList, MemVT, MMO, ExtType));
ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
ID.AddInteger(MMO->getFlags());
- void* IP = nullptr;
+ void *IP = nullptr;
if (auto *E = cast_or_null<AtomicSDNode>(FindNodeOrInsertPos(ID, dl, IP))) {
E->refineAlignment(MMO);
E->refineRanges(MMO);
@@ -10140,8 +10226,8 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
EVT VT = Val.getValueType();
- SDVTList VTs = Opcode == ISD::ATOMIC_STORE ? getVTList(MVT::Other) :
- getVTList(VT, MVT::Other);
+ SDVTList VTs = Opcode == ISD::ATOMIC_STORE ? getVTList(MVT::Other)
+ : getVTList(VT, MVT::Other);
SDValue Ops[] = {Chain, Ptr, Val};
return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
}
@@ -10218,7 +10304,7 @@ SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl,
// Memoize the node unless it returns a glue result.
MemIntrinsicSDNode *N;
- if (VTList.VTs[VTList.NumVTs-1] != MVT::Glue) {
+ if (VTList.VTs[VTList.NumVTs - 1] != MVT::Glue) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops);
ID.AddInteger(getSyntheticNodeSubclassData<MemIntrinsicSDNode>(
@@ -10313,8 +10399,7 @@ static MachinePointerInfo InferPointerInfo(const MachinePointerInfo &Info,
FI->getIndex(), Offset);
// If this is (FI+Offset1)+Offset2, we can model it.
- if (Ptr.getOpcode() != ISD::ADD ||
- !isa<ConstantSDNode>(Ptr.getOperand(1)) ||
+ if (Ptr.getOpcode() != ISD::ADD || !isa<ConstantSDNode>(Ptr.getOperand(1)) ||
!isa<FrameIndexSDNode>(Ptr.getOperand(0)))
return Info;
@@ -10346,8 +10431,7 @@ SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
Align Alignment,
MachineMemOperand::Flags MMOFlags,
const AAMDNodes &AAInfo, const MDNode *Ranges) {
- assert(Chain.getValueType() == MVT::Other &&
- "Invalid chain type");
+ assert(Chain.getValueType() == MVT::Other && "Invalid chain type");
MMOFlags |= MachineMemOperand::MOLoad;
assert((MMOFlags & MachineMemOperand::MOStore) == 0);
@@ -10393,9 +10477,9 @@ SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
bool Indexed = AM != ISD::UNINDEXED;
assert((Indexed || Offset.isUndef()) && "Unindexed load with an offset!");
- SDVTList VTs = Indexed ?
- getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other);
- SDValue Ops[] = { Chain, Ptr, Offset };
+ SDVTList VTs = Indexed ? getVTList(VT, Ptr.getValueType(), MVT::Other)
+ : getVTList(VT, MVT::Other);
+ SDValue Ops[] = {Chain, Ptr, Offset};
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::LOAD, VTs, Ops);
ID.AddInteger(MemVT.getRawBits());
@@ -10452,8 +10536,8 @@ SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl,
EVT VT, SDValue Chain, SDValue Ptr, EVT MemVT,
MachineMemOperand *MMO) {
SDValue Undef = getUNDEF(Ptr.getValueType());
- return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef,
- MemVT, MMO);
+ return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, MemVT,
+ MMO);
}
SDValue SelectionDAG::getIndexedLoad(SDValue OrigLoad, const SDLoc &dl,
@@ -10551,8 +10635,7 @@ SDValue SelectionDAG::getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,
EVT SVT, Align Alignment,
MachineMemOperand::Flags MMOFlags,
const AAMDNodes &AAInfo) {
- assert(Chain.getValueType() == MVT::Other &&
- "Invalid chain type");
+ assert(Chain.getValueType() == MVT::Other && "Invalid chain type");
MMOFlags |= MachineMemOperand::MOStore;
assert((MMOFlags & MachineMemOperand::MOLoad) == 0);
@@ -11120,8 +11203,7 @@ SDValue SelectionDAG::getMaskedStore(SDValue Chain, const SDLoc &dl,
MachineMemOperand *MMO,
ISD::MemIndexedMode AM, bool IsTruncating,
bool IsCompressing) {
- assert(Chain.getValueType() == MVT::Other &&
- "Invalid chain type");
+ assert(Chain.getValueType() == MVT::Other && "Invalid chain type");
bool Indexed = AM != ISD::UNINDEXED;
assert((Indexed || Offset.isUndef()) &&
"Unindexed masked store with an offset!");
@@ -11434,8 +11516,8 @@ SDValue SelectionDAG::simplifyFPBinop(unsigned Opcode, SDValue X, SDValue Y,
// operation is poison. That result can be relaxed to undef.
ConstantFPSDNode *XC = isConstOrConstSplatFP(X, /* AllowUndefs */ true);
ConstantFPSDNode *YC = isConstOrConstSplatFP(Y, /* AllowUndefs */ true);
- bool HasNan = (XC && XC->getValueAPF().isNaN()) ||
- (YC && YC->getValueAPF().isNaN());
+ bool HasNan =
+ (XC && XC->getValueAPF().isNaN()) || (YC && YC->getValueAPF().isNaN());
bool HasInf = (XC && XC->getValueAPF().isInfinity()) ||
(YC && YC->getValueAPF().isInfinity());
@@ -11474,18 +11556,23 @@ SDValue SelectionDAG::simplifyFPBinop(unsigned Opcode, SDValue X, SDValue Y,
SDValue SelectionDAG::getVAArg(EVT VT, const SDLoc &dl, SDValue Chain,
SDValue Ptr, SDValue SV, unsigned Align) {
- SDValue Ops[] = { Chain, Ptr, SV, getTargetConstant(Align, dl, MVT::i32) };
+ SDValue Ops[] = {Chain, Ptr, SV, getTargetConstant(Align, dl, MVT::i32)};
return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops);
}
SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
ArrayRef<SDUse> Ops) {
switch (Ops.size()) {
- case 0: return getNode(Opcode, DL, VT);
- case 1: return getNode(Opcode, DL, VT, Ops[0].get());
- case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]);
- case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]);
- default: break;
+ case 0:
+ return getNode(Opcode, DL, VT);
+ case 1:
+ return getNode(Opcode, DL, VT, Ops[0].get());
+ case 2:
+ return getNode(Opcode, DL, VT, Ops[0], Ops[1]);
+ case 3:
+ return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]);
+ default:
+ break;
}
// Copy from an SDUse array into an SDValue array for use with
@@ -11506,21 +11593,26 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
ArrayRef<SDValue> Ops, const SDNodeFlags Flags) {
unsigned NumOps = Ops.size();
switch (NumOps) {
- case 0: return getNode(Opcode, DL, VT);
- case 1: return getNode(Opcode, DL, VT, Ops[0], Flags);
- case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Flags);
- case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2], Flags);
- default: break;
+ case 0:
+ return getNode(Opcode, DL, VT);
+ case 1:
+ return getNode(Opcode, DL, VT, Ops[0], Flags);
+ case 2:
+ return getNode(Opcode, DL, VT, Ops[0], Ops[1], Flags);
+ case 3:
+ return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2], Flags);
+ default:
+ break;
}
#ifndef NDEBUG
for (const auto &Op : Ops)
- assert(Op.getOpcode() != ISD::DELETED_NODE &&
- "Operand is DELETED_NODE!");
+ assert(Op.getOpcode() != ISD::DELETED_NODE && "Operand is DELETED_NODE!");
#endif
switch (Opcode) {
- default: break;
+ default:
+ break;
case ISD::BUILD_VECTOR:
// Attempt to simplify BUILD_VECTOR.
if (SDValue V = FoldBUILD_VECTOR(DL, VT, Ops, *this))
@@ -11645,8 +11737,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
#ifndef NDEBUG
for (const auto &Op : Ops)
- assert(Op.getOpcode() != ISD::DELETED_NODE &&
- "Operand is DELETED_NODE!");
+ assert(Op.getOpcode() != ISD::DELETED_NODE && "Operand is DELETED_NODE!");
#endif
switch (Opcode) {
@@ -11787,7 +11878,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
// Memoize the node unless it returns a glue result.
SDNode *N;
- if (VTList.VTs[VTList.NumVTs-1] != MVT::Glue) {
+ if (VTList.VTs[VTList.NumVTs - 1] != MVT::Glue) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops);
void *IP = nullptr;
@@ -11818,32 +11909,32 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL,
SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
SDValue N1) {
- SDValue Ops[] = { N1 };
+ SDValue Ops[] = {N1};
return getNode(Opcode, DL, VTList, Ops);
}
SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
SDValue N1, SDValue N2) {
- SDValue Ops[] = { N1, N2 };
+ SDValue Ops[] = {N1, N2};
return getNode(Opcode, DL, VTList, Ops);
}
SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
SDValue N1, SDValue N2, SDValue N3) {
- SDValue Ops[] = { N1, N2, N3 };
+ SDValue Ops[] = {N1, N2, N3};
return getNode(Opcode, DL, VTList, Ops);
}
SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
SDValue N1, SDValue N2, SDValue N3, SDValue N4) {
- SDValue Ops[] = { N1, N2, N3, N4 };
+ SDValue Ops[] = {N1, N2, N3, N4};
return getNode(Opcode, DL, VTList, Ops);
}
SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
SDValue N1, SDValue N2, SDValue N3, SDValue N4,
SDValue N5) {
- SDValue Ops[] = { N1, N2, N3, N4, N5 };
+ SDValue Ops[] = {N1, N2, N3, N4, N5};
return getNode(Opcode, DL, VTList, Ops);
}
@@ -11933,7 +12024,6 @@ SDVTList SelectionDAG::getVTList(ArrayRef<EVT> VTs) {
return Result->getSDVTList();
}
-
/// UpdateNodeOperands - *Mutate* the specified node in-place to have the
/// specified operands. If the resultant node already exists in the DAG,
/// this does not modify the specified node, instead it returns the node that
@@ -11944,7 +12034,8 @@ SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op) {
assert(N->getNumOperands() == 1 && "Update with wrong number of operands");
// Check to see if there is no change.
- if (Op == N->getOperand(0)) return N;
+ if (Op == N->getOperand(0))
+ return N;
// See if the modified node already exists.
void *InsertPos = nullptr;
@@ -11961,7 +12052,8 @@ SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op) {
updateDivergence(N);
// If this gets put into a CSE map, add it.
- if (InsertPos) CSEMap.InsertNode(N, InsertPos);
+ if (InsertPos)
+ CSEMap.InsertNode(N, InsertPos);
return N;
}
@@ -11970,7 +12062,7 @@ SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2) {
// Check to see if there is no change.
if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1))
- return N; // No operands changed, just return the input node.
+ return N; // No operands changed, just return the input node.
// See if the modified node already exists.
void *InsertPos = nullptr;
@@ -11990,32 +12082,31 @@ SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2) {
updateDivergence(N);
// If this gets put into a CSE map, add it.
- if (InsertPos) CSEMap.InsertNode(N, InsertPos);
+ if (InsertPos)
+ CSEMap.InsertNode(N, InsertPos);
return N;
}
-SDNode *SelectionDAG::
-UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) {
- SDValue Ops[] = { Op1, Op2, Op3 };
+SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
+ SDValue Op3) {
+ SDValue Ops[] = {Op1, Op2, Op3};
return UpdateNodeOperands(N, Ops);
}
-SDNode *SelectionDAG::
-UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
- SDValue Op3, SDValue Op4) {
- SDValue Ops[] = { Op1, Op2, Op3, Op4 };
+SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
+ SDValue Op3, SDValue Op4) {
+ SDValue Ops[] = {Op1, Op2, Op3, Op4};
return UpdateNodeOperands(N, Ops);
}
-SDNode *SelectionDAG::
-UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
- SDValue Op3, SDValue Op4, SDValue Op5) {
- SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
+SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
+ SDValue Op3, SDValue Op4,
+ SDValue Op5) {
+ SDValue Ops[] = {Op1, Op2, Op3, Op4, Op5};
return UpdateNodeOperands(N, Ops);
}
-SDNode *SelectionDAG::
-UpdateNodeOperands(SDNode *N, ArrayRef<SDValue> Ops) {
+SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, ArrayRef<SDValue> Ops) {
unsigned NumOps = Ops.size();
assert(N->getNumOperands() == NumOps &&
"Update with wrong number of operands");
@@ -12041,7 +12132,8 @@ UpdateNodeOperands(SDNode *N, ArrayRef<SDValue> Ops) {
updateDivergence(N);
// If this gets put into a CSE map, add it.
- if (InsertPos) CSEMap.InsertNode(N, InsertPos);
+ if (InsertPos)
+ CSEMap.InsertNode(N, InsertPos);
return N;
}
@@ -12050,7 +12142,7 @@ UpdateNodeOperands(SDNode *N, ArrayRef<SDValue> Ops) {
void SDNode::DropOperands() {
// Unlike the code in MorphNodeTo that does this, we don't need to
// watch for dead nodes here.
- for (op_iterator I = op_begin(), E = op_end(); I != E; ) {
+ for (op_iterator I = op_begin(), E = op_end(); I != E;) {
SDUse &Use = *I++;
Use.set(SDValue());
}
@@ -12080,70 +12172,65 @@ void SelectionDAG::setNodeMemRefs(MachineSDNode *N,
/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a
/// machine opcode.
///
-SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- EVT VT) {
+SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT) {
SDVTList VTs = getVTList(VT);
return SelectNodeTo(N, MachineOpc, VTs, {});
}
-SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- EVT VT, SDValue Op1) {
+SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT,
+ SDValue Op1) {
SDVTList VTs = getVTList(VT);
- SDValue Ops[] = { Op1 };
+ SDValue Ops[] = {Op1};
return SelectNodeTo(N, MachineOpc, VTs, Ops);
}
-SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- EVT VT, SDValue Op1,
- SDValue Op2) {
+SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT,
+ SDValue Op1, SDValue Op2) {
SDVTList VTs = getVTList(VT);
- SDValue Ops[] = { Op1, Op2 };
+ SDValue Ops[] = {Op1, Op2};
return SelectNodeTo(N, MachineOpc, VTs, Ops);
}
-SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- EVT VT, SDValue Op1,
- SDValue Op2, SDValue Op3) {
+SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT,
+ SDValue Op1, SDValue Op2, SDValue Op3) {
SDVTList VTs = getVTList(VT);
- SDValue Ops[] = { Op1, Op2, Op3 };
+ SDValue Ops[] = {Op1, Op2, Op3};
return SelectNodeTo(N, MachineOpc, VTs, Ops);
}
-SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- EVT VT, ArrayRef<SDValue> Ops) {
+SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT,
+ ArrayRef<SDValue> Ops) {
SDVTList VTs = getVTList(VT);
return SelectNodeTo(N, MachineOpc, VTs, Ops);
}
-SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- EVT VT1, EVT VT2, ArrayRef<SDValue> Ops) {
+SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
+ EVT VT2, ArrayRef<SDValue> Ops) {
SDVTList VTs = getVTList(VT1, VT2);
return SelectNodeTo(N, MachineOpc, VTs, Ops);
}
-SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- EVT VT1, EVT VT2) {
+SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
+ EVT VT2) {
SDVTList VTs = getVTList(VT1, VT2);
return SelectNodeTo(N, MachineOpc, VTs, {});
}
-SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- EVT VT1, EVT VT2, EVT VT3,
- ArrayRef<SDValue> Ops) {
+SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
+ EVT VT2, EVT VT3, ArrayRef<SDValue> Ops) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
return SelectNodeTo(N, MachineOpc, VTs, Ops);
}
-SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- EVT VT1, EVT VT2,
- SDValue Op1, SDValue Op2) {
+SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
+ EVT VT2, SDValue Op1, SDValue Op2) {
SDVTList VTs = getVTList(VT1, VT2);
- SDValue Ops[] = { Op1, Op2 };
+ SDValue Ops[] = {Op1, Op2};
return SelectNodeTo(N, MachineOpc, VTs, Ops);
}
-SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- SDVTList VTs,ArrayRef<SDValue> Ops) {
+SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, SDVTList VTs,
+ ArrayRef<SDValue> Ops) {
SDNode *New = MorphNodeTo(N, ~MachineOpc, VTs, Ops);
// Reset the NodeID to -1.
New->setNodeId(-1);
@@ -12187,11 +12274,11 @@ SDNode *SelectionDAG::UpdateSDLocOnMergeSDNode(SDNode *N, const SDLoc &OLoc) {
/// As a consequence it isn't appropriate to use from within the DAG combiner or
/// the legalizer which maintain worklists that would need to be updated when
/// deleting things.
-SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- SDVTList VTs, ArrayRef<SDValue> Ops) {
+SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs,
+ ArrayRef<SDValue> Ops) {
// If an identical node already exists, use it.
void *IP = nullptr;
- if (VTs.VTs[VTs.NumVTs-1] != MVT::Glue) {
+ if (VTs.VTs[VTs.NumVTs - 1] != MVT::Glue) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opc, VTs, Ops);
if (SDNode *ON = FindNodeOrInsertPos(ID, SDLoc(N), IP))
@@ -12208,8 +12295,8 @@ SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
// Clear the operands list, updating used nodes to remove this from their
// use list. Keep track of any operands that become dead as a result.
- SmallPtrSet<SDNode*, 16> DeadNodeSet;
- for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) {
+ SmallPtrSet<SDNode *, 16> DeadNodeSet;
+ for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E;) {
SDUse &Use = *I++;
SDNode *Used = Use.getNode();
Use.set(SDValue());
@@ -12236,20 +12323,24 @@ SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
}
if (IP)
- CSEMap.InsertNode(N, IP); // Memoize the new node.
+ CSEMap.InsertNode(N, IP); // Memoize the new node.
return N;
}
-SDNode* SelectionDAG::mutateStrictFPToFP(SDNode *Node) {
+SDNode *SelectionDAG::mutateStrictFPToFP(SDNode *Node) {
unsigned OrigOpc = Node->getOpcode();
unsigned NewOpc;
switch (OrigOpc) {
default:
llvm_unreachable("mutateStrictFPToFP called with unexpected opcode!");
#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
- case ISD::STRICT_##DAGN: NewOpc = ISD::DAGN; break;
+ case ISD::STRICT_##DAGN: \
+ NewOpc = ISD::DAGN; \
+ break;
#define CMP_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
- case ISD::STRICT_##DAGN: NewOpc = ISD::SETCC; break;
+ case ISD::STRICT_##DAGN: \
+ NewOpc = ISD::SETCC; \
+ break;
#include "llvm/IR/ConstrainedOps.def"
}
@@ -12297,14 +12388,14 @@ MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
EVT VT, SDValue Op1) {
SDVTList VTs = getVTList(VT);
- SDValue Ops[] = { Op1 };
+ SDValue Ops[] = {Op1};
return getMachineNode(Opcode, dl, VTs, Ops);
}
MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
EVT VT, SDValue Op1, SDValue Op2) {
SDVTList VTs = getVTList(VT);
- SDValue Ops[] = { Op1, Op2 };
+ SDValue Ops[] = {Op1, Op2};
return getMachineNode(Opcode, dl, VTs, Ops);
}
@@ -12312,7 +12403,7 @@ MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
EVT VT, SDValue Op1, SDValue Op2,
SDValue Op3) {
SDVTList VTs = getVTList(VT);
- SDValue Ops[] = { Op1, Op2, Op3 };
+ SDValue Ops[] = {Op1, Op2, Op3};
return getMachineNode(Opcode, dl, VTs, Ops);
}
@@ -12326,7 +12417,7 @@ MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
EVT VT1, EVT VT2, SDValue Op1,
SDValue Op2) {
SDVTList VTs = getVTList(VT1, VT2);
- SDValue Ops[] = { Op1, Op2 };
+ SDValue Ops[] = {Op1, Op2};
return getMachineNode(Opcode, dl, VTs, Ops);
}
@@ -12334,7 +12425,7 @@ MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
EVT VT1, EVT VT2, SDValue Op1,
SDValue Op2, SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2);
- SDValue Ops[] = { Op1, Op2, Op3 };
+ SDValue Ops[] = {Op1, Op2, Op3};
return getMachineNode(Opcode, dl, VTs, Ops);
}
@@ -12349,7 +12440,7 @@ MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
EVT VT1, EVT VT2, EVT VT3,
SDValue Op1, SDValue Op2) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
- SDValue Ops[] = { Op1, Op2 };
+ SDValue Ops[] = {Op1, Op2};
return getMachineNode(Opcode, dl, VTs, Ops);
}
@@ -12358,7 +12449,7 @@ MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
SDValue Op1, SDValue Op2,
SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
- SDValue Ops[] = { Op1, Op2, Op3 };
+ SDValue Ops[] = {Op1, Op2, Op3};
return getMachineNode(Opcode, dl, VTs, Ops);
}
@@ -12379,7 +12470,7 @@ MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &DL,
SDVTList VTs,
ArrayRef<SDValue> Ops) {
- bool DoCSE = VTs.VTs[VTs.NumVTs-1] != MVT::Glue;
+ bool DoCSE = VTs.VTs[VTs.NumVTs - 1] != MVT::Glue;
MachineSDNode *N;
void *IP = nullptr;
@@ -12409,8 +12500,8 @@ MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &DL,
SDValue SelectionDAG::getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT,
SDValue Operand) {
SDValue SRIdxVal = getTargetConstant(SRIdx, DL, MVT::i32);
- SDNode *Subreg = getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
- VT, Operand, SRIdxVal);
+ SDNode *Subreg =
+ getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, VT, Operand, SRIdxVal);
return SDValue(Subreg, 0);
}
@@ -12419,8 +12510,8 @@ SDValue SelectionDAG::getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT,
SDValue SelectionDAG::getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT,
SDValue Operand, SDValue Subreg) {
SDValue SRIdxVal = getTargetConstant(SRIdx, DL, MVT::i32);
- SDNode *Result = getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
- VT, Operand, Subreg, SRIdxVal);
+ SDNode *Result = getMachineNode(TargetOpcode::INSERT_SUBREG, DL, VT, Operand,
+ Subreg, SRIdxVal);
return SDValue(Result, 0);
}
@@ -12768,8 +12859,8 @@ void SelectionDAG::salvageDebugInfo(SDNode &N) {
}
/// Creates a SDDbgLabel node.
-SDDbgLabel *SelectionDAG::getDbgLabel(DILabel *Label,
- const DebugLoc &DL, unsigned O) {
+SDDbgLabel *SelectionDAG::getDbgLabel(DILabel *Label, const DebugLoc &DL,
+ unsigned O) {
assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
"Expected inlined-at fields to agree");
return new (DbgInfo->getAlloc()) SDDbgLabel(Label, DL, O);
@@ -12792,10 +12883,9 @@ class RAUWUpdateListener : public SelectionDAG::DAGUpdateListener {
}
public:
- RAUWUpdateListener(SelectionDAG &d,
- SDNode::use_iterator &ui,
+ RAUWUpdateListener(SelectionDAG &d, SDNode::use_iterator &ui,
SDNode::use_iterator &ue)
- : SelectionDAG::DAGUpdateListener(d), UI(ui), UE(ue) {}
+ : SelectionDAG::DAGUpdateListener(d), UI(ui), UE(ue) {}
};
} // end anonymous namespace
@@ -12917,7 +13007,7 @@ void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To) {
/// This version can replace From with any result values. To must match the
/// number and types of values returned by From.
void SelectionDAG::ReplaceAllUsesWith(SDNode *From, const SDValue *To) {
- if (From->getNumValues() == 1) // Handle the simple case efficiently.
+ if (From->getNumValues() == 1) // Handle the simple case efficiently.
return ReplaceAllUsesWith(SDValue(From, 0), To[0]);
for (unsigned i = 0, e = From->getNumValues(); i != e; ++i) {
@@ -12967,9 +13057,10 @@ void SelectionDAG::ReplaceAllUsesWith(SDNode *From, const SDValue *To) {
/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving
/// uses of other values produced by From.getNode() alone. The Deleted
/// vector is handled the same way as for ReplaceAllUsesWith.
-void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To){
+void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To) {
// Handle the really simple, really trivial case efficiently.
- if (From == To) return;
+ if (From == To)
+ return;
// Handle the simple, trivial, case efficiently.
if (From.getNode()->getNumValues() == 1) {
@@ -13143,8 +13234,7 @@ void SelectionDAG::VerifyDAGDivergence() {
/// may appear in both the From and To list. The Deleted vector is
/// handled the same way as for ReplaceAllUsesWith.
void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From,
- const SDValue *To,
- unsigned Num){
+ const SDValue *To, unsigned Num) {
// Handle the simple, trivial case efficiently.
if (Num == 1)
return ReplaceAllUsesOfValueWith(*From, *To);
@@ -13172,7 +13262,7 @@ void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From,
RAUOVWUpdateListener Listener(*this, Uses);
for (unsigned UseIndex = 0, UseIndexEnd = Uses.size();
- UseIndex != UseIndexEnd; ) {
+ UseIndex != UseIndexEnd;) {
// We know that this user uses some value of From. If it is the right
// value, update it.
SDNode *User = Uses[UseIndex].User;
@@ -13267,7 +13357,8 @@ unsigned SelectionDAG::AssignTopologicalOrder() {
allnodes_iterator I(N);
SDNode *S = &*++I;
dbgs() << "Overran sorted position:\n";
- S->dumprFull(this); dbgs() << "\n";
+ S->dumprFull(this);
+ dbgs() << "\n";
dbgs() << "Checking if this is due to cycles\n";
checkForCycles(this, true);
#endif
@@ -13275,15 +13366,14 @@ unsigned SelectionDAG::AssignTopologicalOrder() {
}
}
- assert(SortedPos == AllNodes.end() &&
- "Topological sort incomplete!");
+ assert(SortedPos == AllNodes.end() && "Topological sort incomplete!");
assert(AllNodes.front().getOpcode() == ISD::EntryToken &&
"First node in topological sort is not the entry token!");
assert(AllNodes.front().getNodeId() == 0 &&
"First node in topological sort has non-zero id!");
assert(AllNodes.front().getNumOperands() == 0 &&
"First node in topological sort has operands!");
- assert(AllNodes.back().getNodeId() == (int)DAGSize-1 &&
+ assert(AllNodes.back().getNodeId() == (int)DAGSize - 1 &&
"Last node in topologic sort has unexpected id!");
assert(AllNodes.back().use_empty() &&
"Last node in topologic sort has users!");
@@ -13381,10 +13471,11 @@ SDValue SelectionDAG::getSymbolFunctionGlobalAddress(SDValue Op,
auto *Function = Module->getFunction(Symbol);
if (OutFunction != nullptr)
- *OutFunction = Function;
+ *OutFunction = Function;
if (Function != nullptr) {
- auto PtrTy = TLI->getPointerTy(getDataLayout(), Function->getAddressSpace());
+ auto PtrTy =
+ TLI->getPointerTy(getDataLayout(), Function->getAddressSpace());
return getGlobalAddress(Function, SDLoc(Op), PtrTy);
}
@@ -13476,11 +13567,9 @@ bool llvm::isNeutralConstant(unsigned Opcode, SDNodeFlags Flags, SDValue V,
// Neutral element for fminnum is NaN, Inf or FLT_MAX, depending on FMF.
EVT VT = V.getValueType();
const fltSemantics &Semantics = VT.getFltSemantics();
- APFloat NeutralAF = !Flags.hasNoNaNs()
- ? APFloat::getQNaN(Semantics)
- : !Flags.hasNoInfs()
- ? APFloat::getInf(Semantics)
- : APFloat::getLargest(Semantics);
+ APFloat NeutralAF = !Flags.hasNoNaNs() ? APFloat::getQNaN(Semantics)
+ : !Flags.hasNoInfs() ? APFloat::getInf(Semantics)
+ : APFloat::getLargest(Semantics);
if (Opcode == ISD::FMAXNUM)
NeutralAF.changeSign();
@@ -13660,9 +13749,7 @@ bool llvm::isZeroOrZeroSplatFP(SDValue N, bool AllowUndefs) {
return C && C->isZero();
}
-HandleSDNode::~HandleSDNode() {
- DropOperands();
-}
+HandleSDNode::~HandleSDNode() { DropOperands(); }
MemSDNode::MemSDNode(
unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT memvt,
@@ -13695,21 +13782,19 @@ MemSDNode::MemSDNode(
/// Profile - Gather unique data for the node.
///
-void SDNode::Profile(FoldingSetNodeID &ID) const {
- AddNodeIDNode(ID, this);
-}
+void SDNode::Profile(FoldingSetNodeID &ID) const { AddNodeIDNode(ID, this); }
namespace {
- struct EVTArray {
- std::vector<EVT> VTs;
+struct EVTArray {
+ std::vector<EVT> VTs;
- EVTArray() {
- VTs.reserve(MVT::VALUETYPE_SIZE);
- for (unsigned i = 0; i < MVT::VALUETYPE_SIZE; ++i)
- VTs.push_back(MVT((MVT::SimpleValueType)i));
- }
- };
+ EVTArray() {
+ VTs.reserve(MVT::VALUETYPE_SIZE);
+ for (unsigned i = 0; i < MVT::VALUETYPE_SIZE; ++i)
+ VTs.push_back(MVT((MVT::SimpleValueType)i));
+ }
+};
} // end anonymous namespace
@@ -13782,11 +13867,13 @@ bool SDNode::isOperandOf(const SDNode *N) const {
/// constraint is necessary to allow transformations like splitting loads.
bool SDValue::reachesChainWithoutSideEffects(SDValue Dest,
unsigned Depth) const {
- if (*this == Dest) return true;
+ if (*this == Dest)
+ return true;
// Don't search too deeply, we just want to be able to see through
// TokenFactor's etc.
- if (Depth == 0) return false;
+ if (Depth == 0)
+ return false;
// If this is a token factor, all inputs to the TF happen in parallel.
if (getOpcode() == ISD::TokenFactor) {
@@ -13813,7 +13900,7 @@ bool SDValue::reachesChainWithoutSideEffects(SDValue Dest,
// Loads don't have side effects, look through them.
if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) {
if (Ld->isUnordered())
- return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1);
+ return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth - 1);
}
return false;
}
@@ -13999,7 +14086,7 @@ SDValue SelectionDAG::UnrollVectorOp(SDNode *N, unsigned ResNE) {
SmallVector<SDValue, 4> Operands(N->getNumOperands());
unsigned i;
- for (i= 0; i != NE; ++i) {
+ for (i = 0; i != NE; ++i) {
for (unsigned j = 0, e = N->getNumOperands(); j != e; ++j) {
SDValue Operand = N->getOperand(j);
EVT OperandVT = Operand.getValueType();
@@ -14015,8 +14102,8 @@ SDValue SelectionDAG::UnrollVectorOp(SDNode *N, unsigned ResNE) {
switch (N->getOpcode()) {
default: {
- Scalars.push_back(getNode(N->getOpcode(), dl, EltVT, Operands,
- N->getFlags()));
+ Scalars.push_back(
+ getNode(N->getOpcode(), dl, EltVT, Operands, N->getFlags()));
break;
}
case ISD::VSELECT:
@@ -14027,15 +14114,14 @@ SDValue SelectionDAG::UnrollVectorOp(SDNode *N, unsigned ResNE) {
case ISD::SRL:
case ISD::ROTL:
case ISD::ROTR:
- Scalars.push_back(getNode(N->getOpcode(), dl, EltVT, Operands[0],
- getShiftAmountOperand(Operands[0].getValueType(),
- Operands[1])));
+ Scalars.push_back(getNode(
+ N->getOpcode(), dl, EltVT, Operands[0],
+ getShiftAmountOperand(Operands[0].getValueType(), Operands[1])));
break;
case ISD::SIGN_EXTEND_INREG: {
EVT ExtVT = cast<VTSDNode>(Operands[1])->getVT().getVectorElementType();
- Scalars.push_back(getNode(N->getOpcode(), dl, EltVT,
- Operands[0],
- getValueType(ExtVT)));
+ Scalars.push_back(
+ getNode(N->getOpcode(), dl, EltVT, Operands[0], getValueType(ExtVT)));
break;
}
case ISD::ADDRSPACECAST: {
@@ -14055,8 +14141,8 @@ SDValue SelectionDAG::UnrollVectorOp(SDNode *N, unsigned ResNE) {
return getBuildVector(VecVT, dl, Scalars);
}
-std::pair<SDValue, SDValue> SelectionDAG::UnrollVectorOverflowOp(
- SDNode *N, unsigned ResNE) {
+std::pair<SDValue, SDValue>
+SelectionDAG::UnrollVectorOverflowOp(SDNode *N, unsigned ResNE) {
unsigned Opcode = N->getOpcode();
assert((Opcode == ISD::UADDO || Opcode == ISD::SADDO ||
Opcode == ISD::USUBO || Opcode == ISD::SSUBO ||
@@ -14087,10 +14173,9 @@ std::pair<SDValue, SDValue> SelectionDAG::UnrollVectorOverflowOp(
SmallVector<SDValue, 8> OvScalars;
for (unsigned i = 0; i < NE; ++i) {
SDValue Res = getNode(Opcode, dl, VTs, LHSScalars[i], RHSScalars[i]);
- SDValue Ov =
- getSelect(dl, OvEltVT, Res.getValue(1),
- getBoolConstant(true, dl, OvEltVT, ResVT),
- getConstant(0, dl, OvEltVT));
+ SDValue Ov = getSelect(dl, OvEltVT, Res.getValue(1),
+ getBoolConstant(true, dl, OvEltVT, ResVT),
+ getConstant(0, dl, OvEltVT));
ResScalars.push_back(Res);
OvScalars.push_back(Ov);
@@ -14228,9 +14313,10 @@ SelectionDAG::GetDependentSplitDestVTs(const EVT &VT, const EVT &EnvVT,
/// SplitVector - Split the vector with EXTRACT_SUBVECTOR and return the
/// low/high part.
-std::pair<SDValue, SDValue>
-SelectionDAG::SplitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT,
- const EVT &HiVT) {
+std::pair<SDValue, SDValue> SelectionDAG::SplitVector(const SDValue &N,
+ const SDLoc &DL,
+ const EVT &LoVT,
+ const EVT &HiVT) {
assert(LoVT.isScalableVector() == HiVT.isScalableVector() &&
LoVT.isScalableVector() == N.getValueType().isScalableVector() &&
"Splitting vector with an invalid mixture of fixed and scalable "
@@ -14553,8 +14639,7 @@ void BuildVectorSDNode::recastRawBits(bool IsLittleEndian,
unsigned SrcEltSizeInBits = SrcBitElements[0].getBitWidth();
assert(((NumSrcOps * SrcEltSizeInBits) % DstEltSizeInBits) == 0 &&
"Invalid bitcast scale");
- assert(NumSrcOps == SrcUndefElements.size() &&
- "Vector size mismatch");
+ assert(NumSrcOps == SrcUndefElements.size() && "Vector size mismatch");
unsigned NumDstOps = (NumSrcOps * SrcEltSizeInBits) / DstEltSizeInBits;
DstUndefElements.clear();
@@ -14702,8 +14787,7 @@ bool SelectionDAG::isConstantIntBuildVectorOrConstantInt(
// Treat a GlobalAddress supporting constant offset folding as a
// constant integer.
if (auto *GA = dyn_cast<GlobalAddressSDNode>(N))
- if (GA->getOpcode() == ISD::GlobalAddress &&
- TLI->isOffsetFoldingLegal(GA))
+ if (GA->getOpcode() == ISD::GlobalAddress && TLI->isOffsetFoldingLegal(GA))
return true;
if ((N.getOpcode() == ISD::SPLAT_VECTOR) &&
@@ -14825,9 +14909,9 @@ SDValue SelectionDAG::getNeutralElement(unsigned Opcode, const SDLoc &DL,
case ISD::FMAXNUM: {
// Neutral element for fminnum is NaN, Inf or FLT_MAX, depending on FMF.
const fltSemantics &Semantics = VT.getFltSemantics();
- APFloat NeutralAF = !Flags.hasNoNaNs() ? APFloat::getQNaN(Semantics) :
- !Flags.hasNoInfs() ? APFloat::getInf(Semantics) :
- APFloat::getLargest(Semantics);
+ APFloat NeutralAF = !Flags.hasNoNaNs() ? APFloat::getQNaN(Semantics)
+ : !Flags.hasNoInfs() ? APFloat::getInf(Semantics)
+ : APFloat::getLargest(Semantics);
if (Opcode == ISD::FMAXNUM)
NeutralAF.changeSign();
@@ -14844,7 +14928,6 @@ SDValue SelectionDAG::getNeutralElement(unsigned Opcode, const SDLoc &DL,
return getConstantFP(NeutralAF, DL, VT);
}
-
}
}
@@ -14984,8 +15067,8 @@ void SelectionDAG::copyExtraInfo(SDNode *From, SDNode *To) {
#ifndef NDEBUG
static void checkForCyclesHelper(const SDNode *N,
- SmallPtrSetImpl<const SDNode*> &Visited,
- SmallPtrSetImpl<const SDNode*> &Checked,
+ SmallPtrSetImpl<const SDNode *> &Visited,
+ SmallPtrSetImpl<const SDNode *> &Checked,
const llvm::SelectionDAG *DAG) {
// If this node has already been checked, don't check it again.
if (Checked.count(N))
@@ -14996,7 +15079,8 @@ static void checkForCyclesHelper(const SDNode *N,
if (!Visited.insert(N).second) {
errs() << "Detected cycle in SelectionDAG\n";
dbgs() << "Offending node:\n";
- N->dumprFull(DAG); dbgs() << "\n";
+ N->dumprFull(DAG);
+ dbgs() << "\n";
abort();
}
@@ -15008,21 +15092,20 @@ static void checkForCyclesHelper(const SDNode *N,
}
#endif
-void llvm::checkForCycles(const llvm::SDNode *N,
- const llvm::SelectionDAG *DAG,
+void llvm::checkForCycles(const llvm::SDNode *N, const llvm::SelectionDAG *DAG,
bool force) {
#ifndef NDEBUG
bool check = force;
#ifdef EXPENSIVE_CHECKS
check = true;
-#endif // EXPENSIVE_CHECKS
+#endif // EXPENSIVE_CHECKS
if (check) {
assert(N && "Checking nonexistent SDNode");
- SmallPtrSet<const SDNode*, 32> visited;
- SmallPtrSet<const SDNode*, 32> checked;
+ SmallPtrSet<const SDNode *, 32> visited;
+ SmallPtrSet<const SDNode *, 32> checked;
checkForCyclesHelper(N, visited, checked, DAG);
}
-#endif // !NDEBUG
+#endif // !NDEBUG
}
void llvm::checkForCycles(const llvm::SelectionDAG *DAG, bool force) {
diff --git a/llvm/test/CodeGen/X86/known-fpclass.ll b/llvm/test/CodeGen/X86/known-fpclass.ll
index 020f0dd5f59d4..2eeefca850a10 100644
--- a/llvm/test/CodeGen/X86/known-fpclass.ll
+++ b/llvm/test/CodeGen/X86/known-fpclass.ll
@@ -29,3 +29,32 @@ define i1 @sqrt_neginf_v4f32(<4 x float> %a0, ptr %p1) {
%res = tail call i1 @llvm.is.fpclass.f32(float %elt, i32 4) ; 0x4 = "neginf"
ret i1 %res
}
+
+define i1 @demanded_elts_safe_lane(float %unknown) {
+; CHECK-LABEL: demanded_elts_safe_lane:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: retq
+ %vec1 = insertelement <2 x float> poison, float %unknown, i32 0
+ %vec2 = insertelement <2 x float> %vec1, float 1.000000e+00, i32 1
+
+ %ext = extractelement <2 x float> %vec2, i32 1
+
+ %cmp = fcmp uno float %ext, 0.000000e+00
+ ret i1 %cmp
+}
+
+define i1 @demanded_elts_unknown_lane(float %unknown) {
+; CHECK-LABEL: demanded_elts_unknown_lane:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vucomiss %xmm0, %xmm0
+; CHECK-NEXT: setp %al
+; CHECK-NEXT: retq
+ %vec1 = insertelement <2 x float> poison, float %unknown, i32 0
+ %vec2 = insertelement <2 x float> %vec1, float 1.000000e+00, i32 1
+
+ %ext = extractelement <2 x float> %vec2, i32 0
+
+ %cmp = fcmp uno float %ext, 0.000000e+00
+ ret i1 %cmp
+}
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