[llvm] [RISCV] Check EnsureWholeVectorRegisterMoveValidVTYPE in RISCVInsertVSETVLI::transferBefore. (PR #190022)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/190022

Fixes #189786

>From 46ae04f6261826bda6faddc71428bbecfb319e95 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 1 Apr 2026 11:47:58 -0700
Subject: [PATCH 1/2] Pre-commit test

---
 .../rvv/vsetvli-insert-whole-reg-move.ll      | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll

diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll
new file mode 100644
index 0000000000000..82134b6a631fa
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s --check-prefix=ENABLE
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v -riscv-insert-vsetvli-whole-vector-register-move-valid-vtype=false | FileCheck %s --check-prefix=DISABLE
+
+define <vscale x 8 x i8>  @foo(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2) nounwind {
+; ENABLE-LABEL: foo:
+; ENABLE:       # %bb.0: # %entry
+; ENABLE-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
+; ENABLE-NEXT:    vmv1r.v v8, v9
+; ENABLE-NEXT:    vmadd.vv v8, v9, v9
+; ENABLE-NEXT:    ret
+;
+; DISABLE-LABEL: foo:
+; DISABLE:       # %bb.0: # %entry
+; DISABLE-NEXT:    vmv1r.v v8, v9
+; DISABLE-NEXT:    vmadd.vv v8, v9, v9
+; DISABLE-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %1,
+    i64 1, i64 1)
+
+  ret <vscale x 8 x i8> %a
+}

>From 294750f666d861d3186cf714df8ba44f2f7bd887 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 1 Apr 2026 11:50:09 -0700
Subject: [PATCH 2/2] [RISCV] Check EnsureWholeVectorRegisterMoveValidVTYPE in
 RISCVInsertVSETVLI::transferBefore.

Fixes #189786
---
 llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp                 | 3 ++-
 llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 2569954d62eb0..8a5ac3363b905 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -314,7 +314,8 @@ static VSETVLIInfo adjustIncoming(const VSETVLIInfo &PrevInfo,
 // legal for MI, but may not be the state requested by MI.
 void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
                                         const MachineInstr &MI) const {
-  if (RISCV::isVectorCopy(ST->getRegisterInfo(), MI) &&
+  if (EnsureWholeVectorRegisterMoveValidVTYPE &&
+      RISCV::isVectorCopy(ST->getRegisterInfo(), MI) &&
       (Info.isUnknown() || !Info.isValid() || Info.hasSEWLMULRatioOnly())) {
     // Use an arbitrary but valid AVL and VTYPE so vill will be cleared. It may
     // be coalesced into another vsetvli since we won't demand any fields.
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll
index 82134b6a631fa..9e77ef3c85462 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll
@@ -13,6 +13,7 @@ define <vscale x 8 x i8>  @foo(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vsca
 ; DISABLE-LABEL: foo:
 ; DISABLE:       # %bb.0: # %entry
 ; DISABLE-NEXT:    vmv1r.v v8, v9
+; DISABLE-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
 ; DISABLE-NEXT:    vmadd.vv v8, v9, v9
 ; DISABLE-NEXT:    ret
 entry: