[llvm] [AArch64][SelectionDAG] use fmov for constant forming of {1.0,0.0} (PR #189921)

[Eli Friedman via llvm-commits]

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@@ -329,3 +329,69 @@ define <4 x bfloat> @negzero_v4bf16(<4 x bfloat> %a) {
 ; CHECK-NEXT:    ret
   ret <4 x bfloat> <bfloat -0.0, bfloat -0.0, bfloat -0.0, bfloat -0.0>
 }
+
+; Test that BUILD_VECTOR with an FP constant in lane 0 and +0.0 in upper lanes
+; lowers to a scalar FMOV. On AArch64, writing a scalar FP register zeroes the
+; upper bits of the enclosing vector register.
+
+define <2 x float> @fmov_lane0_zero_upper_v2f32() {
+; CHECK-LABEL: fmov_lane0_zero_upper_v2f32:
+; CHECK:       // %bb.0:
+; CHECK-SD-NEXT:    fmov s0, #1.00000000
+; CHECK-GI-NEXT:    adrp x8, .LCPI23_0
+; CHECK-GI-NEXT:    ldr d0, [x8, :lo12:.LCPI23_0]
+; CHECK-NEXT:    ret
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efriedma-quic wrote:

Please use update_llc_test_checks.py to update CHECK lines.

https://github.com/llvm/llvm-project/pull/189921