[llvm] [DAG] computeKnownFPClass - add ISD::SPLAT_VECTOR handling (PR #189780)

[Kartik Ohlan via llvm-commits]

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@@ -0,0 +1,104 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+d -target-abi lp64d < %s | FileCheck %s
+
+define i1 @isinf_f32(float %x) {
+; CHECK-LABEL: isinf_f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fsqrt.s fa5, fa0
+; CHECK-NEXT:    fclass.s a0, fa5
+; CHECK-NEXT:    andi a0, a0, 129
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    ret
+  %sqr = call nsz ninf float @llvm.sqrt.f32(float %x)
+  %res = tail call i1 @llvm.is.fpclass.f32(float %sqr, i32 516)
+  ret i1 %res
+}
+
+define i1 @isnan_f64(double %x) {
+; CHECK-LABEL: isnan_f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fsqrt.d fa5, fa0
+; CHECK-NEXT:    fclass.d a0, fa5
+; CHECK-NEXT:    andi a0, a0, 768
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    ret
+  %sqr = call nsz ninf double @llvm.sqrt.f64(double %x)
+  %res = tail call i1 @llvm.is.fpclass.f64(double %sqr, i32 3)
+  ret i1 %res
+}
+
+define <4 x i1> @isinf_v4f32(<4 x float> %x) {
+; CHECK-LABEL: isinf_v4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT:    vfsqrt.v v8, v8
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 129
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %sqr = call nsz ninf <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
+  %res = tail call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %sqr, i32 516)
+  ret <4 x i1> %res
+}
+
+define <vscale x 4 x i1> @isinf_nxv4f32(<vscale x 4 x float> %x) {
+; CHECK-LABEL: isinf_nxv4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vfsqrt.v v8, v8
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 129
+; CHECK-NEXT:    vand.vx v8, v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %sqr = call nsz ninf <vscale x 4 x float> @llvm.sqrt.nxv4f32(<vscale x 4 x float> %x)
+  %res = tail call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %sqr, i32 516)
+  ret <vscale x 4 x i1> %res
+}
+
+
+define <vscale x 4 x i1> @test_splat_is_pos_normal() {
+; CHECK-LABEL: test_splat_is_pos_normal:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 260096
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    li a0, 32
+; CHECK-NEXT:    vmseq.vx v0, v8, a0
+; CHECK-NEXT:    ret
+  %ins   = insertelement <vscale x 4 x float> poison, float 1.0, i64 0
+  %splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
+  %res   = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %splat, i32 128)
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Ko496-glitch wrote:

got it, thanks !

https://github.com/llvm/llvm-project/pull/189780