[llvm] [RISCV][MCA] Update sifive-p670 tests to consume input files instead. NFC (PR #189785)
Min-Yih Hsu via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 1 09:59:32 PDT 2026
https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/189785
>From 2da51ebd297c03fe986f40be50e004d61d3d7a81 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Tue, 31 Mar 2026 18:15:15 -0700
Subject: [PATCH 1/2] [RISCV][MCA] Update sifive-p670 tests to consume input
files instead
---
.../llvm-mca/RISCV/SiFiveP600/atomic.test | 237 +
.../tools/llvm-mca/RISCV/SiFiveP600/div.s | 832 ---
.../RISCV/SiFiveP600/floating-point.test | 181 +
.../llvm-mca/RISCV/SiFiveP600/integer.test | 173 +
.../tools/llvm-mca/RISCV/SiFiveP600/load.s | 64 -
.../tools/llvm-mca/RISCV/SiFiveP600/mask.s | 129 -
.../llvm-mca/RISCV/SiFiveP600/mul-cpop.s | 63 -
.../RISCV/SiFiveP600/mul-div-rv32.test | 77 +
.../llvm-mca/RISCV/SiFiveP600/mul-div.test | 87 +
.../RISCV/SiFiveP600/rvv/arithmetic.test | 4541 ++++++++++++++++
.../RISCV/SiFiveP600/rvv/bitwise.test | 2893 ++++++++++
.../RISCV/SiFiveP600/rvv/comparison.test | 1821 +++++++
.../RISCV/SiFiveP600/rvv/conversion.test | 1185 +++++
.../llvm-mca/RISCV/SiFiveP600/rvv/fma.test | 1473 +++++
.../llvm-mca/RISCV/SiFiveP600/rvv/fp.test | 3721 +++++++++++++
.../llvm-mca/RISCV/SiFiveP600/rvv/mask.test | 1265 +++++
.../llvm-mca/RISCV/SiFiveP600/rvv/minmax.test | 765 +++
.../RISCV/SiFiveP600/rvv/mul-div.test | 2005 +++++++
.../RISCV/SiFiveP600/rvv/permutation.test | 2349 ++++++++
.../RISCV/SiFiveP600/rvv/reduction.test | 1237 +++++
.../RISCV/SiFiveP600/rvv/vle-vse-vlm.test | 381 ++
.../RISCV/SiFiveP600/rvv/vlse-vsse.test | 237 +
.../RISCV/SiFiveP600/rvv/vlseg-vsseg.test | 3141 +++++++++++
.../RISCV/SiFiveP600/rvv/vlxe-vsxe.test | 413 ++
.../RISCV/SiFiveP600/{ => rvv}/zvbb.s | 0
.../llvm-mca/RISCV/SiFiveP600/rvv/zvbc.test | 101 +
.../RISCV/SiFiveP600/{ => rvv}/zvkg.s | 0
.../RISCV/SiFiveP600/{ => rvv}/zvkned.s | 0
.../RISCV/SiFiveP600/{ => rvv}/zvknhb.s | 0
.../RISCV/SiFiveP600/{ => rvv}/zvksed.s | 0
.../RISCV/SiFiveP600/{ => rvv}/zvksh.s | 0
.../llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s | 545 --
.../llvm-mca/RISCV/SiFiveP600/vlse-vsse.s | 319 --
.../llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s | 4730 -----------------
.../llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s | 591 --
.../tools/llvm-mca/RISCV/SiFiveP600/vmv.s | 816 ---
.../tools/llvm-mca/RISCV/SiFiveP600/zba.test | 77 +
.../tools/llvm-mca/RISCV/SiFiveP600/zbb.test | 109 +
.../tools/llvm-mca/RISCV/SiFiveP600/zbs.test | 77 +
.../llvm-mca/RISCV/SiFiveP600/zfhmin.test | 81 +
.../tools/llvm-mca/RISCV/SiFiveP600/zvbc.s | 113 -
41 files changed, 28627 insertions(+), 8202 deletions(-)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/atomic.test
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/div.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/floating-point.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/integer.test
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/load.s
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mask.s
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-cpop.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-div-rv32.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-div.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/arithmetic.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/bitwise.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/comparison.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/conversion.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/fma.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/fp.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/mask.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/minmax.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/mul-div.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/permutation.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/reduction.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vle-vse-vlm.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlse-vsse.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlseg-vsseg.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlxe-vsxe.test
rename llvm/test/tools/llvm-mca/RISCV/SiFiveP600/{ => rvv}/zvbb.s (100%)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvbc.test
rename llvm/test/tools/llvm-mca/RISCV/SiFiveP600/{ => rvv}/zvkg.s (100%)
rename llvm/test/tools/llvm-mca/RISCV/SiFiveP600/{ => rvv}/zvkned.s (100%)
rename llvm/test/tools/llvm-mca/RISCV/SiFiveP600/{ => rvv}/zvknhb.s (100%)
rename llvm/test/tools/llvm-mca/RISCV/SiFiveP600/{ => rvv}/zvksed.s (100%)
rename llvm/test/tools/llvm-mca/RISCV/SiFiveP600/{ => rvv}/zvksh.s (100%)
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vmv.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zba.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zbb.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zbs.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zfhmin.test
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/atomic.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/atomic.test
new file mode 100644
index 0000000000000..6cfaff890e398
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/atomic.test
@@ -0,0 +1,237 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../Inputs/atomic.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 3 0.50 * 3 SiFiveP600LDST LR_W lr.w t0, (t1)
+# CHECK-NEXT: 1 3 0.50 * 3 SiFiveP600LDST LR_W_AQ lr.w.aq t1, (t2)
+# CHECK-NEXT: 1 3 0.50 * 3 SiFiveP600LDST LR_W_RL lr.w.rl t2, (t3)
+# CHECK-NEXT: 1 3 0.50 * 3 SiFiveP600LDST LR_W_AQRL lr.w.aqrl t3, (t4)
+# CHECK-NEXT: 1 3 0.50 * 3 SiFiveP600LDST SC_W sc.w t6, t5, (t4)
+# CHECK-NEXT: 1 3 0.50 * 3 SiFiveP600LDST SC_W_AQ sc.w.aq t5, t4, (t3)
+# CHECK-NEXT: 1 3 0.50 * 3 SiFiveP600LDST SC_W_RL sc.w.rl t4, t3, (t2)
+# CHECK-NEXT: 1 3 0.50 * 3 SiFiveP600LDST SC_W_AQRL sc.w.aqrl t3, t2, (t1)
+# CHECK-NEXT: 1 3 0.50 * 3 SiFiveP600LDST LR_D lr.d t0, (t1)
+# CHECK-NEXT: 1 3 0.50 * 3 SiFiveP600LDST LR_D_AQ lr.d.aq t1, (t2)
+# CHECK-NEXT: 1 3 0.50 * 3 SiFiveP600LDST LR_D_RL lr.d.rl t2, (t3)
+# CHECK-NEXT: 1 3 0.50 * 3 SiFiveP600LDST LR_D_AQRL lr.d.aqrl t3, (t4)
+# CHECK-NEXT: 1 3 0.50 * 3 SiFiveP600LDST SC_D sc.d t6, t5, (t4)
+# CHECK-NEXT: 1 3 0.50 * 3 SiFiveP600LDST SC_D_AQ sc.d.aq t5, t4, (t3)
+# CHECK-NEXT: 1 3 0.50 * 3 SiFiveP600LDST SC_D_RL sc.d.rl t4, t3, (t2)
+# CHECK-NEXT: 1 3 0.50 * 3 SiFiveP600LDST SC_D_AQRL sc.d.aqrl t3, t2, (t1)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOSWAP_W amoswap.w a4, ra, (s0)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOADD_W amoadd.w a1, a2, (a3)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOXOR_W amoxor.w a2, a3, (a4)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOAND_W amoand.w a3, a4, (a5)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOOR_W amoor.w a4, a5, (a6)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMIN_W amomin.w a5, a6, (a7)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMAX_W amomax.w s7, s6, (s5)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMINU_W amominu.w s6, s5, (s4)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMAXU_W amomaxu.w s5, s4, (s3)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOSWAP_W_AQ amoswap.w.aq a4, ra, (s0)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOADD_W_AQ amoadd.w.aq a1, a2, (a3)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOXOR_W_AQ amoxor.w.aq a2, a3, (a4)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOAND_W_AQ amoand.w.aq a3, a4, (a5)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOOR_W_AQ amoor.w.aq a4, a5, (a6)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMIN_W_AQ amomin.w.aq a5, a6, (a7)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMAX_W_AQ amomax.w.aq s7, s6, (s5)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMINU_W_AQ amominu.w.aq s6, s5, (s4)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMAXU_W_AQ amomaxu.w.aq s5, s4, (s3)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOSWAP_W_RL amoswap.w.rl a4, ra, (s0)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOADD_W_RL amoadd.w.rl a1, a2, (a3)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOXOR_W_RL amoxor.w.rl a2, a3, (a4)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOAND_W_RL amoand.w.rl a3, a4, (a5)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOOR_W_RL amoor.w.rl a4, a5, (a6)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMIN_W_RL amomin.w.rl a5, a6, (a7)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMAX_W_RL amomax.w.rl s7, s6, (s5)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMINU_W_RL amominu.w.rl s6, s5, (s4)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMAXU_W_RL amomaxu.w.rl s5, s4, (s3)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOSWAP_W_AQRL amoswap.w.aqrl a4, ra, (s0)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOADD_W_AQRL amoadd.w.aqrl a1, a2, (a3)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOXOR_W_AQRL amoxor.w.aqrl a2, a3, (a4)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOAND_W_AQRL amoand.w.aqrl a3, a4, (a5)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOOR_W_AQRL amoor.w.aqrl a4, a5, (a6)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMIN_W_AQRL amomin.w.aqrl a5, a6, (a7)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMAX_W_AQRL amomax.w.aqrl s7, s6, (s5)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMINU_W_AQRL amominu.w.aqrl s6, s5, (s4)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMAXU_W_AQRL amomaxu.w.aqrl s5, s4, (s3)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOSWAP_D amoswap.d a4, ra, (s0)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOADD_D amoadd.d a1, a2, (a3)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOXOR_D amoxor.d a2, a3, (a4)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOAND_D amoand.d a3, a4, (a5)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOOR_D amoor.d a4, a5, (a6)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMIN_D amomin.d a5, a6, (a7)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMAX_D amomax.d s7, s6, (s5)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMINU_D amominu.d s6, s5, (s4)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMAXU_D amomaxu.d s5, s4, (s3)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOSWAP_D_AQ amoswap.d.aq a4, ra, (s0)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOADD_D_AQ amoadd.d.aq a1, a2, (a3)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOXOR_D_AQ amoxor.d.aq a2, a3, (a4)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOAND_D_AQ amoand.d.aq a3, a4, (a5)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOOR_D_AQ amoor.d.aq a4, a5, (a6)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMIN_D_AQ amomin.d.aq a5, a6, (a7)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMAX_D_AQ amomax.d.aq s7, s6, (s5)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMINU_D_AQ amominu.d.aq s6, s5, (s4)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMAXU_D_AQ amomaxu.d.aq s5, s4, (s3)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOSWAP_D_RL amoswap.d.rl a4, ra, (s0)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOADD_D_RL amoadd.d.rl a1, a2, (a3)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOXOR_D_RL amoxor.d.rl a2, a3, (a4)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOAND_D_RL amoand.d.rl a3, a4, (a5)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOOR_D_RL amoor.d.rl a4, a5, (a6)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMIN_D_RL amomin.d.rl a5, a6, (a7)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMAX_D_RL amomax.d.rl s7, s6, (s5)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMINU_D_RL amominu.d.rl s6, s5, (s4)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMAXU_D_RL amomaxu.d.rl s5, s4, (s3)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOSWAP_D_AQRL amoswap.d.aqrl a4, ra, (s0)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOADD_D_AQRL amoadd.d.aqrl a1, a2, (a3)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOXOR_D_AQRL amoxor.d.aqrl a2, a3, (a4)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOAND_D_AQRL amoand.d.aqrl a3, a4, (a5)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOOR_D_AQRL amoor.d.aqrl a4, a5, (a6)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMIN_D_AQRL amomin.d.aqrl a5, a6, (a7)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMAX_D_AQRL amomax.d.aqrl s7, s6, (s5)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMINU_D_AQRL amominu.d.aqrl s6, s5, (s4)
+# CHECK-NEXT: 1 3 0.50 * * 3 SiFiveP600LDST AMOMAXU_D_AQRL amomaxu.d.aqrl s5, s4, (s3)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - - - - - 44.00 44.00 - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lr.w t0, (t1)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lr.w.aq t1, (t2)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lr.w.rl t2, (t3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lr.w.aqrl t3, (t4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - sc.w t6, t5, (t4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - sc.w.aq t5, t4, (t3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - sc.w.rl t4, t3, (t2)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - sc.w.aqrl t3, t2, (t1)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lr.d t0, (t1)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lr.d.aq t1, (t2)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lr.d.rl t2, (t3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lr.d.aqrl t3, (t4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - sc.d t6, t5, (t4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - sc.d.aq t5, t4, (t3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - sc.d.rl t4, t3, (t2)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - sc.d.aqrl t3, t2, (t1)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoswap.w a4, ra, (s0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoadd.w a1, a2, (a3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoxor.w a2, a3, (a4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoand.w a3, a4, (a5)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoor.w a4, a5, (a6)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomin.w a5, a6, (a7)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomax.w s7, s6, (s5)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amominu.w s6, s5, (s4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomaxu.w s5, s4, (s3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoswap.w.aq a4, ra, (s0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoadd.w.aq a1, a2, (a3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoxor.w.aq a2, a3, (a4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoand.w.aq a3, a4, (a5)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoor.w.aq a4, a5, (a6)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomin.w.aq a5, a6, (a7)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomax.w.aq s7, s6, (s5)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amominu.w.aq s6, s5, (s4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomaxu.w.aq s5, s4, (s3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoswap.w.rl a4, ra, (s0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoadd.w.rl a1, a2, (a3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoxor.w.rl a2, a3, (a4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoand.w.rl a3, a4, (a5)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoor.w.rl a4, a5, (a6)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomin.w.rl a5, a6, (a7)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomax.w.rl s7, s6, (s5)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amominu.w.rl s6, s5, (s4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomaxu.w.rl s5, s4, (s3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoswap.w.aqrl a4, ra, (s0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoadd.w.aqrl a1, a2, (a3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoxor.w.aqrl a2, a3, (a4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoand.w.aqrl a3, a4, (a5)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoor.w.aqrl a4, a5, (a6)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomin.w.aqrl a5, a6, (a7)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomax.w.aqrl s7, s6, (s5)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amominu.w.aqrl s6, s5, (s4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomaxu.w.aqrl s5, s4, (s3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoswap.d a4, ra, (s0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoadd.d a1, a2, (a3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoxor.d a2, a3, (a4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoand.d a3, a4, (a5)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoor.d a4, a5, (a6)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomin.d a5, a6, (a7)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomax.d s7, s6, (s5)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amominu.d s6, s5, (s4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomaxu.d s5, s4, (s3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoswap.d.aq a4, ra, (s0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoadd.d.aq a1, a2, (a3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoxor.d.aq a2, a3, (a4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoand.d.aq a3, a4, (a5)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoor.d.aq a4, a5, (a6)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomin.d.aq a5, a6, (a7)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomax.d.aq s7, s6, (s5)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amominu.d.aq s6, s5, (s4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomaxu.d.aq s5, s4, (s3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoswap.d.rl a4, ra, (s0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoadd.d.rl a1, a2, (a3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoxor.d.rl a2, a3, (a4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoand.d.rl a3, a4, (a5)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoor.d.rl a4, a5, (a6)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomin.d.rl a5, a6, (a7)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomax.d.rl s7, s6, (s5)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amominu.d.rl s6, s5, (s4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomaxu.d.rl s5, s4, (s3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoswap.d.aqrl a4, ra, (s0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoadd.d.aqrl a1, a2, (a3)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoxor.d.aqrl a2, a3, (a4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoand.d.aqrl a3, a4, (a5)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amoor.d.aqrl a4, a5, (a6)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomin.d.aqrl a5, a6, (a7)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomax.d.aqrl s7, s6, (s5)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amominu.d.aqrl s6, s5, (s4)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - amomaxu.d.aqrl s5, s4, (s3)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/div.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/div.s
deleted file mode 100644
index 83de52b3c2cbc..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/div.s
+++ /dev/null
@@ -1,832 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, mf4, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, mf2, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m1, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m1, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m2, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m4, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m8, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, mf4, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, mf2, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m1, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m1, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m2, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m4, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m8, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, mf2, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m1, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m1, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m2, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m4, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m8, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m1, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m1, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m2, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m4, tu, mu
-vdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m8, tu, mu
-vdiv.vv v8, v16, v24
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e8, mf4, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e8, mf2, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e8, m1, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e8, m1, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e8, m2, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e8, m4, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e8, m8, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e16, mf4, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e16, mf2, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e16, m1, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e16, m1, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e16, m2, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e16, m4, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e16, m8, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e32, mf2, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e32, m1, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e32, m1, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e32, m2, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e32, m4, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e32, m8, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e64, m1, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e64, m1, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e64, m2, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e64, m4, tu, mu
-vdiv.vx v8, v16, a0
-vsetvli zero, zero, e64, m8, tu, mu
-vdiv.vx v8, v16, a0
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, mf4, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, mf2, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m1, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m1, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m2, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m4, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e8, m8, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, mf4, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, mf2, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m1, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m1, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m2, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m4, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e16, m8, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, mf2, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m1, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m1, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m2, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m4, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e32, m8, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m1, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m1, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m2, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m4, tu, mu
-vfdiv.vv v8, v16, v24
-vsetvli zero, zero, e64, m8, tu, mu
-vfdiv.vv v8, v16, v24
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e8, mf4, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e8, mf2, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e8, m1, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e8, m1, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e8, m2, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e8, m4, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e8, m8, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e16, mf4, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e16, mf2, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e16, m1, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e16, m1, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e16, m2, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e16, m4, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e16, m8, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e32, mf2, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e32, m1, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e32, m1, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e32, m2, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e32, m4, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e32, m8, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e64, m1, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e64, m1, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e64, m2, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e64, m4, tu, mu
-vfdiv.vf v8, v16, fa0
-vsetvli zero, zero, e64, m8, tu, mu
-vfdiv.vf v8, v16, fa0
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e8, m2, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e8, m4, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e8, m8, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e16, m2, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e16, m4, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e16, m8, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e32, m2, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e32, m4, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e32, m8, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e64, m2, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e64, m4, tu, mu
-vfsqrt.v v8, v16
-vsetvli zero, zero, e64, m8, tu, mu
-vfsqrt.v v8, v16
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 260
-# CHECK-NEXT: Total Cycles: 10243
-# CHECK-NEXT: Total uOps: 260
-
-# CHECK: Dispatch Width: 4
-# CHECK-NEXT: uOps Per Cycle: 0.03
-# CHECK-NEXT: IPC: 0.03
-# CHECK-NEXT: Block RThroughput: 10185.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 102 102.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 204 204.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 408 408.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 45 45.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 45 45.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 45 45.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 45 45.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 90 90.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 180 180.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 360 360.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 42 42.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 42 42.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 42 42.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 84 84.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 168 168.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 336 336.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 72 72.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 72 72.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 144 144.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 288 288.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 576 576.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 51 51.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 102 102.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 204 204.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 408 408.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 45 45.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 45 45.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 45 45.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 45 45.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 90 90.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 180 180.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 360 360.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 42 42.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 42 42.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 42 42.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 84 84.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 168 168.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 336 336.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 72 72.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 72 72.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 144 144.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 288 288.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 576 576.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 58 58.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 116 116.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 50 50.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 100 100.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 200 200.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 37 37.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 37 37.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 74 74.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 148 148.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 296 296.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 58 58.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 116 116.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 50 50.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 100 100.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 200 200.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 37 37.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 37 37.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 74 74.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 148 148.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 296 296.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 29 29.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 58 58.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 116 116.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 232 232.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 25.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 50 50.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 100 100.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 200 200.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 37 37.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 37 37.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 74 74.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 148 148.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 296 296.00 vfsqrt.v v8, v16
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP600Div
-# CHECK-NEXT: [1] - SiFiveP600FEXQ0
-# CHECK-NEXT: [2] - SiFiveP600FEXQ1
-# CHECK-NEXT: [3] - SiFiveP600FloatDiv
-# CHECK-NEXT: [4] - SiFiveP600IEXQ0
-# CHECK-NEXT: [5] - SiFiveP600IEXQ1
-# CHECK-NEXT: [6] - SiFiveP600IEXQ2
-# CHECK-NEXT: [7] - SiFiveP600IEXQ3
-# CHECK-NEXT: [8.0] - SiFiveP600LDST
-# CHECK-NEXT: [8.1] - SiFiveP600LDST
-# CHECK-NEXT: [9] - SiFiveP600VDiv
-# CHECK-NEXT: [10] - SiFiveP600VEXQ0
-# CHECK-NEXT: [11] - SiFiveP600VEXQ1
-# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
-# CHECK-NEXT: [13] - SiFiveP600VLD
-# CHECK-NEXT: [14] - SiFiveP600VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
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-
-# CHECK: Resource pressure by instruction:
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-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 25.00 - - vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 25.00 - - vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 25.00 - - vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 50.00 - - vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 100.00 - - vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 200.00 - - vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 37.00 - - vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 37.00 - - vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 74.00 - - vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 148.00 - - vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 296.00 - - vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 29.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 29.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 29.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 29.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 58.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 116.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 25.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 25.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 25.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 50.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 100.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 200.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 37.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 37.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 74.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 148.00 - - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 296.00 - - vfsqrt.v v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/floating-point.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/floating-point.test
new file mode 100644
index 0000000000000..7e9a6b008f7cd
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/floating-point.test
@@ -0,0 +1,181 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../Inputs/floating-point.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 5 0.50 * 5 SiFiveP600LDST FLW flw ft0, 0(a0)
+# CHECK-NEXT: 1 1 0.50 * 1 SiFiveP600LDST FSW fsw ft0, 0(a0)
+# CHECK-NEXT: 1 5 0.50 * 5 SiFiveP600LDST FLD fld ft0, 0(a0)
+# CHECK-NEXT: 1 1 0.50 * 1 SiFiveP600LDST FSD fsd ft0, 0(a0)
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FADD_S fadd.s fs10, fs11, ft8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FSUB_S fsub.s ft9, ft10, ft11
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600FloatArith FMUL_S fmul.s ft0, ft1, ft2
+# CHECK-NEXT: 1 6 6.00 6 SiFiveP600FEXQ1,SiFiveP600FloatArith,SiFiveP600FloatDiv[6] FDIV_S fdiv.s ft3, ft4, ft5
+# CHECK-NEXT: 1 18 17.00 18 SiFiveP600FEXQ1,SiFiveP600FloatArith,SiFiveP600FloatDiv[17] FSQRT_S fsqrt.s ft6, ft7
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FMIN_S fmin.s fa5, fa6, fa7
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FMAX_S fmax.s fs2, fs3, fs4
+# CHECK-NEXT: 1 4 0.50 4 SiFiveP600FloatArith FMADD_S fmadd.s fa0, fa1, fa2, ft11
+# CHECK-NEXT: 1 4 0.50 4 SiFiveP600FloatArith FMSUB_S fmsub.s fa4, fa5, fa6, fa7
+# CHECK-NEXT: 1 4 0.50 4 SiFiveP600FloatArith FNMSUB_S fnmsub.s fs2, fs3, fs4, fs5
+# CHECK-NEXT: 1 4 0.50 4 SiFiveP600FloatArith FNMADD_S fnmadd.s fs6, fs7, fs8, fs9
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FADD_D fadd.d fs10, fs11, ft8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FSUB_D fsub.d ft9, ft10, ft11
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600FloatArith FMUL_D fmul.d ft0, ft1, ft2
+# CHECK-NEXT: 1 11 11.00 11 SiFiveP600FEXQ1,SiFiveP600FloatArith,SiFiveP600FloatDiv[11] FDIV_D fdiv.d ft3, ft4, ft5
+# CHECK-NEXT: 1 33 32.00 33 SiFiveP600FEXQ1,SiFiveP600FloatArith,SiFiveP600FloatDiv[32] FSQRT_D fsqrt.d ft6, ft7
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FMIN_D fmin.d fa5, fa6, fa7
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FMAX_D fmax.d fs2, fs3, fs4
+# CHECK-NEXT: 1 4 0.50 4 SiFiveP600FloatArith FMADD_D fmadd.d fa0, fa1, fa2, ft11
+# CHECK-NEXT: 1 4 0.50 4 SiFiveP600FloatArith FMSUB_D fmsub.d fa4, fa5, fa6, fa7
+# CHECK-NEXT: 1 4 0.50 4 SiFiveP600FloatArith FNMSUB_D fnmsub.d fs2, fs3, fs4, fs5
+# CHECK-NEXT: 1 4 0.50 4 SiFiveP600FloatArith FNMADD_D fnmadd.d fs6, fs7, fs8, fs9
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FCVT_W_S fcvt.w.s a0, fs5
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FCVT_WU_S fcvt.wu.s a1, fs6
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith FCVT_S_W fcvt.s.w ft11, a4
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith FCVT_S_WU fcvt.s.wu ft0, a5
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FCVT_L_S fcvt.l.s a0, ft0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FCVT_LU_S fcvt.lu.s a1, ft1
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith FCVT_S_L fcvt.s.l ft2, a2
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith FCVT_S_LU fcvt.s.lu ft3, a3
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FMV_X_W fmv.x.w a2, fs7
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith FMV_W_X fmv.w.x ft1, a6
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FSGNJ_S fsgnj.s fs1, fa0, fa1
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FSGNJN_S fsgnjn.s fa1, fa3, fa4
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FCVT_WU_D fcvt.wu.d a4, ft11
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FCVT_W_D fcvt.w.d a4, ft11
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith FCVT_D_W fcvt.d.w ft0, a5
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith FCVT_D_WU fcvt.d.wu ft1, a6
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FCVT_S_D fcvt.s.d fs5, fs6
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FCVT_D_S fcvt.d.s fs7, fs8
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FCVT_L_D fcvt.l.d a0, ft0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FCVT_LU_D fcvt.lu.d a1, ft1
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith FCVT_D_L fcvt.d.l ft3, a3
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith FCVT_D_LU fcvt.d.lu ft4, a4
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FMV_X_D fmv.x.d a2, ft2
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith FMV_D_X fmv.d.x ft5, a5
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FSGNJ_D fsgnj.d fs1, fa0, fa1
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FSGNJN_D fsgnjn.d fa1, fa3, fa4
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FEQ_S feq.s a1, fs8, fs9
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FLT_S flt.s a2, fs10, fs11
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FLE_S fle.s a3, ft8, ft9
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FEQ_D feq.d a1, fs8, fs9
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FLT_D flt.d a2, fs10, fs11
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FLE_D fle.d a3, ft8, ft9
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FCLASS_S fclass.s a3, ft10
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FCLASS_D fclass.d a3, ft10
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - 30.00 16.00 66.00 - 10.00 - - 2.00 2.00 - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - flw ft0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - fsw ft0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - fld ft0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - fsd ft0, 0(a0)
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fadd.s fs10, fs11, ft8
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fsub.s ft9, ft10, ft11
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fmul.s ft0, ft1, ft2
+# CHECK-NEXT: - - 1.00 6.00 - - - - - - - - - - - - fdiv.s ft3, ft4, ft5
+# CHECK-NEXT: - - 1.00 17.00 - - - - - - - - - - - - fsqrt.s ft6, ft7
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fmin.s fa5, fa6, fa7
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fmax.s fs2, fs3, fs4
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fmadd.s fa0, fa1, fa2, ft11
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fmsub.s fa4, fa5, fa6, fa7
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fnmsub.s fs2, fs3, fs4, fs5
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fnmadd.s fs6, fs7, fs8, fs9
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fadd.d fs10, fs11, ft8
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fsub.d ft9, ft10, ft11
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fmul.d ft0, ft1, ft2
+# CHECK-NEXT: - - 1.00 11.00 - - - - - - - - - - - - fdiv.d ft3, ft4, ft5
+# CHECK-NEXT: - - 1.00 32.00 - - - - - - - - - - - - fsqrt.d ft6, ft7
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fmin.d fa5, fa6, fa7
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fmax.d fs2, fs3, fs4
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fmadd.d fa0, fa1, fa2, ft11
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fmsub.d fa4, fa5, fa6, fa7
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fnmsub.d fs2, fs3, fs4, fs5
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fnmadd.d fs6, fs7, fs8, fs9
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - fcvt.w.s a0, fs5
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - fcvt.wu.s a1, fs6
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fcvt.s.w ft11, a4
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fcvt.s.wu ft0, a5
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - fcvt.l.s a0, ft0
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - fcvt.lu.s a1, ft1
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fcvt.s.l ft2, a2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fcvt.s.lu ft3, a3
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - fmv.x.w a2, fs7
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fmv.w.x ft1, a6
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fsgnj.s fs1, fa0, fa1
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fsgnjn.s fa1, fa3, fa4
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - fcvt.wu.d a4, ft11
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - fcvt.w.d a4, ft11
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fcvt.d.w ft0, a5
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fcvt.d.wu ft1, a6
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fcvt.s.d fs5, fs6
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fcvt.d.s fs7, fs8
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - fcvt.l.d a0, ft0
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - fcvt.lu.d a1, ft1
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fcvt.d.l ft3, a3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fcvt.d.lu ft4, a4
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - fmv.x.d a2, ft2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fmv.d.x ft5, a5
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fsgnj.d fs1, fa0, fa1
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fsgnjn.d fa1, fa3, fa4
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - feq.s a1, fs8, fs9
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - flt.s a2, fs10, fs11
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - fle.s a3, ft8, ft9
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - feq.d a1, fs8, fs9
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - flt.d a2, fs10, fs11
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - fle.d a3, ft8, ft9
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - fclass.s a3, ft10
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - fclass.d a3, ft10
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/integer.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/integer.test
new file mode 100644
index 0000000000000..f1c54534dea58
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/integer.test
@@ -0,0 +1,173 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../Inputs/integer.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_ADDI addi a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_ADDIW addiw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SLTI slti a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SLTIU seqz a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_ANDI andi a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith ORI ori a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith XORI xori a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_SLLI slli a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_SRLI srli a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_SRAI srai a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SLLIW slliw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SRLIW srliw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SRAIW sraiw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_LUI lui a0, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith AUIPC auipc a1, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_ADD add a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_ADDW addw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SLT slt a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SLTU sltu a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_AND and a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_OR or a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_XOR xor a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SLL sll a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SRL srl a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SRA sra a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SLLW sllw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SRLW srlw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SRAW sraw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_SUB sub a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_SUBW subw a0, a0, a0
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600Branch,SiFiveP600IntArith JAL jal a0, .Ltmp0
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600Branch,SiFiveP600IntArith C_JALR jalr a0
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600Branch,SiFiveP600IntArith BEQ beq a0, a0, .Ltmp1
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600Branch,SiFiveP600IntArith BNE bne a0, a0, .Ltmp2
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600Branch,SiFiveP600IntArith BLT blt a0, a0, .Ltmp3
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600Branch,SiFiveP600IntArith BLTU bltu a0, a0, .Ltmp4
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600Branch,SiFiveP600IntArith BGE bge a0, a0, .Ltmp5
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600Branch,SiFiveP600IntArith BGEU bgeu a0, a0, .Ltmp6
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_ADD add a0, a0, a0
+# CHECK-NEXT: 1 4 0.50 * 4 SiFiveP600LDST LB lb t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SiFiveP600LDST LBU lbu t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SiFiveP600LDST LH lh t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SiFiveP600LDST LHU lhu t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SiFiveP600LDST LW lw t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SiFiveP600LDST LWU lwu t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SiFiveP600LDST LD ld t0, 0(a0)
+# CHECK-NEXT: 1 1 0.50 * 1 SiFiveP600LDST SB sb t0, 0(a0)
+# CHECK-NEXT: 1 1 0.50 * 1 SiFiveP600LDST SH sh t0, 0(a0)
+# CHECK-NEXT: 1 1 0.50 * 1 SiFiveP600LDST SW sw t0, 0(a0)
+# CHECK-NEXT: 1 1 0.50 * 1 SiFiveP600LDST SD sd t0, 0(a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith CSRRW csrrw t0, 4095, t1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith CSRRS csrrs s3, fflags, s5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith CSRRC csrrc sp, 0, ra
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith CSRRWI csrrwi a5, 0, 0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith CSRRSI csrrsi t2, 4095, 31
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith CSRRCI csrrci t1, sscratch, 5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 13.75 7.75 11.75 11.75 5.50 5.50 - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - addi a0, a0, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - addiw a0, a0, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - slti a0, a0, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - seqz a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - andi a0, a0, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - ori a0, a0, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - xori a0, a0, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - slli a0, a0, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - srli a0, a0, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - srai a0, a0, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - slliw a0, a0, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - srliw a0, a0, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sraiw a0, a0, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - lui a0, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - auipc a1, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - add a0, a0, a1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - addw a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - slt a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sltu a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - and a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - or a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - xor a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sll a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - srl a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sra a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sllw a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - srlw a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sraw a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sub a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - subw a0, a0, a0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - jal a0, .Ltmp0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - jalr a0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - beq a0, a0, .Ltmp1
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - bne a0, a0, .Ltmp2
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - blt a0, a0, .Ltmp3
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - bltu a0, a0, .Ltmp4
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - bge a0, a0, .Ltmp5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - bgeu a0, a0, .Ltmp6
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - add a0, a0, a0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lb t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lbu t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lh t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lhu t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lw t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lwu t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - ld t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - sb t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - sh t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - sw t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - sd t0, 0(a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - csrrw t0, 4095, t1
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - csrrs s3, fflags, s5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - csrrc sp, 0, ra
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - csrrwi a5, 0, 0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - csrrsi t2, 4095, 31
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - csrrci t1, sscratch, 5
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/load.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/load.s
deleted file mode 100644
index 9ece35b92dfaa..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/load.s
+++ /dev/null
@@ -1,64 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
-
-lw t0, 0(a0)
-ld t0, 0(a0)
-
-flh ft0, 0(a0)
-flw ft0, 0(a0)
-fld ft0, 0(a0)
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 5
-# CHECK-NEXT: Total Cycles: 10
-# CHECK-NEXT: Total uOps: 5
-
-# CHECK: Dispatch Width: 4
-# CHECK-NEXT: uOps Per Cycle: 0.50
-# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 2.5
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 4 0.50 * lw t0, 0(a0)
-# CHECK-NEXT: 1 4 0.50 * ld t0, 0(a0)
-# CHECK-NEXT: 1 5 0.50 * flh ft0, 0(a0)
-# CHECK-NEXT: 1 5 0.50 * flw ft0, 0(a0)
-# CHECK-NEXT: 1 5 0.50 * fld ft0, 0(a0)
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP600Div
-# CHECK-NEXT: [1] - SiFiveP600FEXQ0
-# CHECK-NEXT: [2] - SiFiveP600FEXQ1
-# CHECK-NEXT: [3] - SiFiveP600FloatDiv
-# CHECK-NEXT: [4] - SiFiveP600IEXQ0
-# CHECK-NEXT: [5] - SiFiveP600IEXQ1
-# CHECK-NEXT: [6] - SiFiveP600IEXQ2
-# CHECK-NEXT: [7] - SiFiveP600IEXQ3
-# CHECK-NEXT: [8.0] - SiFiveP600LDST
-# CHECK-NEXT: [8.1] - SiFiveP600LDST
-# CHECK-NEXT: [9] - SiFiveP600VDiv
-# CHECK-NEXT: [10] - SiFiveP600VEXQ0
-# CHECK-NEXT: [11] - SiFiveP600VEXQ1
-# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
-# CHECK-NEXT: [13] - SiFiveP600VLD
-# CHECK-NEXT: [14] - SiFiveP600VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
-# CHECK-NEXT: - - - - - - - - 2.00 3.00 - - - - - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - lw t0, 0(a0)
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - ld t0, 0(a0)
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - flh ft0, 0(a0)
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - flw ft0, 0(a0)
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - fld ft0, 0(a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mask.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mask.s
deleted file mode 100644
index adb45fceda372..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mask.s
+++ /dev/null
@@ -1,129 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=100 < %s | FileCheck %s
-
-vsetvli zero, zero, e32, m1, ta, ma
-
-vmslt.vv v0, v4, v20
-vmsle.vv v8, v4, v20
-vmsgt.vv v8, v20, v4
-vmsge.vv v8, v20, v4
-vmseq.vv v8, v4, v20
-vmsne.vv v8, v4, v20
-vmsltu.vv v8, v4, v20
-vmsleu.vv v8, v4, v20
-vmsgtu.vv v8, v20, v4
-vmsgeu.vv v8, v20, v4
-
-vmflt.vv v0, v4, v20
-vmfle.vv v8, v4, v20
-vmfgt.vv v8, v20, v4
-vmfge.vv v8, v20, v4
-vmfeq.vv v8, v4, v20
-vmfne.vv v8, v4, v20
-
-vmadc.vv v8, v4, v20
-vmsbc.vv v8, v4, v20
-
-vfirst.m a2, v4
-vpopc.m a2, v4
-
-viota.m v8, v4
-
-vmsbf.m v8, v4
-vmsif.m v8, v4
-vmsof.m v8, v4
-
-# CHECK: Iterations: 100
-# CHECK-NEXT: Instructions: 2500
-# CHECK-NEXT: Total Cycles: 2605
-# CHECK-NEXT: Total uOps: 2500
-
-# CHECK: Dispatch Width: 4
-# CHECK-NEXT: uOps Per Cycle: 0.96
-# CHECK-NEXT: IPC: 0.96
-# CHECK-NEXT: Block RThroughput: 26.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 2 1.00 vmslt.vv v0, v4, v20
-# CHECK-NEXT: 1 2 1.00 vmsle.vv v8, v4, v20
-# CHECK-NEXT: 1 2 1.00 vmslt.vv v8, v4, v20
-# CHECK-NEXT: 1 2 1.00 vmsle.vv v8, v4, v20
-# CHECK-NEXT: 1 2 1.00 vmseq.vv v8, v4, v20
-# CHECK-NEXT: 1 2 1.00 vmsne.vv v8, v4, v20
-# CHECK-NEXT: 1 2 1.00 vmsltu.vv v8, v4, v20
-# CHECK-NEXT: 1 2 1.00 vmsleu.vv v8, v4, v20
-# CHECK-NEXT: 1 2 1.00 vmsltu.vv v8, v4, v20
-# CHECK-NEXT: 1 2 1.00 vmsleu.vv v8, v4, v20
-# CHECK-NEXT: 1 2 1.00 vmflt.vv v0, v4, v20
-# CHECK-NEXT: 1 2 1.00 vmfle.vv v8, v4, v20
-# CHECK-NEXT: 1 2 1.00 vmflt.vv v8, v4, v20
-# CHECK-NEXT: 1 2 1.00 vmfle.vv v8, v4, v20
-# CHECK-NEXT: 1 2 1.00 vmfeq.vv v8, v4, v20
-# CHECK-NEXT: 1 2 1.00 vmfne.vv v8, v4, v20
-# CHECK-NEXT: 1 2 1.00 vmadc.vv v8, v4, v20
-# CHECK-NEXT: 1 2 1.00 vmsbc.vv v8, v4, v20
-# CHECK-NEXT: 1 2 2.00 vfirst.m a2, v4
-# CHECK-NEXT: 1 2 2.00 vcpop.m a2, v4
-# CHECK-NEXT: 1 2 1.00 viota.m v8, v4
-# CHECK-NEXT: 1 2 1.00 vmsbf.m v8, v4
-# CHECK-NEXT: 1 2 1.00 vmsif.m v8, v4
-# CHECK-NEXT: 1 2 1.00 vmsof.m v8, v4
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP600Div
-# CHECK-NEXT: [1] - SiFiveP600FEXQ0
-# CHECK-NEXT: [2] - SiFiveP600FEXQ1
-# CHECK-NEXT: [3] - SiFiveP600FloatDiv
-# CHECK-NEXT: [4] - SiFiveP600IEXQ0
-# CHECK-NEXT: [5] - SiFiveP600IEXQ1
-# CHECK-NEXT: [6] - SiFiveP600IEXQ2
-# CHECK-NEXT: [7] - SiFiveP600IEXQ3
-# CHECK-NEXT: [8.0] - SiFiveP600LDST
-# CHECK-NEXT: [8.1] - SiFiveP600LDST
-# CHECK-NEXT: [9] - SiFiveP600VDiv
-# CHECK-NEXT: [10] - SiFiveP600VEXQ0
-# CHECK-NEXT: [11] - SiFiveP600VEXQ1
-# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
-# CHECK-NEXT: [13] - SiFiveP600VLD
-# CHECK-NEXT: [14] - SiFiveP600VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
-# CHECK-NEXT: - - - - 1.00 - - - - - - 26.00 - - - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vv v0, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsle.vv v8, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vv v8, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsle.vv v8, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vv v8, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsne.vv v8, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsltu.vv v8, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsleu.vv v8, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsltu.vv v8, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsleu.vv v8, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmflt.vv v0, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmfle.vv v8, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmflt.vv v8, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmfle.vv v8, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmfeq.vv v8, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmfne.vv v8, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmadc.vv v8, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsbc.vv v8, v4, v20
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfirst.m a2, v4
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vcpop.m a2, v4
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - viota.m v8, v4
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsbf.m v8, v4
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsif.m v8, v4
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsof.m v8, v4
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-cpop.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-cpop.s
deleted file mode 100644
index ec067ba658403..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-cpop.s
+++ /dev/null
@@ -1,63 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
-
-mul s6, s6, s7
-
-mulw s4, s4, a2
-
-cpop t1, t1
-
-cpopw t2, t2
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 4
-# CHECK-NEXT: Total Cycles: 8
-# CHECK-NEXT: Total uOps: 4
-
-# CHECK: Dispatch Width: 4
-# CHECK-NEXT: uOps Per Cycle: 0.50
-# CHECK-NEXT: IPC: 0.50
-# CHECK-NEXT: Block RThroughput: 4.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 2 1.00 mul s6, s6, s7
-# CHECK-NEXT: 1 2 1.00 mulw s4, s4, a2
-# CHECK-NEXT: 1 2 1.00 cpop t1, t1
-# CHECK-NEXT: 1 2 1.00 cpopw t2, t2
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP600Div
-# CHECK-NEXT: [1] - SiFiveP600FEXQ0
-# CHECK-NEXT: [2] - SiFiveP600FEXQ1
-# CHECK-NEXT: [3] - SiFiveP600FloatDiv
-# CHECK-NEXT: [4] - SiFiveP600IEXQ0
-# CHECK-NEXT: [5] - SiFiveP600IEXQ1
-# CHECK-NEXT: [6] - SiFiveP600IEXQ2
-# CHECK-NEXT: [7] - SiFiveP600IEXQ3
-# CHECK-NEXT: [8.0] - SiFiveP600LDST
-# CHECK-NEXT: [8.1] - SiFiveP600LDST
-# CHECK-NEXT: [9] - SiFiveP600VDiv
-# CHECK-NEXT: [10] - SiFiveP600VEXQ0
-# CHECK-NEXT: [11] - SiFiveP600VEXQ1
-# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
-# CHECK-NEXT: [13] - SiFiveP600VLD
-# CHECK-NEXT: [14] - SiFiveP600VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
-# CHECK-NEXT: - - - - - 4.00 - - - - - - - - - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
-# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - mul s6, s6, s7
-# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - mulw s4, s4, a2
-# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - cpop t1, t1
-# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - cpopw t2, t2
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-div-rv32.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-div-rv32.test
new file mode 100644
index 0000000000000..d27014a92c818
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-div-rv32.test
@@ -0,0 +1,77 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../Inputs/mul-div-rv32.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith MUL mul a0, a0, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith MULH mulh a0, a0, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith MULHU mulhu a0, a0, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith MULHSU mulhsu a0, a0, a0
+# CHECK-NEXT: 1 35 34.00 35 SiFiveP600Div[34],SiFiveP600IEXQ1,SiFiveP600IntArith DIV div a0, a1, a2
+# CHECK-NEXT: 1 35 34.00 35 SiFiveP600Div[34],SiFiveP600IEXQ1,SiFiveP600IntArith DIVU divu a0, a1, a2
+# CHECK-NEXT: 1 35 34.00 35 SiFiveP600Div[34],SiFiveP600IEXQ1,SiFiveP600IntArith REM rem a0, a1, a2
+# CHECK-NEXT: 1 35 34.00 35 SiFiveP600Div[34],SiFiveP600IEXQ1,SiFiveP600IntArith REMU remu a0, a1, a2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: 136.00 - - - - 8.00 - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - mul a0, a0, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - mulh a0, a0, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - mulhu a0, a0, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - mulhsu a0, a0, a0
+# CHECK-NEXT: 34.00 - - - - 1.00 - - - - - - - - - - div a0, a1, a2
+# CHECK-NEXT: 34.00 - - - - 1.00 - - - - - - - - - - divu a0, a1, a2
+# CHECK-NEXT: 34.00 - - - - 1.00 - - - - - - - - - - rem a0, a1, a2
+# CHECK-NEXT: 34.00 - - - - 1.00 - - - - - - - - - - remu a0, a1, a2
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-div.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-div.test
new file mode 100644
index 0000000000000..8d86d3a8334ff
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-div.test
@@ -0,0 +1,87 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../Inputs/mul-div.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith MUL mul a0, a0, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith MULH mulh a0, a0, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith MULHU mulhu a0, a0, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith MULHSU mulhsu a0, a0, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith MULW mulw a0, a0, a0
+# CHECK-NEXT: 1 35 34.00 35 SiFiveP600Div[34],SiFiveP600IEXQ1,SiFiveP600IntArith DIV div a0, a1, a2
+# CHECK-NEXT: 1 35 34.00 35 SiFiveP600Div[34],SiFiveP600IEXQ1,SiFiveP600IntArith DIVU divu a0, a1, a2
+# CHECK-NEXT: 1 35 34.00 35 SiFiveP600Div[34],SiFiveP600IEXQ1,SiFiveP600IntArith REM rem a0, a1, a2
+# CHECK-NEXT: 1 35 34.00 35 SiFiveP600Div[34],SiFiveP600IEXQ1,SiFiveP600IntArith REMU remu a0, a1, a2
+# CHECK-NEXT: 1 20 19.00 20 SiFiveP600Div[19],SiFiveP600IEXQ1,SiFiveP600IntArith DIVW divw a0, a1, a2
+# CHECK-NEXT: 1 20 19.00 20 SiFiveP600Div[19],SiFiveP600IEXQ1,SiFiveP600IntArith DIVUW divuw a0, a1, a2
+# CHECK-NEXT: 1 20 19.00 20 SiFiveP600Div[19],SiFiveP600IEXQ1,SiFiveP600IntArith REMW remw a0, a1, a2
+# CHECK-NEXT: 1 20 19.00 20 SiFiveP600Div[19],SiFiveP600IEXQ1,SiFiveP600IntArith REMUW remuw a0, a1, a2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: 212.00 - - - - 13.00 - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - mul a0, a0, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - mulh a0, a0, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - mulhu a0, a0, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - mulhsu a0, a0, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - mulw a0, a0, a0
+# CHECK-NEXT: 34.00 - - - - 1.00 - - - - - - - - - - div a0, a1, a2
+# CHECK-NEXT: 34.00 - - - - 1.00 - - - - - - - - - - divu a0, a1, a2
+# CHECK-NEXT: 34.00 - - - - 1.00 - - - - - - - - - - rem a0, a1, a2
+# CHECK-NEXT: 34.00 - - - - 1.00 - - - - - - - - - - remu a0, a1, a2
+# CHECK-NEXT: 19.00 - - - - 1.00 - - - - - - - - - - divw a0, a1, a2
+# CHECK-NEXT: 19.00 - - - - 1.00 - - - - - - - - - - divuw a0, a1, a2
+# CHECK-NEXT: 19.00 - - - - 1.00 - - - - - - - - - - remw a0, a1, a2
+# CHECK-NEXT: 19.00 - - - - 1.00 - - - - - - - - - - remuw a0, a1, a2
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/arithmetic.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/arithmetic.test
new file mode 100644
index 0000000000000..41ca10855f015
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/arithmetic.test
@@ -0,0 +1,4541 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/arithmetic.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 4 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VWSUB_WX vwsub.wx v8, v16, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 1120.00 - - - - - - 1974.00 1314.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vadd.vv v8, v8, v8
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vwsub.wx v8, v16, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/bitwise.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/bitwise.test
new file mode 100644
index 0000000000000..122c124741780
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/bitwise.test
@@ -0,0 +1,2893 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/bitwise.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSSRL_VX vssrl.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 708.00 - - - - - - 954.00 954.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vand.vv v8, v8, v8
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vssrl.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/comparison.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/comparison.test
new file mode 100644
index 0000000000000..b520acb2f2803
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/comparison.test
@@ -0,0 +1,1821 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/comparison.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMSLT_VX vmslt.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 440.00 - - - - - - 1320.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmsle.vv v8, v8, v8
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmslt.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/conversion.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/conversion.test
new file mode 100644
index 0000000000000..3012f96797cb8
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/conversion.test
@@ -0,0 +1,1185 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/conversion.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SiFiveP600VectorArith VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VectorArith[2] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VectorArith[4] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 281.00 - - - - - - 393.50 393.50 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vsext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vzext.vf2 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vsext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vzext.vf4 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsext.vf8 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vsext.vf8 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vsext.vf8 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vsext.vf8 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vzext.vf8 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vzext.vf8 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vzext.vf8 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vzext.vf8 v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfcvt.f.xu.v v8, v8
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwcvt.xu.f.v v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/fma.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/fma.test
new file mode 100644
index 0000000000000..3a276fcb970ce
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/fma.test
@@ -0,0 +1,1473 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/fma.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 353.00 - - - - - - 426.50 426.50 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmacc.vx v8, s0, v8
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwnmsac.vv v8, v16, v24
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/fp.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/fp.test
new file mode 100644
index 0000000000000..364f7ab5cd000
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/fp.test
@@ -0,0 +1,3721 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/fp.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[29],SiFiveP600VectorArith VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[29],SiFiveP600VectorArith VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[29],SiFiveP600VectorArith VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 58 58.00 58 SiFiveP600VEXQ1[2],SiFiveP600VFloatDiv[58],SiFiveP600VectorArith[2] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 116 116.00 116 SiFiveP600VEXQ1[4],SiFiveP600VFloatDiv[116],SiFiveP600VectorArith[4] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP600VEXQ1[8],SiFiveP600VFloatDiv[232],SiFiveP600VectorArith[8] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[25],SiFiveP600VectorArith VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[25],SiFiveP600VectorArith VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 50 50.00 50 SiFiveP600VEXQ1[2],SiFiveP600VFloatDiv[50],SiFiveP600VectorArith[2] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 100 100.00 100 SiFiveP600VEXQ1[4],SiFiveP600VFloatDiv[100],SiFiveP600VectorArith[4] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 200 200.00 200 SiFiveP600VEXQ1[8],SiFiveP600VFloatDiv[200],SiFiveP600VectorArith[8] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 37 37.00 37 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[37],SiFiveP600VectorArith VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 74 74.00 74 SiFiveP600VEXQ1[2],SiFiveP600VFloatDiv[74],SiFiveP600VectorArith[2] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 148 148.00 148 SiFiveP600VEXQ1[4],SiFiveP600VFloatDiv[148],SiFiveP600VectorArith[4] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 296 296.00 296 SiFiveP600VEXQ1[8],SiFiveP600VFloatDiv[296],SiFiveP600VectorArith[8] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[29],SiFiveP600VectorArith VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[29],SiFiveP600VectorArith VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[29],SiFiveP600VectorArith VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 58 58.00 58 SiFiveP600VEXQ1[2],SiFiveP600VFloatDiv[58],SiFiveP600VectorArith[2] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 116 116.00 116 SiFiveP600VEXQ1[4],SiFiveP600VFloatDiv[116],SiFiveP600VectorArith[4] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP600VEXQ1[8],SiFiveP600VFloatDiv[232],SiFiveP600VectorArith[8] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[25],SiFiveP600VectorArith VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[25],SiFiveP600VectorArith VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 50 50.00 50 SiFiveP600VEXQ1[2],SiFiveP600VFloatDiv[50],SiFiveP600VectorArith[2] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 100 100.00 100 SiFiveP600VEXQ1[4],SiFiveP600VFloatDiv[100],SiFiveP600VectorArith[4] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 200 200.00 200 SiFiveP600VEXQ1[8],SiFiveP600VFloatDiv[200],SiFiveP600VectorArith[8] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 37 37.00 37 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[37],SiFiveP600VectorArith VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 74 74.00 74 SiFiveP600VEXQ1[2],SiFiveP600VFloatDiv[74],SiFiveP600VectorArith[2] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 148 148.00 148 SiFiveP600VEXQ1[4],SiFiveP600VFloatDiv[148],SiFiveP600VectorArith[4] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 296 296.00 296 SiFiveP600VEXQ1[8],SiFiveP600VFloatDiv[296],SiFiveP600VectorArith[8] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[29],SiFiveP600VectorArith VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[29],SiFiveP600VectorArith VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[29],SiFiveP600VectorArith VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 58 58.00 58 SiFiveP600VEXQ1[2],SiFiveP600VFloatDiv[58],SiFiveP600VectorArith[2] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 116 116.00 116 SiFiveP600VEXQ1[4],SiFiveP600VFloatDiv[116],SiFiveP600VectorArith[4] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP600VEXQ1[8],SiFiveP600VFloatDiv[232],SiFiveP600VectorArith[8] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[25],SiFiveP600VectorArith VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[25],SiFiveP600VectorArith VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 50 50.00 50 SiFiveP600VEXQ1[2],SiFiveP600VFloatDiv[50],SiFiveP600VectorArith[2] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 100 100.00 100 SiFiveP600VEXQ1[4],SiFiveP600VFloatDiv[100],SiFiveP600VectorArith[4] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 200 200.00 200 SiFiveP600VEXQ1[8],SiFiveP600VFloatDiv[200],SiFiveP600VectorArith[8] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 37 37.00 37 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[37],SiFiveP600VectorArith VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 74 74.00 74 SiFiveP600VEXQ1[2],SiFiveP600VFloatDiv[74],SiFiveP600VectorArith[2] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 148 148.00 148 SiFiveP600VEXQ1[4],SiFiveP600VFloatDiv[148],SiFiveP600VectorArith[4] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 296 296.00 296 SiFiveP600VEXQ1[8],SiFiveP600VFloatDiv[296],SiFiveP600VectorArith[8] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[29],SiFiveP600VectorArith VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[29],SiFiveP600VectorArith VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[29],SiFiveP600VectorArith VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 58 58.00 58 SiFiveP600VEXQ1[2],SiFiveP600VFloatDiv[58],SiFiveP600VectorArith[2] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 116 116.00 116 SiFiveP600VEXQ1[4],SiFiveP600VFloatDiv[116],SiFiveP600VectorArith[4] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP600VEXQ1[8],SiFiveP600VFloatDiv[232],SiFiveP600VectorArith[8] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[25],SiFiveP600VectorArith VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[25],SiFiveP600VectorArith VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 50 50.00 50 SiFiveP600VEXQ1[2],SiFiveP600VFloatDiv[50],SiFiveP600VectorArith[2] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 100 100.00 100 SiFiveP600VEXQ1[4],SiFiveP600VFloatDiv[100],SiFiveP600VectorArith[4] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 200 200.00 200 SiFiveP600VEXQ1[8],SiFiveP600VFloatDiv[200],SiFiveP600VectorArith[8] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 37 37.00 37 SiFiveP600VEXQ1,SiFiveP600VFloatDiv[37],SiFiveP600VectorArith VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 74 74.00 74 SiFiveP600VEXQ1[2],SiFiveP600VFloatDiv[74],SiFiveP600VectorArith[2] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 148 148.00 148 SiFiveP600VEXQ1[4],SiFiveP600VFloatDiv[148],SiFiveP600VectorArith[4] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 296 296.00 296 SiFiveP600VEXQ1[8],SiFiveP600VFloatDiv[296],SiFiveP600VectorArith[8] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VFWSUB_WV vfwsub.wv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 915.00 - - - - - - 1619.00 1235.00 5792.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmfeq.vv v8, v8, v8
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwmul.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwsub.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vfwsub.wv v8, v16, v24
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/mask.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/mask.test
new file mode 100644
index 0000000000000..3a448a3f133e3
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/mask.test
@@ -0,0 +1,1265 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/mask.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMAND_MM vmmv.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNAND_MM vmnot.m v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXOR_MM vmclr.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMXNOR_MM vmset.m v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600VectorArith VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600VectorArith VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600VectorArith VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600VectorArith VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 SiFiveP600VectorArith[2] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600VectorArith VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600VectorArith VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600VectorArith VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 SiFiveP600VectorArith[2] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600VectorArith VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600VectorArith VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 SiFiveP600VectorArith[2] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 SiFiveP600VectorArith VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 1 SiFiveP600VectorArith[2] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFIRST_M vfirst.m s0, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 301.00 - - - - - - 349.00 33.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmmv.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmnot.m v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmclr.m v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmclr.m v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmclr.m v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmclr.m v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmclr.m v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmclr.m v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmclr.m v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmclr.m v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmclr.m v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmclr.m v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmclr.m v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmclr.m v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmclr.m v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vcpop.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vcpop.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vcpop.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vcpop.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vcpop.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfirst.m s0, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfirst.m s0, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/minmax.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/minmax.test
new file mode 100644
index 0000000000000..277c0428ee57d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/minmax.test
@@ -0,0 +1,765 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/minmax.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMINU_VX vminu.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 176.00 - - - - - - 264.00 264.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmax.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmax.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vminu.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vminu.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vminu.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/mul-div.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/mul-div.test
new file mode 100644
index 0000000000000..fbe896438c3c9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/mul-div.test
@@ -0,0 +1,2005 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/mul-div.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP600VDiv[102],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP600VDiv[204],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP600VDiv[408],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP600VDiv[90],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP600VDiv[180],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP600VDiv[360],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP600VDiv[42],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP600VDiv[42],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP600VDiv[84],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP600VDiv[168],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP600VDiv[336],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP600VDiv[72],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP600VDiv[144],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP600VDiv[288],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP600VDiv[576],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP600VDiv[102],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP600VDiv[204],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP600VDiv[408],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP600VDiv[90],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP600VDiv[180],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP600VDiv[360],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP600VDiv[42],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP600VDiv[42],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP600VDiv[84],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP600VDiv[168],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP600VDiv[336],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP600VDiv[72],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP600VDiv[144],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP600VDiv[288],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP600VDiv[576],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP600VDiv[102],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP600VDiv[204],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP600VDiv[408],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP600VDiv[90],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP600VDiv[180],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP600VDiv[360],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP600VDiv[42],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP600VDiv[42],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP600VDiv[84],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP600VDiv[168],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP600VDiv[336],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP600VDiv[72],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP600VDiv[144],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP600VDiv[288],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP600VDiv[576],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP600VDiv[102],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP600VDiv[204],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP600VDiv[408],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP600VDiv[90],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP600VDiv[180],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP600VDiv[360],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP600VDiv[42],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP600VDiv[42],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP600VDiv[84],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP600VDiv[168],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP600VDiv[336],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP600VDiv[72],SiFiveP600VEXQ1,SiFiveP600VectorArith VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP600VDiv[144],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP600VDiv[288],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP600VDiv[576],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP600VDiv[102],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP600VDiv[204],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP600VDiv[408],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP600VDiv[90],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP600VDiv[180],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP600VDiv[360],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP600VDiv[42],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP600VDiv[42],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP600VDiv[84],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP600VDiv[168],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP600VDiv[336],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP600VDiv[72],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP600VDiv[144],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP600VDiv[288],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP600VDiv[576],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP600VDiv[102],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP600VDiv[204],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP600VDiv[408],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP600VDiv[90],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP600VDiv[180],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP600VDiv[360],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP600VDiv[42],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP600VDiv[42],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP600VDiv[84],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP600VDiv[168],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP600VDiv[336],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP600VDiv[72],SiFiveP600VEXQ1,SiFiveP600VectorArith VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP600VDiv[144],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP600VDiv[288],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP600VDiv[576],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP600VDiv[102],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP600VDiv[204],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP600VDiv[408],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP600VDiv[90],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP600VDiv[180],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP600VDiv[360],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP600VDiv[42],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP600VDiv[42],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP600VDiv[84],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP600VDiv[168],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP600VDiv[336],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP600VDiv[72],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP600VDiv[144],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP600VDiv[288],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP600VDiv[576],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP600VDiv[51],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP600VDiv[102],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP600VDiv[204],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP600VDiv[408],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP600VDiv[45],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP600VDiv[90],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP600VDiv[180],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP600VDiv[360],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP600VDiv[42],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP600VDiv[42],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP600VDiv[84],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP600VDiv[168],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP600VDiv[336],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP600VDiv[72],SiFiveP600VEXQ1,SiFiveP600VectorArith VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP600VDiv[144],SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP600VDiv[288],SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP600VDiv[576],SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 0.50 6 SiFiveP600VectorArith VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP600VectorArith[2] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP600VectorArith[4] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VectorArith[8] VSMUL_VX vsmul.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 486.00 - - - - - 27480.00 411.00 939.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 51.00 - 1.00 - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 51.00 - 1.00 - - - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vsmul.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/permutation.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/permutation.test
new file mode 100644
index 0000000000000..c31b69ce37874
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/permutation.test
@@ -0,0 +1,2349 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/permutation.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VectorArith[8] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 2 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 13.00 6 SiFiveP600VEXQ1[13],SiFiveP600VectorArith[13] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 17.00 6 SiFiveP600VEXQ1[17],SiFiveP600VectorArith[17] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 25.00 6 SiFiveP600VEXQ1[25],SiFiveP600VectorArith[25] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 13.00 6 SiFiveP600VEXQ1[13],SiFiveP600VectorArith[13] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 17.00 6 SiFiveP600VEXQ1[17],SiFiveP600VectorArith[17] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 25.00 6 SiFiveP600VEXQ1[25],SiFiveP600VectorArith[25] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 13.00 6 SiFiveP600VEXQ1[13],SiFiveP600VectorArith[13] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 17.00 6 SiFiveP600VEXQ1[17],SiFiveP600VectorArith[17] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 25.00 6 SiFiveP600VEXQ1[25],SiFiveP600VectorArith[25] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 13.00 6 SiFiveP600VEXQ1[13],SiFiveP600VectorArith[13] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 17.00 6 SiFiveP600VEXQ1[17],SiFiveP600VectorArith[17] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 25.00 6 SiFiveP600VEXQ1[25],SiFiveP600VectorArith[25] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 SiFiveP600VEXQ1[10],SiFiveP600VectorArith[10] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 12.00 14 SiFiveP600VEXQ1[12],SiFiveP600VectorArith[12] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 20 16.00 20 SiFiveP600VEXQ1[16],SiFiveP600VectorArith[16] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 SiFiveP600VEXQ1[10],SiFiveP600VectorArith[10] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 14 12.00 14 SiFiveP600VEXQ1[12],SiFiveP600VectorArith[12] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 20 16.00 20 SiFiveP600VEXQ1[16],SiFiveP600VectorArith[16] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 SiFiveP600VEXQ1[10],SiFiveP600VectorArith[10] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 14 12.00 14 SiFiveP600VEXQ1[12],SiFiveP600VectorArith[12] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 20 16.00 20 SiFiveP600VEXQ1[16],SiFiveP600VectorArith[16] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 11 10.00 11 SiFiveP600VEXQ1[10],SiFiveP600VectorArith[10] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 14 12.00 14 SiFiveP600VEXQ1[12],SiFiveP600VectorArith[12] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 20 16.00 20 SiFiveP600VEXQ1[16],SiFiveP600VectorArith[16] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 11 11.00 11 SiFiveP600VEXQ1[11],SiFiveP600VectorArith[11] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SiFiveP600VEXQ1[14],SiFiveP600VectorArith[14] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 20 20.00 20 SiFiveP600VEXQ1[20],SiFiveP600VectorArith[20] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 11.00 11 SiFiveP600VEXQ1[11],SiFiveP600VectorArith[11] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SiFiveP600VEXQ1[14],SiFiveP600VectorArith[14] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 20 20.00 20 SiFiveP600VEXQ1[20],SiFiveP600VectorArith[20] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 11 11.00 11 SiFiveP600VEXQ1[11],SiFiveP600VectorArith[11] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SiFiveP600VEXQ1[14],SiFiveP600VectorArith[14] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 20 20.00 20 SiFiveP600VEXQ1[20],SiFiveP600VectorArith[20] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 11 11.00 11 SiFiveP600VEXQ1[11],SiFiveP600VectorArith[11] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SiFiveP600VEXQ1[14],SiFiveP600VectorArith[14] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 20 20.00 20 SiFiveP600VEXQ1[20],SiFiveP600VectorArith[20] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP600VEXQ1[12],SiFiveP600VectorArith[12] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP600VEXQ1[16],SiFiveP600VectorArith[16] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP600VEXQ1[24],SiFiveP600VectorArith[24] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP600VEXQ1[12],SiFiveP600VectorArith[12] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP600VEXQ1[16],SiFiveP600VectorArith[16] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP600VEXQ1[24],SiFiveP600VectorArith[24] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP600VEXQ1[12],SiFiveP600VectorArith[12] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP600VEXQ1[16],SiFiveP600VectorArith[16] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP600VEXQ1[24],SiFiveP600VectorArith[24] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP600VEXQ1[12],SiFiveP600VectorArith[12] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP600VEXQ1[16],SiFiveP600VectorArith[16] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP600VEXQ1[24],SiFiveP600VectorArith[24] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP600VEXQ1[12],SiFiveP600VectorArith[12] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP600VEXQ1[16],SiFiveP600VectorArith[16] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP600VEXQ1[24],SiFiveP600VectorArith[24] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP600VEXQ1[12],SiFiveP600VectorArith[12] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP600VEXQ1[16],SiFiveP600VectorArith[16] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP600VEXQ1[24],SiFiveP600VectorArith[24] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP600VEXQ1[12],SiFiveP600VectorArith[12] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP600VEXQ1[16],SiFiveP600VectorArith[16] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP600VEXQ1[24],SiFiveP600VectorArith[24] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP600VEXQ1[12],SiFiveP600VectorArith[12] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP600VEXQ1[16],SiFiveP600VectorArith[16] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP600VEXQ1[24],SiFiveP600VectorArith[24] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP600VEXQ1[12],SiFiveP600VectorArith[12] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP600VEXQ1[16],SiFiveP600VectorArith[16] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP600VEXQ1[12],SiFiveP600VectorArith[12] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP600VEXQ1[16],SiFiveP600VectorArith[16] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP600VEXQ1[24],SiFiveP600VectorArith[24] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP600VEXQ1[12],SiFiveP600VectorArith[12] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP600VEXQ1[16],SiFiveP600VectorArith[16] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP600VEXQ1[24],SiFiveP600VectorArith[24] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP600VEXQ1,SiFiveP600VectorArith VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 6 SiFiveP600VEXQ1[12],SiFiveP600VectorArith[12] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 6 SiFiveP600VEXQ1[16],SiFiveP600VectorArith[16] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 6 SiFiveP600VEXQ1[24],SiFiveP600VectorArith[24] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600VectorArith VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VectorArith[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VectorArith[4] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VectorArith[8] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 572.00 - - - - - - 880.00 1692.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmv.v.v v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 - - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vfslide1up.vf v8, v16, ft0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/reduction.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/reduction.test
new file mode 100644
index 0000000000000..766dc87957d15
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/reduction.test
@@ -0,0 +1,1237 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/reduction.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 8 6.00 8 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 5.00 6 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 9.00 12 SiFiveP600VEXQ1[9],SiFiveP600VectorArith[9] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 11.00 14 SiFiveP600VEXQ1[11],SiFiveP600VectorArith[11] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 11.00 16 SiFiveP600VEXQ1[11],SiFiveP600VectorArith[11] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 5.00 6 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 6.00 8 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 12 10.00 12 SiFiveP600VEXQ1[10],SiFiveP600VectorArith[10] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 14 9.00 14 SiFiveP600VEXQ1[9],SiFiveP600VectorArith[9] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 7.00 10 SiFiveP600VEXQ1[7],SiFiveP600VectorArith[7] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 8 6.00 8 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 5.00 6 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 9.00 12 SiFiveP600VEXQ1[9],SiFiveP600VectorArith[9] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 11.00 14 SiFiveP600VEXQ1[11],SiFiveP600VectorArith[11] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 11.00 16 SiFiveP600VEXQ1[11],SiFiveP600VectorArith[11] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 5.00 6 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 6.00 8 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 12 10.00 12 SiFiveP600VEXQ1[10],SiFiveP600VectorArith[10] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 14 9.00 14 SiFiveP600VEXQ1[9],SiFiveP600VectorArith[9] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 7.00 10 SiFiveP600VEXQ1[7],SiFiveP600VectorArith[7] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 8 6.00 8 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 5.00 6 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 9.00 12 SiFiveP600VEXQ1[9],SiFiveP600VectorArith[9] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 11.00 14 SiFiveP600VEXQ1[11],SiFiveP600VectorArith[11] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 11.00 16 SiFiveP600VEXQ1[11],SiFiveP600VectorArith[11] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 5.00 6 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 6.00 8 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 12 10.00 12 SiFiveP600VEXQ1[10],SiFiveP600VectorArith[10] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 14 9.00 14 SiFiveP600VEXQ1[9],SiFiveP600VectorArith[9] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 7.00 10 SiFiveP600VEXQ1[7],SiFiveP600VectorArith[7] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 8 6.00 8 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 5.00 6 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 12 9.00 12 SiFiveP600VEXQ1[9],SiFiveP600VectorArith[9] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 14 11.00 14 SiFiveP600VEXQ1[11],SiFiveP600VectorArith[11] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 11.00 16 SiFiveP600VEXQ1[11],SiFiveP600VectorArith[11] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 5.00 6 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 6.00 8 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 12 10.00 12 SiFiveP600VEXQ1[10],SiFiveP600VectorArith[10] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 14 9.00 14 SiFiveP600VEXQ1[9],SiFiveP600VectorArith[9] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 7.00 10 SiFiveP600VEXQ1[7],SiFiveP600VectorArith[7] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ1,SiFiveP600VectorArith VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SiFiveP600VEXQ1[2],SiFiveP600VectorArith[2] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SiFiveP600VEXQ1[8],SiFiveP600VectorArith[8] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 12 7.00 12 SiFiveP600VEXQ1[7],SiFiveP600VectorArith[7] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 12 7.00 12 SiFiveP600VEXQ1[7],SiFiveP600VectorArith[7] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 12 7.00 12 SiFiveP600VEXQ1[7],SiFiveP600VectorArith[7] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 12 7.00 12 SiFiveP600VEXQ1[7],SiFiveP600VectorArith[7] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SiFiveP600VEXQ1[3],SiFiveP600VectorArith[3] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP600VEXQ1[4],SiFiveP600VectorArith[4] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 5.00 8 SiFiveP600VEXQ1[5],SiFiveP600VectorArith[5] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SiFiveP600VEXQ1[10],SiFiveP600VectorArith[10] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 20 SiFiveP600VEXQ1[20],SiFiveP600VectorArith[20] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 40 40.00 40 SiFiveP600VEXQ1[40],SiFiveP600VectorArith[40] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 80 80.00 80 SiFiveP600VEXQ1[80],SiFiveP600VectorArith[80] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SiFiveP600VEXQ1[10],SiFiveP600VectorArith[10] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 20 SiFiveP600VEXQ1[20],SiFiveP600VectorArith[20] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 40 40.00 40 SiFiveP600VEXQ1[40],SiFiveP600VectorArith[40] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 80 80.00 80 SiFiveP600VEXQ1[80],SiFiveP600VectorArith[80] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SiFiveP600VEXQ1[12],SiFiveP600VectorArith[12] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SiFiveP600VEXQ1[24],SiFiveP600VectorArith[24] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SiFiveP600VEXQ1[48],SiFiveP600VectorArith[48] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SiFiveP600VEXQ1[10],SiFiveP600VectorArith[10] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 16 10.00 16 SiFiveP600VEXQ1[10],SiFiveP600VectorArith[10] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 22 11.00 22 SiFiveP600VEXQ1[11],SiFiveP600VectorArith[11] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 28 11.00 28 SiFiveP600VEXQ1[11],SiFiveP600VectorArith[11] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SiFiveP600VEXQ1[10],SiFiveP600VectorArith[10] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 10.00 16 SiFiveP600VEXQ1[10],SiFiveP600VectorArith[10] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 22 11.00 22 SiFiveP600VEXQ1[11],SiFiveP600VectorArith[11] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 28 11.00 28 SiFiveP600VEXQ1[11],SiFiveP600VectorArith[11] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 12 6.00 12 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 18 6.00 18 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 24 6.00 24 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SiFiveP600VEXQ1[10],SiFiveP600VectorArith[10] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 20 SiFiveP600VEXQ1[20],SiFiveP600VectorArith[20] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 40 40.00 40 SiFiveP600VEXQ1[40],SiFiveP600VectorArith[40] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 80 80.00 80 SiFiveP600VEXQ1[80],SiFiveP600VectorArith[80] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SiFiveP600VEXQ1[10],SiFiveP600VectorArith[10] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 20 SiFiveP600VEXQ1[20],SiFiveP600VectorArith[20] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 40 40.00 40 SiFiveP600VEXQ1[40],SiFiveP600VectorArith[40] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 80 80.00 80 SiFiveP600VEXQ1[80],SiFiveP600VectorArith[80] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 18 6.00 18 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 24 6.00 24 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 30 6.00 30 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 10 6.00 10 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 18 6.00 18 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 24 6.00 24 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 30 6.00 30 SiFiveP600VEXQ1[6],SiFiveP600VectorArith[6] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 294.00 - - - - - - - 1982.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vredand.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - - 6.00 - - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 6.00 - - - vfwredusum.vs v8, v8, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vle-vse-vlm.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vle-vse-vlm.test
new file mode 100644
index 0000000000000..0323b9275db72
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vle-vse-vlm.test
@@ -0,0 +1,381 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vle-vse-vlm.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP600VLD[2] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP600VLD[4] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP600VLD[8] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP600VLD[2] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP600VLD[4] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP600VLD[8] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP600VLD[2] VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP600VLD[4] VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP600VLD[8] VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP600VLD[2] VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP600VLD[4] VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP600VLD[8] VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VST VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VST VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VST VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VST VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP600VST[2] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP600VST[4] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP600VST[8] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VST VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VST VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VST VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP600VST[2] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP600VST[4] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP600VST[8] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VST VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VST VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP600VST[2] VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP600VST[4] VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP600VST[8] VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VST VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP600VST[2] VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP600VST[4] VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP600VST[8] VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VST VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VST VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VST VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VST VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VST VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VST VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VST VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP600VLD[2] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP600VLD[4] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP600VLD[8] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP600VLD[2] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP600VLD[4] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP600VLD[8] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP600VLD[2] VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP600VLD[4] VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP600VLD[8] VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP600VLD VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP600VLD[2] VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP600VLD[4] VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP600VLD[8] VLE64FF_V vle64ff.v v8, (a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 80.00 - - - - - - - - - 139.00 73.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle64ff.v v8, (a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlse-vsse.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlse-vsse.test
new file mode 100644
index 0000000000000..4c96980586ec1
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlse-vsse.test
@@ -0,0 +1,237 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlse-vsse.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VLD[2] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VLD[4] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VLD[8] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VLD[16] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VLD[32] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP600VLD[64] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 126 128.00 * 126 SiFiveP600VLD[128] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VLD[2] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VLD[4] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VLD[8] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VLD[16] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VLD[32] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP600VLD[64] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VLD[2] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VLD[4] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VLD[8] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VLD[16] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VLD[32] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VLD[2] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VLD[4] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VLD[8] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VLD[16] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VST[2] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VST[4] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VST[8] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VST[16] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VST[32] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP600VST[64] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 126 128.00 * 126 SiFiveP600VST[128] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VST[2] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VST[4] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VST[8] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VST[16] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VST[32] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP600VST[64] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VST[2] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VST[4] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VST[8] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VST[16] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VST[32] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VST[2] VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VST[4] VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VST[8] VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VST[16] VSSE64_V vsse64.v v8, (a0), t0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 44.00 - - - - - - - - - 472.00 472.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 128.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 64.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 128.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 64.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsse64.v v8, (a0), t0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlseg-vsseg.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlseg-vsseg.test
new file mode 100644
index 0000000000000..3d672c6c86c82
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlseg-vsseg.test
@@ -0,0 +1,3141 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlseg-vsseg.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP600VLD[140] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP600VLD[108] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLSEG3E64_V vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSEG3E64_V vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP600VLD[140] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSEG4E64_V vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG4E64_V vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP600VLD[32] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP600VLD[52] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 92 92.00 * 92 SiFiveP600VLD[92] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP600VLD[32] VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP600VLD[52] VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLSEG5E32_V vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP600VLD[32] VLSEG5E32_V vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLSEG5E64_V vlseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP600VLD[108] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSEG6E32_V vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSEG6E32_V vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSEG6E64_V vlseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP600VLD[40] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP600VLD[68] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 124 124.00 * 124 SiFiveP600VLD[124] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP600VLD[40] VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP600VLD[68] VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLSEG7E32_V vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP600VLD[40] VLSEG7E32_V vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLSEG7E64_V vlseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP600VLD[140] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG8E32_V vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG8E32_V vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG8E64_V vlseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP600VST[16] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP600VST[140] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP600VST[16] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP600VST[16] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP600VST[16] VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP600VST[18] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP600VST[60] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * 97 SiFiveP600VST[108] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP600VST[18] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP600VST[60] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP600VST[18] VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP600VST[18] VSSEG3E64_V vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSSEG3E64_V vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP600VST[140] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSSEG4E64_V vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSEG4E64_V vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP600VST[22] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP600VST[32] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 41 52.00 * 41 SiFiveP600VST[52] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 81 92.00 * 81 SiFiveP600VST[92] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP600VST[22] VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP600VST[32] VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 41 52.00 * 41 SiFiveP600VST[52] VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP600VST[22] VSSEG5E32_V vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP600VST[32] VSSEG5E32_V vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP600VST[22] VSSEG5E64_V vsseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP600VST[60] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 97 108.00 * 97 SiFiveP600VST[108] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP600VST[60] VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSSEG6E32_V vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSSEG6E32_V vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSSEG6E64_V vsseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP600VST[26] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP600VST[40] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 57 68.00 * 57 SiFiveP600VST[68] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 113 124.00 * 113 SiFiveP600VST[124] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP600VST[26] VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP600VST[40] VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 57 68.00 * 57 SiFiveP600VST[68] VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP600VST[26] VSSEG7E32_V vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP600VST[40] VSSEG7E32_V vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP600VST[26] VSSEG7E64_V vsseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP600VST[140] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSEG8E32_V vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSEG8E32_V vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSEG8E64_V vsseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP600VLD[140] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP600VLD[108] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLSSEG3E64_V vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSSEG3E64_V vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP600VLD[140] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSSEG4E64_V vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSSEG4E64_V vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP600VLD[32] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP600VLD[52] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 92 92.00 * 92 SiFiveP600VLD[92] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP600VLD[32] VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP600VLD[52] VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLSSEG5E32_V vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP600VLD[32] VLSSEG5E32_V vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLSSEG5E64_V vlsseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP600VLD[108] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSSEG6E32_V vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSSEG6E32_V vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSSEG6E64_V vlsseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP600VLD[40] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP600VLD[68] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 124 124.00 * 124 SiFiveP600VLD[124] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP600VLD[40] VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP600VLD[68] VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLSSEG7E32_V vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP600VLD[40] VLSSEG7E32_V vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLSSEG7E64_V vlsseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP600VLD[140] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSSEG8E32_V vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSSEG8E32_V vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSSEG8E64_V vlsseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP600VST[16] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP600VST[140] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP600VST[16] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP600VST[16] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP600VST[16] VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP600VST[18] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP600VST[60] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * 97 SiFiveP600VST[108] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP600VST[18] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP600VST[60] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP600VST[18] VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP600VST[18] VSSSEG3E64_V vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSSSEG3E64_V vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP600VST[140] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSSSEG4E64_V vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSSEG4E64_V vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP600VST[22] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP600VST[32] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 41 52.00 * 41 SiFiveP600VST[52] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 81 92.00 * 81 SiFiveP600VST[92] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP600VST[22] VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP600VST[32] VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 41 52.00 * 41 SiFiveP600VST[52] VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP600VST[22] VSSSEG5E32_V vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP600VST[32] VSSSEG5E32_V vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP600VST[22] VSSSEG5E64_V vssseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP600VST[60] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 97 108.00 * 97 SiFiveP600VST[108] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP600VST[60] VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSSSEG6E32_V vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSSSEG6E32_V vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSSSEG6E64_V vssseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP600VST[26] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP600VST[40] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 57 68.00 * 57 SiFiveP600VST[68] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 113 124.00 * 113 SiFiveP600VST[124] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP600VST[26] VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP600VST[40] VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 57 68.00 * 57 SiFiveP600VST[68] VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP600VST[26] VSSSEG7E32_V vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP600VST[40] VSSSEG7E32_V vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP600VST[26] VSSSEG7E64_V vssseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP600VST[140] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSSEG8E32_V vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSSSEG8E32_V vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSSSEG8E64_V vssseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP600VLD[140] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP600VLD[108] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLSEG3E64FF_V vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSEG3E64FF_V vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP600VLD[140] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLSEG4E64FF_V vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG4E64FF_V vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP600VLD[32] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP600VLD[52] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 92 92.00 * 92 SiFiveP600VLD[92] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP600VLD[32] VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP600VLD[52] VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLSEG5E32FF_V vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP600VLD[32] VLSEG5E32FF_V vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLSEG5E64FF_V vlseg5e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP600VLD[108] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSEG6E32FF_V vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLSEG6E32FF_V vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLSEG6E64FF_V vlseg6e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP600VLD[40] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP600VLD[68] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 124 124.00 * 124 SiFiveP600VLD[124] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP600VLD[40] VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP600VLD[68] VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLSEG7E32FF_V vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP600VLD[40] VLSEG7E32FF_V vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLSEG7E64FF_V vlseg7e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP600VLD[140] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG8E32FF_V vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLSEG8E32FF_V vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLSEG8E64FF_V vlseg8e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP600VLD[140] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP600VLD[108] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLUXSEG3EI64_V vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLUXSEG3EI64_V vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP600VLD[140] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLUXSEG4EI64_V vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLUXSEG4EI64_V vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP600VLD[32] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP600VLD[52] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 92 92.00 * 92 SiFiveP600VLD[92] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP600VLD[32] VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP600VLD[52] VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLUXSEG5EI32_V vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP600VLD[32] VLUXSEG5EI32_V vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLUXSEG5EI64_V vluxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP600VLD[108] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLUXSEG6EI32_V vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLUXSEG6EI32_V vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLUXSEG6EI64_V vluxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP600VLD[40] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP600VLD[68] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 124 124.00 * 124 SiFiveP600VLD[124] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP600VLD[40] VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP600VLD[68] VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLUXSEG7EI32_V vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP600VLD[40] VLUXSEG7EI32_V vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLUXSEG7EI64_V vluxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP600VLD[140] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLUXSEG8EI32_V vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLUXSEG8EI32_V vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLUXSEG8EI64_V vluxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP600VLD[140] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP600VLD[16] VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP600VLD[108] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 18 18.00 * 18 SiFiveP600VLD[18] VLOXSEG3EI64_V vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLOXSEG3EI64_V vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP600VLD[140] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP600VLD[20] VLOXSEG4EI64_V vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLOXSEG4EI64_V vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP600VLD[32] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP600VLD[52] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 92 92.00 * 92 SiFiveP600VLD[92] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP600VLD[32] VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 52 52.00 * 52 SiFiveP600VLD[52] VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLOXSEG5EI32_V vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SiFiveP600VLD[32] VLOXSEG5EI32_V vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 22 22.00 * 22 SiFiveP600VLD[22] VLOXSEG5EI64_V vloxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 108 108.00 * 108 SiFiveP600VLD[108] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * 60 SiFiveP600VLD[60] VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLOXSEG6EI32_V vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * 36 SiFiveP600VLD[36] VLOXSEG6EI32_V vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SiFiveP600VLD[24] VLOXSEG6EI64_V vloxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP600VLD[40] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP600VLD[68] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 124 124.00 * 124 SiFiveP600VLD[124] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP600VLD[40] VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 68 68.00 * 68 SiFiveP600VLD[68] VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLOXSEG7EI32_V vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SiFiveP600VLD[40] VLOXSEG7EI32_V vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 26.00 * 26 SiFiveP600VLD[26] VLOXSEG7EI64_V vloxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 140 140.00 * 140 SiFiveP600VLD[140] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP600VLD[76] VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLOXSEG8EI32_V vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP600VLD[44] VLOXSEG8EI32_V vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP600VLD[28] VLOXSEG8EI64_V vloxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP600VST[16] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP600VST[16] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP600VST[16] VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP600VST[16] VSUXSEG2EI64_V vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSUXSEG2EI64_V vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP600VST[18] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP600VST[60] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * 97 SiFiveP600VST[108] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP600VST[18] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP600VST[60] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP600VST[18] VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP600VST[18] VSUXSEG3EI64_V vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSUXSEG3EI64_V vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP600VST[140] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSUXSEG4EI64_V vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSUXSEG4EI64_V vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP600VST[22] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP600VST[32] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 41 52.00 * 41 SiFiveP600VST[52] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 81 92.00 * 81 SiFiveP600VST[92] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP600VST[22] VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP600VST[32] VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 41 52.00 * 41 SiFiveP600VST[52] VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP600VST[22] VSUXSEG5EI32_V vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP600VST[32] VSUXSEG5EI32_V vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP600VST[22] VSUXSEG5EI64_V vsuxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP600VST[60] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 97 108.00 * 97 SiFiveP600VST[108] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP600VST[60] VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSUXSEG6EI32_V vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSUXSEG6EI32_V vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSUXSEG6EI64_V vsuxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP600VST[26] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP600VST[40] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 57 68.00 * 57 SiFiveP600VST[68] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 113 124.00 * 113 SiFiveP600VST[124] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP600VST[26] VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP600VST[40] VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 57 68.00 * 57 SiFiveP600VST[68] VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP600VST[26] VSUXSEG7EI32_V vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP600VST[40] VSUXSEG7EI32_V vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP600VST[26] VSUXSEG7EI64_V vsuxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP600VST[140] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSUXSEG8EI32_V vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSUXSEG8EI32_V vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSUXSEG8EI64_V vsuxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP600VST[16] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP600VST[140] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP600VST[16] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP600VST[16] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP600VST[16] VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP600VST[18] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP600VST[60] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * 97 SiFiveP600VST[108] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP600VST[18] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP600VST[60] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP600VST[18] VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 18.00 * 7 SiFiveP600VST[18] VSOXSEG3EI64_V vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSOXSEG3EI64_V vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP600VST[140] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP600VST[20] VSOXSEG4EI64_V vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSOXSEG4EI64_V vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP600VST[22] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP600VST[32] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 41 52.00 * 41 SiFiveP600VST[52] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 81 92.00 * 81 SiFiveP600VST[92] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP600VST[22] VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP600VST[32] VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 41 52.00 * 41 SiFiveP600VST[52] VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP600VST[22] VSOXSEG5EI32_V vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 21 32.00 * 21 SiFiveP600VST[32] VSOXSEG5EI32_V vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 11 22.00 * 11 SiFiveP600VST[22] VSOXSEG5EI64_V vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP600VST[60] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 97 108.00 * 97 SiFiveP600VST[108] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * 49 SiFiveP600VST[60] VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSOXSEG6EI32_V vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * 25 SiFiveP600VST[36] VSOXSEG6EI32_V vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * 13 SiFiveP600VST[24] VSOXSEG6EI64_V vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP600VST[26] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP600VST[40] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 57 68.00 * 57 SiFiveP600VST[68] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 113 124.00 * 113 SiFiveP600VST[124] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP600VST[26] VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP600VST[40] VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 57 68.00 * 57 SiFiveP600VST[68] VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP600VST[26] VSOXSEG7EI32_V vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 29 40.00 * 29 SiFiveP600VST[40] VSOXSEG7EI32_V vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 15 26.00 * 15 SiFiveP600VST[26] VSOXSEG7EI64_V vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 129 140.00 * 129 SiFiveP600VST[140] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP600VST[76] VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSOXSEG8EI32_V vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP600VST[44] VSOXSEG8EI32_V vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP600VST[28] VSOXSEG8EI64_V vsoxseg8ei64.v v8, (a0), v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 24.00 vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 26.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 40.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 68.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 124.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 26.00 vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 40.00 vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 68.00 vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 26.00 vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 40.00 vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 26.00 vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 28.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 44.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 76.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 140.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 28.00 vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 44.00 vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 76.00 vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 28.00 vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 44.00 vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 28.00 vsoxseg8ei64.v v8, (a0), v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlxe-vsxe.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlxe-vsxe.test
new file mode 100644
index 0000000000000..4f3e19a81bb7e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/vlxe-vsxe.test
@@ -0,0 +1,413 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlxe-vsxe.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VLD[2] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VLD[4] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VLD[8] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VLD[16] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VLD[32] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP600VLD[64] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 126 128.00 * 126 SiFiveP600VLD[128] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VLD[2] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VLD[4] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VLD[8] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VLD[16] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VLD[32] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP600VLD[64] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VLD[2] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VLD[4] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VLD[8] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VLD[16] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VLD[32] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VLD[2] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VLD[4] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VLD[8] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VLD[16] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VLD[2] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VLD[4] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VLD[8] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VLD[16] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VLD[32] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP600VLD[64] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 126 128.00 * 126 SiFiveP600VLD[128] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VLD[2] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VLD[4] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VLD[8] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VLD[16] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VLD[32] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP600VLD[64] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VLD[2] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VLD[4] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VLD[8] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VLD[16] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VLD[32] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VLD[2] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VLD[4] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VLD[8] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VLD[16] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VST[2] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VST[4] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VST[8] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VST[16] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VST[32] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP600VST[64] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 126 128.00 * 126 SiFiveP600VST[128] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VST[2] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VST[4] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VST[8] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VST[16] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VST[32] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP600VST[64] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VST[2] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VST[4] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VST[8] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VST[16] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VST[32] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VST[2] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VST[4] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VST[8] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VST[16] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VST[2] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VST[4] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VST[8] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VST[16] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VST[32] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP600VST[64] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 126 128.00 * 126 SiFiveP600VST[128] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VST[2] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VST[4] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VST[8] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VST[16] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VST[32] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 62 64.00 * 62 SiFiveP600VST[64] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VST[2] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VST[4] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VST[8] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VST[16] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 30 32.00 * 30 SiFiveP600VST[32] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * 13 SiFiveP600VST[2] VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 18 4.00 * 18 SiFiveP600VST[4] VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 22 8.00 * 22 SiFiveP600VST[8] VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 30 16.00 * 30 SiFiveP600VST[16] VSOXEI64_V vsoxei64.v v8, (a0), v0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 88.00 - - - - - - - - - 944.00 944.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 128.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 128.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 64.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 128.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 64.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 64.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 128.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 64.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsoxei64.v v8, (a0), v0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvbb.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s
rename to llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvbb.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvbc.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvbc.test
new file mode 100644
index 0000000000000..9aa037449d3bc
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvbc.test
@@ -0,0 +1,101 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/zvbc.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VCLMUL_VV vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VCLMUL_VX vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VCLMULH_VV vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600VEXQ0,SiFiveP600VectorArith VCLMULH_VX vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCLMUL_VV vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCLMUL_VX vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCLMULH_VV vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP600VEXQ0[2],SiFiveP600VectorArith[2] VCLMULH_VX vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VCLMUL_VV vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VCLMUL_VX vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VCLMULH_VV vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 4 4.00 4 SiFiveP600VEXQ0[4],SiFiveP600VectorArith[4] VCLMULH_VX vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VCLMUL_VV vclmul.vv v8, v12, v24
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VCLMUL_VX vclmul.vx v8, v12, a0
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VCLMULH_VV vclmulh.vv v8, v12, v24
+# CHECK-NEXT: 1 8 8.00 8 SiFiveP600VEXQ0[8],SiFiveP600VectorArith[8] VCLMULH_VX vclmulh.vx v8, v12, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 4.00 - - - - - - 60.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmul.vv v8, v12, v24
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmul.vx v8, v12, a0
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmulh.vv v8, v12, v24
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmulh.vx v8, v12, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkg.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvkg.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkg.s
rename to llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvkg.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvkned.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s
rename to llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvkned.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvknhb.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s
rename to llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvknhb.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksed.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvksed.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksed.s
rename to llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvksed.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvksh.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s
rename to llvm/test/tools/llvm-mca/RISCV/SiFiveP600/rvv/zvksh.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s
deleted file mode 100644
index cc972c6d63454..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s
+++ /dev/null
@@ -1,545 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, mf4, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, mf2, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, m1, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, m2, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, m4, ta, ma
-vle8.v v8, (a0)
-vsetvli zero, zero, e8, m8, ta, ma
-vle8.v v8, (a0)
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vle16.v v8, (a0)
-vsetvli zero, zero, e16, mf2, ta, ma
-vle16.v v8, (a0)
-vsetvli zero, zero, e16, m1, ta, ma
-vle16.v v8, (a0)
-vsetvli zero, zero, e16, m2, ta, ma
-vle16.v v8, (a0)
-vsetvli zero, zero, e16, m4, ta, ma
-vle16.v v8, (a0)
-vsetvli zero, zero, e16, m8, ta, ma
-vle16.v v8, (a0)
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vle32.v v8, (a0)
-vsetvli zero, zero, e32, m1, ta, ma
-vle32.v v8, (a0)
-vsetvli zero, zero, e32, m2, ta, ma
-vle32.v v8, (a0)
-vsetvli zero, zero, e32, m4, ta, ma
-vle32.v v8, (a0)
-vsetvli zero, zero, e32, m8, ta, ma
-vle32.v v8, (a0)
-
-vsetvli zero, zero, e64, m1, ta, ma
-vle64.v v8, (a0)
-vsetvli zero, zero, e64, m2, ta, ma
-vle64.v v8, (a0)
-vsetvli zero, zero, e64, m4, ta, ma
-vle64.v v8, (a0)
-vsetvli zero, zero, e64, m8, ta, ma
-vle64.v v8, (a0)
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, mf4, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, mf2, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, m1, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, m2, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, m4, ta, ma
-vse8.v v8, (a0)
-vsetvli zero, zero, e8, m8, ta, ma
-vse8.v v8, (a0)
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vse16.v v8, (a0)
-vsetvli zero, zero, e16, mf2, ta, ma
-vse16.v v8, (a0)
-vsetvli zero, zero, e16, m1, ta, ma
-vse16.v v8, (a0)
-vsetvli zero, zero, e16, m2, ta, ma
-vse16.v v8, (a0)
-vsetvli zero, zero, e16, m4, ta, ma
-vse16.v v8, (a0)
-vsetvli zero, zero, e16, m8, ta, ma
-vse16.v v8, (a0)
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vse32.v v8, (a0)
-vsetvli zero, zero, e32, m1, ta, ma
-vse32.v v8, (a0)
-vsetvli zero, zero, e32, m2, ta, ma
-vse32.v v8, (a0)
-vsetvli zero, zero, e32, m4, ta, ma
-vse32.v v8, (a0)
-vsetvli zero, zero, e32, m8, ta, ma
-vse32.v v8, (a0)
-
-vsetvli zero, zero, e64, m1, ta, ma
-vse64.v v8, (a0)
-vsetvli zero, zero, e64, m2, ta, ma
-vse64.v v8, (a0)
-vsetvli zero, zero, e64, m4, ta, ma
-vse64.v v8, (a0)
-vsetvli zero, zero, e64, m8, ta, ma
-vse64.v v8, (a0)
-
-# Unit-stride mask load/store
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, mf4, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, mf2, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, m1, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, m2, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, m4, ta, ma
-vlm.v v8, (a0)
-vsetvli zero, zero, e8, m8, ta, ma
-vlm.v v8, (a0)
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, mf4, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, mf2, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, m1, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, m2, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, m4, ta, ma
-vsm.v v8, (a0)
-vsetvli zero, zero, e8, m8, ta, ma
-vsm.v v8, (a0)
-
-# Fault-only-first
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, mf4, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, mf2, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, m1, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, m2, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, m4, ta, ma
-vle8ff.v v8, (a0)
-vsetvli zero, zero, e8, m8, ta, ma
-vle8ff.v v8, (a0)
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vle16ff.v v8, (a0)
-vsetvli zero, zero, e16, mf2, ta, ma
-vle16ff.v v8, (a0)
-vsetvli zero, zero, e16, m1, ta, ma
-vle16ff.v v8, (a0)
-vsetvli zero, zero, e16, m2, ta, ma
-vle16ff.v v8, (a0)
-vsetvli zero, zero, e16, m4, ta, ma
-vle16ff.v v8, (a0)
-vsetvli zero, zero, e16, m8, ta, ma
-vle16ff.v v8, (a0)
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vle32ff.v v8, (a0)
-vsetvli zero, zero, e32, m1, ta, ma
-vle32ff.v v8, (a0)
-vsetvli zero, zero, e32, m2, ta, ma
-vle32ff.v v8, (a0)
-vsetvli zero, zero, e32, m4, ta, ma
-vle32ff.v v8, (a0)
-vsetvli zero, zero, e32, m8, ta, ma
-vle32ff.v v8, (a0)
-
-vsetvli zero, zero, e64, m1, ta, ma
-vle64ff.v v8, (a0)
-vsetvli zero, zero, e64, m2, ta, ma
-vle64ff.v v8, (a0)
-vsetvli zero, zero, e64, m4, ta, ma
-vle64ff.v v8, (a0)
-vsetvli zero, zero, e64, m8, ta, ma
-vle64ff.v v8, (a0)
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 160
-# CHECK-NEXT: Total Cycles: 146
-# CHECK-NEXT: Total uOps: 160
-
-# CHECK: Dispatch Width: 4
-# CHECK-NEXT: uOps Per Cycle: 1.10
-# CHECK-NEXT: IPC: 1.10
-# CHECK-NEXT: Block RThroughput: 139.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vle32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vle32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vle32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vle64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vle64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vle64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vse32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vse32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vse32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vse64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vse64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vse64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vse64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vle32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vle32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vle32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 8 1.00 * vle64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 8 2.00 * vle64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 8 4.00 * vle64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 8 8.00 * vle64ff.v v8, (a0)
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP600Div
-# CHECK-NEXT: [1] - SiFiveP600FEXQ0
-# CHECK-NEXT: [2] - SiFiveP600FEXQ1
-# CHECK-NEXT: [3] - SiFiveP600FloatDiv
-# CHECK-NEXT: [4] - SiFiveP600IEXQ0
-# CHECK-NEXT: [5] - SiFiveP600IEXQ1
-# CHECK-NEXT: [6] - SiFiveP600IEXQ2
-# CHECK-NEXT: [7] - SiFiveP600IEXQ3
-# CHECK-NEXT: [8.0] - SiFiveP600LDST
-# CHECK-NEXT: [8.1] - SiFiveP600LDST
-# CHECK-NEXT: [9] - SiFiveP600VDiv
-# CHECK-NEXT: [10] - SiFiveP600VEXQ0
-# CHECK-NEXT: [11] - SiFiveP600VEXQ1
-# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
-# CHECK-NEXT: [13] - SiFiveP600VLD
-# CHECK-NEXT: [14] - SiFiveP600VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
-# CHECK-NEXT: - - - - 80.00 - - - - - - - - - 139.00 73.00
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vse8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vse8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vse8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vse16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vse16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vse16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vse32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vse32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vse32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vse64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vse64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vse64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle8ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle8ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle8ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle16ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle16ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle16ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle32ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle32ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle32ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle64ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle64ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle64ff.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle64ff.v v8, (a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s
deleted file mode 100644
index 418eda5f3b145..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s
+++ /dev/null
@@ -1,319 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, mf4, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, mf2, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m1, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m2, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m4, ta, ma
-vlse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m8, ta, ma
-vlse8.v v8, (a0), t0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vlse16.v v8, (a0), t0
-vsetvli zero, zero, e16, mf2, ta, ma
-vlse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m1, ta, ma
-vlse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m2, ta, ma
-vlse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m4, ta, ma
-vlse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m8, ta, ma
-vlse16.v v8, (a0), t0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vlse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m1, ta, ma
-vlse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m2, ta, ma
-vlse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m4, ta, ma
-vlse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m8, ta, ma
-vlse32.v v8, (a0), t0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vlse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m2, ta, ma
-vlse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m4, ta, ma
-vlse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m8, ta, ma
-vlse64.v v8, (a0), t0
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, mf4, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, mf2, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m1, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m2, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m4, ta, ma
-vsse8.v v8, (a0), t0
-vsetvli zero, zero, e8, m8, ta, ma
-vsse8.v v8, (a0), t0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vsse16.v v8, (a0), t0
-vsetvli zero, zero, e16, mf2, ta, ma
-vsse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m1, ta, ma
-vsse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m2, ta, ma
-vsse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m4, ta, ma
-vsse16.v v8, (a0), t0
-vsetvli zero, zero, e16, m8, ta, ma
-vsse16.v v8, (a0), t0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vsse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m1, ta, ma
-vsse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m2, ta, ma
-vsse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m4, ta, ma
-vsse32.v v8, (a0), t0
-vsetvli zero, zero, e32, m8, ta, ma
-vsse32.v v8, (a0), t0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vsse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m2, ta, ma
-vsse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m4, ta, ma
-vsse64.v v8, (a0), t0
-vsetvli zero, zero, e64, m8, ta, ma
-vsse64.v v8, (a0), t0
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 88
-# CHECK-NEXT: Total Cycles: 954
-# CHECK-NEXT: Total uOps: 88
-
-# CHECK: Dispatch Width: 4
-# CHECK-NEXT: uOps Per Cycle: 0.09
-# CHECK-NEXT: IPC: 0.09
-# CHECK-NEXT: Block RThroughput: 472.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 126 128.00 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vlse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vlse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vlse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vlse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vlse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vlse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vlse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vlse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vlse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 126 128.00 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsse64.v v8, (a0), t0
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP600Div
-# CHECK-NEXT: [1] - SiFiveP600FEXQ0
-# CHECK-NEXT: [2] - SiFiveP600FEXQ1
-# CHECK-NEXT: [3] - SiFiveP600FloatDiv
-# CHECK-NEXT: [4] - SiFiveP600IEXQ0
-# CHECK-NEXT: [5] - SiFiveP600IEXQ1
-# CHECK-NEXT: [6] - SiFiveP600IEXQ2
-# CHECK-NEXT: [7] - SiFiveP600IEXQ3
-# CHECK-NEXT: [8.0] - SiFiveP600LDST
-# CHECK-NEXT: [8.1] - SiFiveP600LDST
-# CHECK-NEXT: [9] - SiFiveP600VDiv
-# CHECK-NEXT: [10] - SiFiveP600VEXQ0
-# CHECK-NEXT: [11] - SiFiveP600VEXQ1
-# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
-# CHECK-NEXT: [13] - SiFiveP600VLD
-# CHECK-NEXT: [14] - SiFiveP600VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
-# CHECK-NEXT: - - - - 44.00 - - - - - - - - - 472.00 472.00
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 128.00 - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vlse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vlse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vlse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vlse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vlse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vlse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vlse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 64.00 vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 128.00 vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 64.00 vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsse64.v v8, (a0), t0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s
deleted file mode 100644
index e690dbebfb26a..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s
+++ /dev/null
@@ -1,4730 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vlseg2e8.v v8,(a0)
-vsetvli zero, zero, e8, mf4, tu, mu
-vlseg2e8.v v8,(a0)
-vsetvli zero, zero, e8, mf2, tu, mu
-vlseg2e8.v v8,(a0)
-vsetvli zero, zero, e8, m1, tu, mu
-vlseg2e8.v v8,(a0)
-vsetvli zero, zero, e8, m2, tu, mu
-vlseg2e8.v v8,(a0)
-vsetvli zero, zero, e8, m4, tu, mu
-vlseg2e8.v v8,(a0)
-vsetvli zero, zero, e16, mf4, tu, mu
-vlseg2e16.v v8,(a0)
-vsetvli zero, zero, e16, mf2, tu, mu
-vlseg2e16.v v8,(a0)
-vsetvli zero, zero, e16, m1, tu, mu
-vlseg2e16.v v8,(a0)
-vsetvli zero, zero, e16, m2, tu, mu
-vlseg2e16.v v8,(a0)
-vsetvli zero, zero, e16, m4, tu, mu
-vlseg2e16.v v8,(a0)
-vsetvli zero, zero, e32, mf2, tu, mu
-vlseg2e32.v v8,(a0)
-vsetvli zero, zero, e32, m1, tu, mu
-vlseg2e32.v v8,(a0)
-vsetvli zero, zero, e32, m2, tu, mu
-vlseg2e32.v v8,(a0)
-vsetvli zero, zero, e32, m4, tu, mu
-vlseg2e32.v v8,(a0)
-vsetvli zero, zero, e64, m1, tu, mu
-vlseg2e64.v v8,(a0)
-vsetvli zero, zero, e64, m2, tu, mu
-vlseg2e64.v v8,(a0)
-vsetvli zero, zero, e64, m4, tu, mu
-vlseg2e64.v v8,(a0)
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vlseg3e8.v v8,(a0)
-vsetvli zero, zero, e8, mf4, tu, mu
-vlseg3e8.v v8,(a0)
-vsetvli zero, zero, e8, mf2, tu, mu
-vlseg3e8.v v8,(a0)
-vsetvli zero, zero, e8, m1, tu, mu
-vlseg3e8.v v8,(a0)
-vsetvli zero, zero, e8, m2, tu, mu
-vlseg3e8.v v8,(a0)
-vsetvli zero, zero, e16, mf4, tu, mu
-vlseg3e16.v v8,(a0)
-vsetvli zero, zero, e16, mf2, tu, mu
-vlseg3e16.v v8,(a0)
-vsetvli zero, zero, e16, m1, tu, mu
-vlseg3e16.v v8,(a0)
-vsetvli zero, zero, e16, m2, tu, mu
-vlseg3e16.v v8,(a0)
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-vsuxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsuxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsuxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsuxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsuxseg5ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsuxseg5ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsuxseg5ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsuxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsuxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsuxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsuxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsuxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsuxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsuxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsuxseg6ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsuxseg6ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsuxseg6ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsuxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsuxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsuxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsuxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsuxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsuxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsuxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsuxseg7ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsuxseg7ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsuxseg7ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsuxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsuxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsuxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsuxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsuxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsuxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsuxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsuxseg8ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsuxseg8ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsuxseg8ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m2, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m4, tu, mu
-vsoxseg2ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m2, tu, mu
-vsoxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m4, tu, mu
-vsoxseg2ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg2ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg2ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m2, tu, mu
-vsoxseg2ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m4, tu, mu
-vsoxseg2ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg2ei64.v v8, (a0), v16
-vsetvli zero, zero, e64, m2, tu, mu
-vsoxseg2ei64.v v8, (a0), v16
-vsetvli zero, zero, e64, m4, tu, mu
-vsoxseg2ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m2, tu, mu
-vsoxseg3ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg3ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg3ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg3ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m2, tu, mu
-vsoxseg3ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg3ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg3ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m2, tu, mu
-vsoxseg3ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg3ei64.v v8, (a0), v16
-vsetvli zero, zero, e64, m2, tu, mu
-vsoxseg3ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m2, tu, mu
-vsoxseg4ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m2, tu, mu
-vsoxseg4ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg4ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg4ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m2, tu, mu
-vsoxseg4ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg4ei64.v v8, (a0), v16
-vsetvli zero, zero, e64, m2, tu, mu
-vsoxseg4ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg5ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg5ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg5ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg5ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg5ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg6ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg6ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg6ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg6ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg6ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg7ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg7ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg7ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg7ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg7ei64.v v8, (a0), v16
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vsoxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vsoxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vsoxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e8, m1, tu, mu
-vsoxseg8ei8.v v8, (a0), v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vsoxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vsoxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e16, m1, tu, mu
-vsoxseg8ei16.v v8, (a0), v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vsoxseg8ei32.v v8, (a0), v16
-vsetvli zero, zero, e32, m1, tu, mu
-vsoxseg8ei32.v v8, (a0), v16
-vsetvli zero, zero, e64, m1, tu, mu
-vsoxseg8ei64.v v8, (a0), v16
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 1540
-# CHECK-NEXT: Total Cycles: 25109
-# CHECK-NEXT: Total uOps: 1540
-
-# CHECK: Dispatch Width: 4
-# CHECK-NEXT: uOps Per Cycle: 0.06
-# CHECK-NEXT: IPC: 0.06
-# CHECK-NEXT: Block RThroughput: 18160.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vlseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlseg3e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg3e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg4e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg4e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vlseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 92 92.00 * vlseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vlseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlseg5e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlseg5e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlseg5e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vlseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg6e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg6e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg6e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vlseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 124 124.00 * vlseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vlseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlseg7e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlseg7e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlseg7e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg8e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg8e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg8e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 97 108.00 * vsseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsseg3e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsseg3e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vsseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsseg4e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg4e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 41 52.00 * vsseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 81 92.00 * vsseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 41 52.00 * vsseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsseg5e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsseg5e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsseg5e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 97 108.00 * vsseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsseg6e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsseg6e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsseg6e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 57 68.00 * vsseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 113 124.00 * vsseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 57 68.00 * vsseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsseg7e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsseg7e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsseg7e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vsseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg8e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsseg8e32.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsseg8e64.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlsseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlsseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlsseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlsseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlsseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlsseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlsseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlsseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlsseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlsseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlsseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vlsseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlsseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlsseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlsseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlsseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlsseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlsseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlsseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlsseg3e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlsseg3e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlsseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlsseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlsseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlsseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlsseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlsseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlsseg4e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg4e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlsseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlsseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vlsseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 92 92.00 * vlsseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlsseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlsseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vlsseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlsseg5e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlsseg5e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlsseg5e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlsseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlsseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlsseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vlsseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlsseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlsseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlsseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlsseg6e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlsseg6e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlsseg6e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlsseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlsseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vlsseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 124 124.00 * vlsseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlsseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlsseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vlsseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlsseg7e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlsseg7e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlsseg7e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlsseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlsseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlsseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg8e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlsseg8e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlsseg8e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vssseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vssseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vssseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vssseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vssseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vssseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vssseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vssseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vssseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vssseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vssseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 97 108.00 * vssseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vssseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vssseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vssseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vssseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vssseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vssseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vssseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vssseg3e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vssseg3e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vssseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vssseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vssseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vssseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vssseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vssseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vssseg4e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg4e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vssseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vssseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 41 52.00 * vssseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 81 92.00 * vssseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vssseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vssseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 41 52.00 * vssseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vssseg5e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vssseg5e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vssseg5e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vssseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vssseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vssseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 97 108.00 * vssseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vssseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vssseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vssseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vssseg6e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vssseg6e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vssseg6e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vssseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vssseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 57 68.00 * vssseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 113 124.00 * vssseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vssseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vssseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 57 68.00 * vssseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vssseg7e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vssseg7e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vssseg7e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vssseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vssseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vssseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg8e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vssseg8e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vssseg8e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlseg2e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg2e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg2e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg2e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg2e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlseg2e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg2e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg2e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg2e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vlseg2e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg2e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg2e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlseg3e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg3e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg3e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlseg3e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vlseg3e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlseg3e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg3e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg3e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlseg3e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlseg3e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg3e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg3e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vlseg3e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg3e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg4e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg4e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg4e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg4e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlseg4e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg4e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg4e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg4e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg4e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg4e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg4e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg4e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vlseg4e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg4e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlseg5e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlseg5e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vlseg5e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 92 92.00 * vlseg5e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlseg5e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlseg5e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vlseg5e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlseg5e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vlseg5e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vlseg5e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg6e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg6e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlseg6e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vlseg6e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg6e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg6e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vlseg6e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg6e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vlseg6e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vlseg6e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlseg7e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlseg7e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vlseg7e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 124 124.00 * vlseg7e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlseg7e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlseg7e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vlseg7e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlseg7e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vlseg7e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vlseg7e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg8e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg8e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg8e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vlseg8e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg8e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg8e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vlseg8e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg8e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vlseg8e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vlseg8e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vluxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vluxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vluxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vluxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vluxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vluxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vluxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vluxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vluxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vluxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vluxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vluxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vluxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vluxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vluxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vluxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vluxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vluxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vluxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vluxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vluxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 92 92.00 * vluxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vluxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vluxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vluxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vluxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vluxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vluxseg5ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vluxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vluxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vluxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vluxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vluxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vluxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vluxseg6ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vluxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vluxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vluxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 124 124.00 * vluxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vluxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vluxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vluxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vluxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vluxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vluxseg7ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vluxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vluxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vluxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vluxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vluxseg8ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vloxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vloxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vloxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vloxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vloxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 16 16.00 * vloxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vloxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vloxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vloxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vloxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vloxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vloxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vloxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vloxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vloxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vloxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vloxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vloxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vloxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 18 18.00 * vloxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vloxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vloxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vloxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vloxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vloxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vloxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vloxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 20 20.00 * vloxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vloxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vloxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vloxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 92 92.00 * vloxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vloxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vloxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 52 52.00 * vloxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vloxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 32 32.00 * vloxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 22 22.00 * vloxseg5ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vloxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vloxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vloxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 108 108.00 * vloxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vloxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vloxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 60 60.00 * vloxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vloxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 36 36.00 * vloxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 24 24.00 * vloxseg6ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vloxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vloxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vloxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 124 124.00 * vloxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vloxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vloxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 68 68.00 * vloxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vloxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 40 40.00 * vloxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 26 26.00 * vloxseg7ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vloxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 140 140.00 * vloxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 76 76.00 * vloxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 44 44.00 * vloxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 28 28.00 * vloxseg8ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsuxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsuxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsuxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsuxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsuxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsuxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsuxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsuxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsuxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsuxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsuxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsuxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsuxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsuxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsuxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 97 108.00 * vsuxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsuxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsuxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsuxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsuxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsuxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsuxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsuxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsuxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsuxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsuxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsuxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsuxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vsuxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsuxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsuxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsuxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsuxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsuxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsuxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsuxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsuxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 41 52.00 * vsuxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 81 92.00 * vsuxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsuxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsuxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 41 52.00 * vsuxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsuxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsuxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsuxseg5ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsuxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsuxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsuxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 97 108.00 * vsuxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsuxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsuxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsuxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsuxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsuxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsuxseg6ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsuxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsuxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 57 68.00 * vsuxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 113 124.00 * vsuxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsuxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsuxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 57 68.00 * vsuxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsuxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsuxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsuxseg7ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsuxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsuxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vsuxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsuxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsuxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsuxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsuxseg8ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsoxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsoxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsoxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsoxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsoxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 5 16.00 * vsoxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsoxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 97 108.00 * vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsoxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsoxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsoxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsoxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsoxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsoxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsoxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 7 18.00 * vsoxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsoxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsoxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsoxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsoxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 9 20.00 * vsoxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 41 52.00 * vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 81 92.00 * vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsoxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsoxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 41 52.00 * vsoxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsoxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 21 32.00 * vsoxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 11 22.00 * vsoxseg5ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 97 108.00 * vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsoxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsoxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 49 60.00 * vsoxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsoxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 25 36.00 * vsoxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 13 24.00 * vsoxseg6ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 57 68.00 * vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 113 124.00 * vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsoxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsoxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 57 68.00 * vsoxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsoxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 29 40.00 * vsoxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 15 26.00 * vsoxseg7ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 129 140.00 * vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 65 76.00 * vsoxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 33 44.00 * vsoxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 17 28.00 * vsoxseg8ei64.v v8, (a0), v16
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP600Div
-# CHECK-NEXT: [1] - SiFiveP600FEXQ0
-# CHECK-NEXT: [2] - SiFiveP600FEXQ1
-# CHECK-NEXT: [3] - SiFiveP600FloatDiv
-# CHECK-NEXT: [4] - SiFiveP600IEXQ0
-# CHECK-NEXT: [5] - SiFiveP600IEXQ1
-# CHECK-NEXT: [6] - SiFiveP600IEXQ2
-# CHECK-NEXT: [7] - SiFiveP600IEXQ3
-# CHECK-NEXT: [8.0] - SiFiveP600LDST
-# CHECK-NEXT: [8.1] - SiFiveP600LDST
-# CHECK-NEXT: [9] - SiFiveP600VDiv
-# CHECK-NEXT: [10] - SiFiveP600VEXQ0
-# CHECK-NEXT: [11] - SiFiveP600VEXQ1
-# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
-# CHECK-NEXT: [13] - SiFiveP600VLD
-# CHECK-NEXT: [14] - SiFiveP600VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
-# CHECK-NEXT: - - - - 770.00 - - - - - - - - - 18160.00 14240.00
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 20.00 - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 28.00 - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 44.00 - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 76.00 - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 140.00 - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlseg2e16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 20.00 - vlseg2e16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 28.00 - vlseg2e16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 44.00 - vlseg2e16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 76.00 - vlseg2e16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlseg2e32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 20.00 - vlseg2e32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 28.00 - vlseg2e32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 44.00 - vlseg2e32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlseg2e64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 20.00 - vlseg2e64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 28.00 - vlseg2e64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 18.00 - vlseg3e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 24.00 - vlseg3e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 36.00 - vlseg3e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 60.00 - vlseg3e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 108.00 - vlseg3e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 18.00 - vlseg3e16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 24.00 - vlseg3e16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 36.00 - vlseg3e16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 60.00 - vlseg3e16.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 18.00 - vlseg3e32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 24.00 - vlseg3e32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 36.00 - vlseg3e32.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 18.00 - vlseg3e64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 24.00 - vlseg3e64.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 20.00 - vlseg4e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 28.00 - vlseg4e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 44.00 - vlseg4e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 76.00 - vlseg4e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 140.00 - vlseg4e8.v v8, (a0)
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - 20.00 - vlseg4e16.v v8, (a0)
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-# CHECK-NEXT: - - - - - - - - - - - - - - - 20.00 vsoxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 28.00 vsoxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 44.00 vsoxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsoxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 20.00 vsoxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 28.00 vsoxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 18.00 vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 24.00 vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 36.00 vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 60.00 vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 108.00 vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 18.00 vsoxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 24.00 vsoxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 36.00 vsoxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 60.00 vsoxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 18.00 vsoxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 24.00 vsoxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 36.00 vsoxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 18.00 vsoxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 24.00 vsoxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 20.00 vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 28.00 vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 44.00 vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 76.00 vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 140.00 vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 20.00 vsoxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 28.00 vsoxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 44.00 vsoxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 76.00 vsoxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 20.00 vsoxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 28.00 vsoxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 44.00 vsoxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 20.00 vsoxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 28.00 vsoxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 22.00 vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 52.00 vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 92.00 vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 22.00 vsoxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsoxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 52.00 vsoxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 22.00 vsoxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsoxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 22.00 vsoxseg5ei64.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 24.00 vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 36.00 vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 60.00 vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 108.00 vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 24.00 vsoxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 36.00 vsoxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 60.00 vsoxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 24.00 vsoxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 36.00 vsoxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 24.00 vsoxseg6ei64.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 26.00 vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 40.00 vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 68.00 vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 124.00 vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 26.00 vsoxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 40.00 vsoxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 68.00 vsoxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 26.00 vsoxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 40.00 vsoxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 26.00 vsoxseg7ei64.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 28.00 vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 44.00 vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 76.00 vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 140.00 vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 28.00 vsoxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 44.00 vsoxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 76.00 vsoxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 28.00 vsoxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 44.00 vsoxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - - - - 28.00 vsoxseg8ei64.v v8, (a0), v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s
deleted file mode 100644
index 2671e0bb2f5d6..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s
+++ /dev/null
@@ -1,591 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf4, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf2, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m1, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m2, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m4, ta, ma
-vluxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m8, ta, ma
-vluxei8.v v8, (a0), v0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vluxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, mf2, ta, ma
-vluxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m1, ta, ma
-vluxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m2, ta, ma
-vluxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m4, ta, ma
-vluxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m8, ta, ma
-vluxei16.v v8, (a0), v0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vluxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m1, ta, ma
-vluxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m2, ta, ma
-vluxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m4, ta, ma
-vluxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m8, ta, ma
-vluxei32.v v8, (a0), v0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vluxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m2, ta, ma
-vluxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m4, ta, ma
-vluxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m8, ta, ma
-vluxei64.v v8, (a0), v0
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf4, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf2, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m1, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m2, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m4, ta, ma
-vloxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m8, ta, ma
-vloxei8.v v8, (a0), v0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vloxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, mf2, ta, ma
-vloxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m1, ta, ma
-vloxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m2, ta, ma
-vloxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m4, ta, ma
-vloxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m8, ta, ma
-vloxei16.v v8, (a0), v0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vloxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m1, ta, ma
-vloxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m2, ta, ma
-vloxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m4, ta, ma
-vloxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m8, ta, ma
-vloxei32.v v8, (a0), v0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vloxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m2, ta, ma
-vloxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m4, ta, ma
-vloxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m8, ta, ma
-vloxei64.v v8, (a0), v0
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf4, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf2, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m1, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m2, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m4, ta, ma
-vsuxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m8, ta, ma
-vsuxei8.v v8, (a0), v0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vsuxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, mf2, ta, ma
-vsuxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m1, ta, ma
-vsuxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m2, ta, ma
-vsuxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m4, ta, ma
-vsuxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m8, ta, ma
-vsuxei16.v v8, (a0), v0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vsuxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m1, ta, ma
-vsuxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m2, ta, ma
-vsuxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m4, ta, ma
-vsuxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m8, ta, ma
-vsuxei32.v v8, (a0), v0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vsuxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m2, ta, ma
-vsuxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m4, ta, ma
-vsuxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m8, ta, ma
-vsuxei64.v v8, (a0), v0
-
-vsetvli zero, zero, e8, mf8, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf4, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, mf2, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m1, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m2, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m4, ta, ma
-vsoxei8.v v8, (a0), v0
-vsetvli zero, zero, e8, m8, ta, ma
-vsoxei8.v v8, (a0), v0
-
-vsetvli zero, zero, e16, mf4, ta, ma
-vsoxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, mf2, ta, ma
-vsoxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m1, ta, ma
-vsoxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m2, ta, ma
-vsoxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m4, ta, ma
-vsoxei16.v v8, (a0), v0
-vsetvli zero, zero, e16, m8, ta, ma
-vsoxei16.v v8, (a0), v0
-
-vsetvli zero, zero, e32, mf2, ta, ma
-vsoxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m1, ta, ma
-vsoxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m2, ta, ma
-vsoxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m4, ta, ma
-vsoxei32.v v8, (a0), v0
-vsetvli zero, zero, e32, m8, ta, ma
-vsoxei32.v v8, (a0), v0
-
-vsetvli zero, zero, e64, m1, ta, ma
-vsoxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m2, ta, ma
-vsoxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m4, ta, ma
-vsoxei64.v v8, (a0), v0
-vsetvli zero, zero, e64, m8, ta, ma
-vsoxei64.v v8, (a0), v0
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 176
-# CHECK-NEXT: Total Cycles: 1898
-# CHECK-NEXT: Total uOps: 176
-
-# CHECK: Dispatch Width: 4
-# CHECK-NEXT: uOps Per Cycle: 0.09
-# CHECK-NEXT: IPC: 0.09
-# CHECK-NEXT: Block RThroughput: 944.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 126 128.00 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vluxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vluxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vluxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vluxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vluxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vluxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vluxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vluxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vluxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 126 128.00 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vloxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vloxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vloxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vloxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vloxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vloxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vloxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vloxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vloxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 126 128.00 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsuxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsuxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsuxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsuxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 126 128.00 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 62 64.00 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 30 32.00 * vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 13 2.00 * vsoxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 18 4.00 * vsoxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 22 8.00 * vsoxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 30 16.00 * vsoxei64.v v8, (a0), v0
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP600Div
-# CHECK-NEXT: [1] - SiFiveP600FEXQ0
-# CHECK-NEXT: [2] - SiFiveP600FEXQ1
-# CHECK-NEXT: [3] - SiFiveP600FloatDiv
-# CHECK-NEXT: [4] - SiFiveP600IEXQ0
-# CHECK-NEXT: [5] - SiFiveP600IEXQ1
-# CHECK-NEXT: [6] - SiFiveP600IEXQ2
-# CHECK-NEXT: [7] - SiFiveP600IEXQ3
-# CHECK-NEXT: [8.0] - SiFiveP600LDST
-# CHECK-NEXT: [8.1] - SiFiveP600LDST
-# CHECK-NEXT: [9] - SiFiveP600VDiv
-# CHECK-NEXT: [10] - SiFiveP600VEXQ0
-# CHECK-NEXT: [11] - SiFiveP600VEXQ1
-# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
-# CHECK-NEXT: [13] - SiFiveP600VLD
-# CHECK-NEXT: [14] - SiFiveP600VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
-# CHECK-NEXT: - - - - 88.00 - - - - - - - - - 944.00 944.00
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vluxei8.v v8, (a0), v0
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-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
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-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
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-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
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-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
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-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
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-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
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-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsoxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsoxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsoxei64.v v8, (a0), v0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsoxei64.v v8, (a0), v0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vmv.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vmv.s
deleted file mode 100644
index 99b72b1fabbae..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vmv.s
+++ /dev/null
@@ -1,816 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
-
-vsetvli zero, zero, e8, mf8, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e8, m2, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e8, m4, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e8, m8, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e16, mf8, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e16, m2, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e16, m4, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e16, m8, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e32, mf8, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e32, mf4, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e32, m2, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e32, m4, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e32, m8, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e64, mf8, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e64, mf4, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e64, mf2, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e64, m2, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e64, m4, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e64, m8, tu, mu
-vmv1r.v v8, v16
-vsetvli zero, zero, e8, mf8, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e8, m2, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e8, m4, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e8, m8, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e16, mf8, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e16, m2, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e16, m4, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e16, m8, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e32, mf8, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e32, mf4, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e32, m2, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e32, m4, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e32, m8, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e64, mf8, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e64, mf4, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e64, mf2, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e64, m2, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e64, m4, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e64, m8, tu, mu
-vmv2r.v v8, v16
-vsetvli zero, zero, e8, mf8, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e8, m2, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e8, m4, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e8, m8, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e16, mf8, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e16, m2, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e16, m4, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e16, m8, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e32, mf8, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e32, mf4, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e32, m2, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e32, m4, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e32, m8, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e64, mf8, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e64, mf4, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e64, mf2, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e64, m2, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e64, m4, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e64, m8, tu, mu
-vmv4r.v v8, v16
-vsetvli zero, zero, e8, mf8, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e8, mf4, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e8, mf2, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e8, m1, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e8, m2, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e8, m4, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e8, m8, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e16, mf8, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e16, mf4, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e16, mf2, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e16, m1, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e16, m2, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e16, m4, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e16, m8, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e32, mf8, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e32, mf4, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e32, mf2, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e32, m1, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e32, m2, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e32, m4, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e32, m8, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e64, mf8, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e64, mf4, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e64, mf2, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e64, m1, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e64, m2, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e64, m4, tu, mu
-vmv8r.v v8, v16
-vsetvli zero, zero, e64, m8, tu, mu
-vmv8r.v v8, v16
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 256
-# CHECK-NEXT: Total Cycles: 255
-# CHECK-NEXT: Total uOps: 256
-
-# CHECK: Dispatch Width: 4
-# CHECK-NEXT: uOps Per Cycle: 1.00
-# CHECK-NEXT: IPC: 1.00
-# CHECK-NEXT: Block RThroughput: 240.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 2 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 2 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 2 4.00 vmv8r.v v8, v16
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP600Div
-# CHECK-NEXT: [1] - SiFiveP600FEXQ0
-# CHECK-NEXT: [2] - SiFiveP600FEXQ1
-# CHECK-NEXT: [3] - SiFiveP600FloatDiv
-# CHECK-NEXT: [4] - SiFiveP600IEXQ0
-# CHECK-NEXT: [5] - SiFiveP600IEXQ1
-# CHECK-NEXT: [6] - SiFiveP600IEXQ2
-# CHECK-NEXT: [7] - SiFiveP600IEXQ3
-# CHECK-NEXT: [8.0] - SiFiveP600LDST
-# CHECK-NEXT: [8.1] - SiFiveP600LDST
-# CHECK-NEXT: [9] - SiFiveP600VDiv
-# CHECK-NEXT: [10] - SiFiveP600VEXQ0
-# CHECK-NEXT: [11] - SiFiveP600VEXQ1
-# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
-# CHECK-NEXT: [13] - SiFiveP600VLD
-# CHECK-NEXT: [14] - SiFiveP600VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
-# CHECK-NEXT: - - - - 128.00 - - - - - - 240.00 240.00 - - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vmv8r.v v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zba.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zba.test
new file mode 100644
index 0000000000000..cf2a96fb0b396
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zba.test
@@ -0,0 +1,77 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../Inputs/zba.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith ADD_UW add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SLLI_UW slli.uw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SH1ADD_UW sh1add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SH2ADD_UW sh2add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SH3ADD_UW sh3add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SH1ADD sh1add a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SH2ADD sh2add a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SH3ADD sh3add a0, a0, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 2.00 2.00 2.00 2.00 - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - add.uw a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - slli.uw a0, a0, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sh1add.uw a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sh2add.uw a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sh3add.uw a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sh1add a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sh2add a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sh3add a0, a0, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zbb.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zbb.test
new file mode 100644
index 0000000000000..4ba314dd4f160
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zbb.test
@@ -0,0 +1,109 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../Inputs/zbb.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith ANDN andn a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith ORN orn a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith XNOR xnor a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith CLZ clz a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith CLZW clzw a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith CTZ ctz a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith CTZW ctzw a0, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith CPOP cpop a0, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith CPOPW cpopw a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith MIN min a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith MINU minu a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith MAX max a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith MAXU maxu a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SEXT_B sext.b a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SEXT_H sext.h a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith ZEXT_H_RV64 zext.h a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith ROL rol a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith ROLW rolw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith ROR ror a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith RORW rorw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith RORI rori a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith RORIW roriw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith ORC_B orc.b a0, a0
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith REV8_RV64 rev8 a0, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 5.50 7.50 5.50 5.50 - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - andn a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - orn a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - xnor a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - clz a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - clzw a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - ctz a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - ctzw a0, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - cpop a0, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - cpopw a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - min a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - minu a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - max a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - maxu a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sext.b a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sext.h a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - zext.h a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - rol a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - rolw a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - ror a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - rorw a0, a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - rori a0, a0, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - roriw a0, a0, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - orc.b a0, a0
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - rev8 a0, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zbs.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zbs.test
new file mode 100644
index 0000000000000..5a40d22ba490b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zbs.test
@@ -0,0 +1,77 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../Inputs/zbs.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith BCLR bclr a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith BCLRI bclri a0, a1, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith BEXT bext a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith BEXTI bexti a0, a1, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith BINV binv a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith BINVI binvi a0, a1, 1
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith BSET bset a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith BSETI bseti a0, a1, 1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 2.00 2.00 2.00 2.00 - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - bclr a0, a1, a2
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - bclri a0, a1, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - bext a0, a1, a2
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - bexti a0, a1, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - binv a0, a1, a2
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - binvi a0, a1, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - bset a0, a1, a2
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - bseti a0, a1, 1
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zfhmin.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zfhmin.test
new file mode 100644
index 0000000000000..2a976be5ef0c2
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zfhmin.test
@@ -0,0 +1,81 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../Inputs/zfhmin.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [1] - SiFiveP600Div:1
+# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
+# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
+# CHECK-NEXT: [11] - SiFiveP600LDST:2
+# CHECK-NEXT: [12] - SiFiveP600VDiv:1
+# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
+# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
+# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
+# CHECK-NEXT: [16] - SiFiveP600VLD:1
+# CHECK-NEXT: [17] - SiFiveP600VST:1
+# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 5 0.50 * 5 SiFiveP600LDST FLH flh ft0, 0(a0)
+# CHECK-NEXT: 1 1 0.50 * 1 SiFiveP600LDST FSH fsh ft0, 0(a0)
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FMV_X_H fmv.x.h a2, fs7
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith FMV_H_X fmv.h.x ft1, a6
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FCVT_S_H fcvt.s.h fa0, ft0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FCVT_S_H fcvt.s.h fa0, ft0, rup
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FCVT_H_S fcvt.h.s ft2, fa2
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FCVT_D_H fcvt.d.h fa0, ft0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FCVT_D_H fcvt.d.h fa0, ft0, rup
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FCVT_H_D fcvt.h.d ft2, fa2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - 4.00 3.00 - - 1.00 - - 1.00 1.00 - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - flh ft0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - fsh ft0, 0(a0)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - fmv.x.h a2, fs7
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fmv.h.x ft1, a6
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fcvt.s.h fa0, ft0
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fcvt.s.h fa0, ft0, rup
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fcvt.h.s ft2, fa2
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fcvt.d.h fa0, ft0
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fcvt.d.h fa0, ft0, rup
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fcvt.h.d ft2, fa2
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
deleted file mode 100644
index d8f926d8a6793..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
+++ /dev/null
@@ -1,113 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
-
-# These instructions only work with e64
-
-vsetvli zero, zero, e64, m1, tu, mu
-vclmul.vv v4, v8, v12
-vclmul.vx v4, v8, a0
-vclmulh.vv v4, v8, v12
-vclmulh.vx v4, v8, a0
-
-vsetvli zero, zero, e64, m2, tu, mu
-vclmul.vv v4, v8, v12
-vclmul.vx v4, v8, a0
-vclmulh.vv v4, v8, v12
-vclmulh.vx v4, v8, a0
-
-vsetvli zero, zero, e64, m4, tu, mu
-vclmul.vv v4, v8, v12
-vclmul.vx v4, v8, a0
-vclmulh.vv v4, v8, v12
-vclmulh.vx v4, v8, a0
-
-vsetvli zero, zero, e64, m8, tu, mu
-vclmul.vv v8, v12, v24
-vclmul.vx v8, v12, a0
-vclmulh.vv v8, v12, v24
-vclmulh.vx v8, v12, a0
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 20
-# CHECK-NEXT: Total Cycles: 64
-# CHECK-NEXT: Total uOps: 20
-
-# CHECK: Dispatch Width: 4
-# CHECK-NEXT: uOps Per Cycle: 0.31
-# CHECK-NEXT: IPC: 0.31
-# CHECK-NEXT: Block RThroughput: 60.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vclmul.vv v4, v8, v12
-# CHECK-NEXT: 1 2 1.00 vclmul.vx v4, v8, a0
-# CHECK-NEXT: 1 2 1.00 vclmulh.vv v4, v8, v12
-# CHECK-NEXT: 1 2 1.00 vclmulh.vx v4, v8, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 2.00 vclmul.vv v4, v8, v12
-# CHECK-NEXT: 1 2 2.00 vclmul.vx v4, v8, a0
-# CHECK-NEXT: 1 2 2.00 vclmulh.vv v4, v8, v12
-# CHECK-NEXT: 1 2 2.00 vclmulh.vx v4, v8, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 4 4.00 vclmul.vv v4, v8, v12
-# CHECK-NEXT: 1 4 4.00 vclmul.vx v4, v8, a0
-# CHECK-NEXT: 1 4 4.00 vclmulh.vv v4, v8, v12
-# CHECK-NEXT: 1 4 4.00 vclmulh.vx v4, v8, a0
-# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 8 8.00 vclmul.vv v8, v12, v24
-# CHECK-NEXT: 1 8 8.00 vclmul.vx v8, v12, a0
-# CHECK-NEXT: 1 8 8.00 vclmulh.vv v8, v12, v24
-# CHECK-NEXT: 1 8 8.00 vclmulh.vx v8, v12, a0
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP600Div
-# CHECK-NEXT: [1] - SiFiveP600FEXQ0
-# CHECK-NEXT: [2] - SiFiveP600FEXQ1
-# CHECK-NEXT: [3] - SiFiveP600FloatDiv
-# CHECK-NEXT: [4] - SiFiveP600IEXQ0
-# CHECK-NEXT: [5] - SiFiveP600IEXQ1
-# CHECK-NEXT: [6] - SiFiveP600IEXQ2
-# CHECK-NEXT: [7] - SiFiveP600IEXQ3
-# CHECK-NEXT: [8.0] - SiFiveP600LDST
-# CHECK-NEXT: [8.1] - SiFiveP600LDST
-# CHECK-NEXT: [9] - SiFiveP600VDiv
-# CHECK-NEXT: [10] - SiFiveP600VEXQ0
-# CHECK-NEXT: [11] - SiFiveP600VEXQ1
-# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
-# CHECK-NEXT: [13] - SiFiveP600VLD
-# CHECK-NEXT: [14] - SiFiveP600VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
-# CHECK-NEXT: - - - - 4.00 - - - - - - 60.00 - - - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmul.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmul.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmulh.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmulh.vx v4, v8, a0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmul.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmul.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmulh.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmulh.vx v4, v8, a0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmul.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmul.vx v4, v8, a0
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmulh.vv v4, v8, v12
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmulh.vx v4, v8, a0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmul.vv v8, v12, v24
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmul.vx v8, v12, a0
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmulh.vv v8, v12, v24
-# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmulh.vx v8, v12, a0
>From 4434504b433ba54d14102b663819149b99f77816 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Wed, 1 Apr 2026 09:58:59 -0700
Subject: [PATCH 2/2] fixup! Remove 32-bit-only test
---
.../RISCV/SiFiveP600/mul-div-rv32.test | 77 -------------------
1 file changed, 77 deletions(-)
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-div-rv32.test
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-div-rv32.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-div-rv32.test
deleted file mode 100644
index d27014a92c818..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-div-rv32.test
+++ /dev/null
@@ -1,77 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../Inputs/mul-div-rv32.s | FileCheck %s
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
-# CHECK-NEXT: [1] - SiFiveP600Div:1
-# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
-# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
-# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
-# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
-# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
-# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
-# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
-# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
-# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
-# CHECK-NEXT: [11] - SiFiveP600LDST:2
-# CHECK-NEXT: [12] - SiFiveP600VDiv:1
-# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
-# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
-# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
-# CHECK-NEXT: [16] - SiFiveP600VLD:1
-# CHECK-NEXT: [17] - SiFiveP600VST:1
-# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-# CHECK-NEXT: [7]: Bypass Latency
-# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
-# CHECK-NEXT: [9]: LLVM Opcode Name
-
-# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
-# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith MUL mul a0, a0, a0
-# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith MULH mulh a0, a0, a0
-# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith MULHU mulhu a0, a0, a0
-# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith MULHSU mulhsu a0, a0, a0
-# CHECK-NEXT: 1 35 34.00 35 SiFiveP600Div[34],SiFiveP600IEXQ1,SiFiveP600IntArith DIV div a0, a1, a2
-# CHECK-NEXT: 1 35 34.00 35 SiFiveP600Div[34],SiFiveP600IEXQ1,SiFiveP600IntArith DIVU divu a0, a1, a2
-# CHECK-NEXT: 1 35 34.00 35 SiFiveP600Div[34],SiFiveP600IEXQ1,SiFiveP600IntArith REM rem a0, a1, a2
-# CHECK-NEXT: 1 35 34.00 35 SiFiveP600Div[34],SiFiveP600IEXQ1,SiFiveP600IntArith REMU remu a0, a1, a2
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - SiFiveP600Div
-# CHECK-NEXT: [1] - SiFiveP600FEXQ0
-# CHECK-NEXT: [2] - SiFiveP600FEXQ1
-# CHECK-NEXT: [3] - SiFiveP600FloatDiv
-# CHECK-NEXT: [4] - SiFiveP600IEXQ0
-# CHECK-NEXT: [5] - SiFiveP600IEXQ1
-# CHECK-NEXT: [6] - SiFiveP600IEXQ2
-# CHECK-NEXT: [7] - SiFiveP600IEXQ3
-# CHECK-NEXT: [8.0] - SiFiveP600LDST
-# CHECK-NEXT: [8.1] - SiFiveP600LDST
-# CHECK-NEXT: [9] - SiFiveP600VDiv
-# CHECK-NEXT: [10] - SiFiveP600VEXQ0
-# CHECK-NEXT: [11] - SiFiveP600VEXQ1
-# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
-# CHECK-NEXT: [13] - SiFiveP600VLD
-# CHECK-NEXT: [14] - SiFiveP600VST
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
-# CHECK-NEXT: 136.00 - - - - 8.00 - - - - - - - - - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
-# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - mul a0, a0, a0
-# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - mulh a0, a0, a0
-# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - mulhu a0, a0, a0
-# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - mulhsu a0, a0, a0
-# CHECK-NEXT: 34.00 - - - - 1.00 - - - - - - - - - - div a0, a1, a2
-# CHECK-NEXT: 34.00 - - - - 1.00 - - - - - - - - - - divu a0, a1, a2
-# CHECK-NEXT: 34.00 - - - - 1.00 - - - - - - - - - - rem a0, a1, a2
-# CHECK-NEXT: 34.00 - - - - 1.00 - - - - - - - - - - remu a0, a1, a2
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