[llvm] 16255e4 - [RISCV] Add RISCVISD::USATI/SATI to computeKnownBitsForTargetNode/ComputeNumSignBitsForTargetNode. (#189702)

[via llvm-commits]

Author: Craig Topper
Date: 2026-04-01T09:02:19-07:00
New Revision: 16255e457c9d5d418bd67543c97204448e195597

URL: https://github.com/llvm/llvm-project/commit/16255e457c9d5d418bd67543c97204448e195597
DIFF: https://github.com/llvm/llvm-project/commit/16255e457c9d5d418bd67543c97204448e195597.diff

LOG: [RISCV] Add RISCVISD::USATI/SATI to computeKnownBitsForTargetNode/ComputeNumSignBitsForTargetNode. (#189702)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/rv32p.ll
    llvm/test/CodeGen/RISCV/rv64p.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index aa93acde602d2..88bf173dfbca3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -23259,6 +23259,11 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
     Known.One = computeGREVOrGORC(Known.One.getZExtValue(), 7, IsGORC);
     break;
   }
+  case RISCVISD::USATI: {
+    unsigned Width = Op.getConstantOperandVal(1);
+    Known.Zero.setBitsFrom(Width);
+    break;
+  }
   case RISCVISD::READ_VLENB: {
     // We can use the minimum and maximum VLEN values to bound VLENB.  We
     // know VLEN must be a power of two.
@@ -23360,6 +23365,10 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
   case RISCVISD::STRICT_FCVT_WU_RV64:
     // TODO: As the result is sign-extended, this is conservatively correct.
     return 33;
+  case RISCVISD::SATI: {
+    unsigned Width = Op.getConstantOperandVal(1);
+    return Op.getScalarValueSizeInBits() - Width;
+  }
   case RISCVISD::VMV_X_S: {
     // The number of sign bits of the scalar result is computed by obtaining the
     // element type of the input vector operand, subtracting its width from the

diff  --git a/llvm/test/CodeGen/RISCV/rv32p.ll b/llvm/test/CodeGen/RISCV/rv32p.ll
index 4992161e88c0c..d2bf1c581e900 100644
--- a/llvm/test/CodeGen/RISCV/rv32p.ll
+++ b/llvm/test/CodeGen/RISCV/rv32p.ll
@@ -1536,3 +1536,18 @@ entry:
   %1 = call i32 @llvm.smin.i32(i32 %0, i32 255)
   ret i32 %1
 }
+
+; Test that we select pack.
+define i32 @mm_usati_32_knownbits_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: mm_usati_32_knownbits_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    usati a0, a0, 16
+; CHECK-NEXT:    pack a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = call i32 @llvm.smax.i32(i32 %x, i32 0)
+  %1 = call i32 @llvm.smin.i32(i32 %0, i32 65535)
+  %2 = shl i32 %y, 16
+  %3 = or i32 %1, %2
+  ret i32 %3
+}

diff  --git a/llvm/test/CodeGen/RISCV/rv64p.ll b/llvm/test/CodeGen/RISCV/rv64p.ll
index c682e4711aaf1..1d626611b736a 100644
--- a/llvm/test/CodeGen/RISCV/rv64p.ll
+++ b/llvm/test/CodeGen/RISCV/rv64p.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+zbb -verify-machineinstrs \
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+zbb,+m -verify-machineinstrs \
 ; RUN:   < %s | FileCheck %s
 
 define i32 @abs_i32(i32 %x) {
@@ -1000,3 +1000,34 @@ entry:
   %1 = call i64 @llvm.smin.i64(i64 %0, i64 -1)
   ret i64 %1
 }
+
+; Test that we select remw.
+define signext i32 @mm_sati_32_numsignbits_i64(i64 %x, i32 %y) {
+; CHECK-LABEL: mm_sati_32_numsignbits_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sati a0, a0, 32
+; CHECK-NEXT:    remw a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = call i64 @llvm.smax.i64(i64 %x, i64 -2147483648)
+  %1 = call i64 @llvm.smin.i64(i64 %0, i64 2147483647)
+  %2 = sext i32 %y to i64
+  %3 = srem i64 %1, %2
+  %4 = trunc i64 %3 to i32
+  ret i32 %4
+}
+
+; Test that we select pack.
+define i64 @mm_usati_32_knownbits_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: mm_usati_32_knownbits_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    usati a0, a0, 32
+; CHECK-NEXT:    pack a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %0 = call i64 @llvm.smax.i64(i64 %x, i64 0)
+  %1 = call i64 @llvm.smin.i64(i64 %0, i64 4294967295)
+  %2 = shl i64 %y, 32
+  %3 = or i64 %1, %2
+  ret i64 %3
+}