[llvm] calling conv (PR #187135)

[Guo Chen via llvm-commits]

https://github.com/broxigarchen updated https://github.com/llvm/llvm-project/pull/187135

>From 1c30c51f238e156bbe3bc94690c9bb14e36c84db Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Wed, 1 Apr 2026 11:20:27 -0400
Subject: [PATCH] calling conv update

---
 llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td | 25 +++++++++++++++++++--
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp   |  5 ++++-
 2 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
index 2932bbf0e7bbd..3981fbe28444a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
@@ -18,6 +18,10 @@ class CCIfOrigTypeShaderCCIsSGPR<CCAction A>
   : CCIf<[{(!OrigTy->getScalarType()->isFloatTy() &&
             !OrigTy->getScalarType()->isHalfTy()) }], A>;
 
+class CCIfTrue16<CCAction A> :
+  CCIf<"State.getMachineFunction().getSubtarget<GCNSubtarget>().useRealTrue16Insts()", A>;
+class CCIfNotTrue16<CCAction A> :
+  CCIf<"!State.getMachineFunction().getSubtarget<GCNSubtarget>().useRealTrue16Insts()", A>;
 
 // Calling convention for SI
 def CC_SI_Gfx : CallingConv<[
@@ -143,9 +147,18 @@ def CC_AMDGPU_Func : CallingConv<[
     !foreach(i, !range(0, 30), !cast<Register>("SGPR"#i))  // SGPR0-29
   >>>,
 
-  CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1, bf16, v2bf16], CCAssignToReg<
+  CCIfType<[i32, f32, v2i16, v2f16, i1, v2bf16], CCAssignToReg<
     !foreach(i, !range(0, 32), !cast<Register>("VGPR"#i))  // VGPR0-31
   >>,
+
+  CCIfTrue16<CCIfType<[i16, f16, bf16], CCAssignToReg<
+       !foreach(i, !range(0, 32), !cast<Register>("VGPR"#i#"_LO16"))  // VGPR0-31_LO16
+  >>>,
+
+  CCIfNotTrue16<CCIfType<[i16, f16, bf16], CCAssignToReg<
+       !foreach(i, !range(0, 32), !cast<Register>("VGPR"#i))  // VGPR0-31
+  >>>,
+
   CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>>
 ]>;
 
@@ -153,9 +166,17 @@ def CC_AMDGPU_Func : CallingConv<[
 def RetCC_AMDGPU_Func : CallingConv<[
   CCIfType<[i1], CCPromoteToType<i32>>,
   CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
-  CCIfType<[i32, f32, i16, f16, v2i16, v2f16, bf16, v2bf16], CCAssignToReg<
+  CCIfType<[i32, f32, v2i16, v2f16, v2bf16], CCAssignToReg<
     !foreach(i, !range(0, 32), !cast<Register>("VGPR"#i))  // VGPR0-31
   >>,
+
+  CCIfTrue16<CCIfType<[i16, f16, bf16], CCAssignToReg<
+       !foreach(i, !range(0, 32), !cast<Register>("VGPR"#i#"_LO16"))  // VGPR0-31_LO16
+  >>>,
+
+  CCIfNotTrue16<CCIfType<[i16, f16, bf16], CCAssignToReg<
+       !foreach(i, !range(0, 32), !cast<Register>("VGPR"#i))  // VGPR0-31
+  >>>,
 ]>;
 
 def CC_AMDGPU : CallingConv<[
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 544aca0458975..ac3aa20ac5d7a 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -3639,12 +3639,15 @@ SDValue SITargetLowering::LowerFormalArguments(
       RC = &AMDGPU::VGPR_32RegClass;
     else if (AMDGPU::SGPR_32RegClass.contains(Reg))
       RC = &AMDGPU::SGPR_32RegClass;
+    else if (AMDGPU::VGPR_16RegClass.contains(Reg))
+      RC = &AMDGPU::VGPR_16RegClass;
     else
       llvm_unreachable("Unexpected register class in LowerFormalArguments!");
 
     Reg = MF.addLiveIn(Reg, RC);
     SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
-    if (Arg.Flags.isInReg() && RC == &AMDGPU::VGPR_32RegClass) {
+    if (Arg.Flags.isInReg() &&
+        (RC == &AMDGPU::VGPR_32RegClass || RC == &AMDGPU::VGPR_16RegClass)) {
       // FIXME: Need to forward the chains created by `CopyFromReg`s, make sure
       // they will read physical regs before any side effect instructions.
       SDValue ReadFirstLane =