[llvm] [SPIR-V] Emit builtin variable OpVariable into entry block (PR #189958)

[Arseniy Obolenskiy via llvm-commits]

https://github.com/aobolensk updated https://github.com/llvm/llvm-project/pull/189958

>From 51ebeca2ea6ba10a0ba16eebcb8e4f2533a51586 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Wed, 1 Apr 2026 15:25:39 +0200
Subject: [PATCH 1/2] [SPIR-V] Emit builtin variable OpVariable into entry
 block

Move the OpVariable and decoration emission for builtin variables into the first MBB so that VReg definition dependencies remain valid across all BBs
---
 llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp                | 10 ++++++++--
 .../test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy.ll |  6 ++----
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index db5218ec73bb7..4c5c37e6d7ddc 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -518,11 +518,17 @@ static Register buildBuiltinVariableLoad(
       VariableType, MIRBuilder, SPIRV::StorageClass::Input);
   GR->assignSPIRVTypeToVReg(PtrType, NewRegister, MIRBuilder.getMF());
 
-  // Set up the global OpVariable with the necessary builtin decorations.
+  // Emit the OpVariable and its decorations into the first MBB to ensure
+  // VReg definition dependencies are valid across all MBBs.
+  MachineBasicBlock &EntryBB = MIRBuilder.getMF().front();
+  MachineIRBuilder FirstBlockBuilder;
+  FirstBlockBuilder.setMF(MIRBuilder.getMF());
+  FirstBlockBuilder.setMBB(EntryBB);
+
   Register Variable = GR->buildGlobalVariable(
       NewRegister, PtrType, getLinkStringForBuiltIn(BuiltinValue), nullptr,
       SPIRV::StorageClass::Input, nullptr, /* isConst= */ isConst, LinkageTy,
-      MIRBuilder, false);
+      FirstBlockBuilder, false);
 
   // Load the value from the global variable.
   Register LoadedRegister =
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy.ll
index 3e68161105cc1..0c5b03895f579 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy.ll
@@ -1,7 +1,5 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
-
-; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled
-; XFAIL: expensive_checks
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: %if spirv-tools %{ llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
 ; CHECK-SPIRV-DAG: %[[#]] = OpGroupAsyncCopy %[[#]] %[[#Scope:]]
 ; CHECK-SPIRV-DAG: %[[#Scope]] = OpConstant %[[#]]

>From fc61b8d39ff5171b38be2b57013afa05a247e22f Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Wed, 1 Apr 2026 16:53:56 +0200
Subject: [PATCH 2/2] add spir-val todo

---
 llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy.ll | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy.ll
index 0c5b03895f579..facab89b1ad1e 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy.ll
@@ -1,5 +1,6 @@
 ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
-; RUN: %if spirv-tools %{ llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+; TODO: enable spirv-val: OpGroupAsyncCopy event arg needs OpTypeEvent, not OpTypePointer
+; RUNx: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
 ; CHECK-SPIRV-DAG: %[[#]] = OpGroupAsyncCopy %[[#]] %[[#Scope:]]
 ; CHECK-SPIRV-DAG: %[[#Scope]] = OpConstant %[[#]]