[llvm] [AMDGPU] Add v2i32 and/or patterns for VOP3 AND_OR and OR3 operations (PR #188375)

[Matt Arsenault via llvm-commits]

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@@ -142,3 +142,256 @@ define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) {
   %bc = bitcast i32 %result to float
   ret float %bc
 }
+
+define <2 x i32> @and_or_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+; VI-LABEL: and_or_v2i32:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_and_b32_e32 v0, v0, v2
+; VI-DAG:    v_and_b32_e32 v1, v1, v3
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, v0, v4
+; VI-DAG:    v_or_b32_e32 v1, v1, v5
+;
+; GFX9-LABEL: and_or_v2i32:
+; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:     v_and_or_b32 v0, v0, v2, v4
+; GFX9-DAG:     v_and_or_b32 v1, v1, v3, v5
+;
+; GFX10-LABEL: and_or_v2i32:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_and_or_b32 v0, v0, v2, v4
+; GFX10-DAG:     v_and_or_b32 v1, v1, v3, v5
+  %x = and <2 x i32> %a, %b
+  %result = or <2 x i32> %x, %c
+  ret <2 x i32> %result
+}
+
+; ThreeOp instruction variant not used due to Constant Bus Limitations
+define <2 x i32> @and_or_v2i32_b(<2 x i32> inreg %a, <2 x i32> %b, <2 x i32> inreg %c) {
+; VI-LABEL: and_or_v2i32_b:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_and_b32_e32 v0, s16, v0
+; VI-DAG:    v_and_b32_e32 v1, s17, v1
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, s18, v0
+; VI-DAG:    v_or_b32_e32 v1, s19, v1
+;
+; GFX9-LABEL: and_or_v2i32_b:
+; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:    v_and_b32_e32 v0, s16, v0
+; GFX9-DAG:    v_and_b32_e32 v1, s17, v1
+; GFX9-CHECK-NOT: {{.}}
+; GFX9-DAG:    v_or_b32_e32 v0, s18, v0
+; GFX9-DAG:    v_or_b32_e32 v1, s19, v1
+;
+; GFX10-LABEL: and_or_v2i32_b:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_and_or_b32 v0, s{{[0-9]+}}, v0, s{{[0-9]+}}
+; GFX10-DAG:     v_and_or_b32 v1, s{{[0-9]+}}, v1, s{{[0-9]+}}
+  %x = and <2 x i32> %a, %b
+  %result = or <2 x i32> %x, %c
+  ret <2 x i32> %result
+}
+
+define <2 x i32> @and_or_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) {
+; VI-LABEL: and_or_v2i32_ab:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_and_b32_e32 v0, v0, v2
+; VI-DAG:    v_and_b32_e32 v1, v1, v3
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, s16, v0
+; VI-DAG:    v_or_b32_e32 v1, s17, v1
+;
+; GFX9-LABEL: and_or_v2i32_ab:
+; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:     v_and_or_b32 v0, v0, v2, s16
+; GFX9-DAG:     v_and_or_b32 v1, v1, v3, s17
+;
+; GFX10-LABEL: and_or_v2i32_ab:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_and_or_b32 v0, v0, v2, s{{[0-9]+}}
+; GFX10-DAG:     v_and_or_b32 v1, v1, v3, s{{[0-9]+}}
+  %x = and <2 x i32> %a, %b
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arsenm wrote:

These aren't generated checks? 

https://github.com/llvm/llvm-project/pull/188375