[llvm] 86c3abe - [NFC] Rename InstructionUniformity to ValueUniformity (#189935)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 1 06:58:38 PDT 2026
Author: Pankaj Dwivedi
Date: 2026-04-01T19:28:33+05:30
New Revision: 86c3abe85e7d323c8b7fbe4b83442ca3794512c9
URL: https://github.com/llvm/llvm-project/commit/86c3abe85e7d323c8b7fbe4b83442ca3794512c9
DIFF: https://github.com/llvm/llvm-project/commit/86c3abe85e7d323c8b7fbe4b83442ca3794512c9.diff
LOG: [NFC] Rename InstructionUniformity to ValueUniformity (#189935)
Added:
Modified:
llvm/include/llvm/ADT/Uniformity.h
llvm/include/llvm/Analysis/TargetTransformInfo.h
llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
llvm/include/llvm/CodeGen/TargetInstrInfo.h
llvm/lib/Analysis/TargetTransformInfo.cpp
llvm/lib/Analysis/UniformityAnalysis.cpp
llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
Removed:
################################################################################
diff --git a/llvm/include/llvm/ADT/Uniformity.h b/llvm/include/llvm/ADT/Uniformity.h
index 0adbdf99c6d2a..f52ca5e6d3ac0 100644
--- a/llvm/include/llvm/ADT/Uniformity.h
+++ b/llvm/include/llvm/ADT/Uniformity.h
@@ -11,21 +11,21 @@
namespace llvm {
-/// Enum describing how instructions behave with respect to uniformity and
+/// Enum describing how values behave with respect to uniformity and
/// divergence, to answer the question: if the same instruction is executed by
-/// two threads in a convergent set of threads, will its result value(s) be
+/// two threads in a convergent set of threads, will its result value be
/// uniform, i.e. the same on both threads?
-enum class InstructionUniformity {
- /// The result values are uniform if and only if all operands are uniform.
+enum class ValueUniformity {
+ /// The result value is uniform if and only if all operands are uniform.
Default,
- /// The result values are always uniform.
+ /// The result value is always uniform.
AlwaysUniform,
- /// The result values can never be assumed to be uniform.
+ /// The result value can never be assumed to be uniform.
NeverUniform,
- /// The result values require a custom uniformity check. A target-specific
+ /// The result value requires a custom uniformity check. A target-specific
/// callback determines whether the result is uniform based on which
/// operands are uniform.
Custom
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h
index 9059c1ee6f606..3c4f00c0d87b5 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -513,14 +513,14 @@ class TargetTransformInfo {
/// uniformity analysis and assume all values are uniform.
LLVM_ABI bool hasBranchDivergence(const Function *F = nullptr) const;
- /// Get target-specific uniformity information for an instruction.
+ /// Get target-specific uniformity information for a value.
/// This allows targets to provide more fine-grained control over
- /// uniformity analysis by specifying whether specific instructions
+ /// uniformity analysis by specifying whether specific values
/// should always or never be considered uniform, or require custom
/// operand-based analysis.
/// \param V The value to query for uniformity information.
- /// \return InstructionUniformity.
- LLVM_ABI InstructionUniformity getInstructionUniformity(const Value *V) const;
+ /// \return ValueUniformity.
+ LLVM_ABI ValueUniformity getValueUniformity(const Value *V) const;
/// Query the target whether the specified address space cast from FromAS to
/// ToAS is valid.
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
index f0439b065a8cd..7eb363c7b4404 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -132,8 +132,8 @@ class TargetTransformInfoImplBase {
return false;
}
- virtual InstructionUniformity getInstructionUniformity(const Value *V) const {
- return InstructionUniformity::Default;
+ virtual ValueUniformity getValueUniformity(const Value *V) const {
+ return ValueUniformity::Default;
}
virtual bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const {
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 77f710203d1fc..cd5561e57d033 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -2361,10 +2361,9 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
llvm_unreachable("impossible call instruction");
}
- /// Return the uniformity behavior of the given instruction.
- virtual InstructionUniformity
- getInstructionUniformity(const MachineInstr &MI) const {
- return InstructionUniformity::Default;
+ /// Return the uniformity behavior of the given value.
+ virtual ValueUniformity getValueUniformity(const MachineInstr &MI) const {
+ return ValueUniformity::Default;
}
/// Returns true if the given \p MI defines a TargetIndex operand that can be
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp
index 85a1e3f8fbbb9..5111593d76a6d 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -292,14 +292,14 @@ bool TargetTransformInfo::hasBranchDivergence(const Function *F) const {
return TTIImpl->hasBranchDivergence(F);
}
-InstructionUniformity
-llvm::TargetTransformInfo::getInstructionUniformity(const Value *V) const {
+ValueUniformity
+llvm::TargetTransformInfo::getValueUniformity(const Value *V) const {
// Calls with the NoDivergenceSource attribute are always uniform.
if (const auto *Call = dyn_cast<CallBase>(V)) {
if (Call->hasFnAttr(Attribute::NoDivergenceSource))
- return InstructionUniformity::AlwaysUniform;
+ return ValueUniformity::AlwaysUniform;
}
- return TTIImpl->getInstructionUniformity(V);
+ return TTIImpl->getValueUniformity(V);
}
bool llvm::TargetTransformInfo::isValidAddrSpaceCast(unsigned FromAS,
diff --git a/llvm/lib/Analysis/UniformityAnalysis.cpp b/llvm/lib/Analysis/UniformityAnalysis.cpp
index f40ea1a556f9f..55cba19ceec14 100644
--- a/llvm/lib/Analysis/UniformityAnalysis.cpp
+++ b/llvm/lib/Analysis/UniformityAnalysis.cpp
@@ -71,31 +71,30 @@ template <> void llvm::GenericUniformityAnalysisImpl<SSAContext>::initialize() {
// and will be reported as such by isDivergent() (not in UniformValues).
SmallVector<const Value *, 4> DivergentArgs;
for (auto &Arg : F.args()) {
- if (TTI->getInstructionUniformity(&Arg) ==
- InstructionUniformity::NeverUniform)
+ if (TTI->getValueUniformity(&Arg) == ValueUniformity::NeverUniform)
DivergentArgs.push_back(&Arg);
else
UniformValues.insert(&Arg);
}
for (auto &I : instructions(F)) {
- InstructionUniformity IU = TTI->getInstructionUniformity(&I);
+ ValueUniformity IU = TTI->getValueUniformity(&I);
switch (IU) {
- case InstructionUniformity::AlwaysUniform:
+ case ValueUniformity::AlwaysUniform:
UniformValues.insert(&I);
addUniformOverride(I);
continue;
- case InstructionUniformity::NeverUniform:
+ case ValueUniformity::NeverUniform:
// Skip inserting -- divergent by definition. Add to Worklist directly
// so compute() propagates divergence to users.
if (I.isTerminator())
DivergentTermBlocks.insert(I.getParent());
Worklist.push_back(&I);
continue;
- case InstructionUniformity::Custom:
+ case ValueUniformity::Custom:
UniformValues.insert(&I);
addCustomUniformityCandidate(&I);
continue;
- case InstructionUniformity::Default:
+ case ValueUniformity::Default:
UniformValues.insert(&I);
break;
}
diff --git a/llvm/lib/CodeGen/MachineUniformityAnalysis.cpp b/llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
index 416864d07f7d0..aa85b95a96d09 100644
--- a/llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
+++ b/llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
@@ -66,18 +66,18 @@ void llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::initialize() {
for (const MachineBasicBlock &block : F) {
for (const MachineInstr &instr : block) {
- auto uniformity = InstrInfo.getInstructionUniformity(instr);
+ auto uniformity = InstrInfo.getValueUniformity(instr);
switch (uniformity) {
- case InstructionUniformity::AlwaysUniform:
+ case ValueUniformity::AlwaysUniform:
addUniformOverride(instr);
break;
- case InstructionUniformity::NeverUniform:
+ case ValueUniformity::NeverUniform:
markDivergent(instr);
break;
- case InstructionUniformity::Custom:
+ case ValueUniformity::Custom:
break;
- case InstructionUniformity::Default:
+ case ValueUniformity::Default:
break;
}
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index 5b2d29f495cb0..7f6e42e54646b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -1801,24 +1801,23 @@ unsigned GCNTTIImpl::getNumberOfParts(Type *Tp) const {
return BaseT::getNumberOfParts(Tp);
}
-InstructionUniformity
-GCNTTIImpl::getInstructionUniformity(const Value *V) const {
+ValueUniformity GCNTTIImpl::getValueUniformity(const Value *V) const {
if (const IntrinsicInst *Intrinsic = dyn_cast<IntrinsicInst>(V)) {
switch (Intrinsic->getIntrinsicID()) {
case Intrinsic::amdgcn_wave_shuffle:
- return InstructionUniformity::Custom;
+ return ValueUniformity::Custom;
default:
break;
}
}
if (isAlwaysUniform(V))
- return InstructionUniformity::AlwaysUniform;
+ return ValueUniformity::AlwaysUniform;
if (isSourceOfDivergence(V))
- return InstructionUniformity::NeverUniform;
+ return ValueUniformity::NeverUniform;
- return InstructionUniformity::Default;
+ return ValueUniformity::Default;
}
InstructionCost GCNTTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
index 727cf966b5d8d..eb0a1f202412b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
@@ -312,7 +312,7 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
/// implementation.
unsigned getNumberOfParts(Type *Tp) const override;
- InstructionUniformity getInstructionUniformity(const Value *V) const override;
+ ValueUniformity getValueUniformity(const Value *V) const override;
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
StackOffset BaseOffset, bool HasBaseReg,
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index df2700d414893..bafa6cd800b5e 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -10725,8 +10725,8 @@ SIInstrInfo::getCalleeOperand(const MachineInstr &MI) const {
return TargetInstrInfo::getCalleeOperand(MI);
}
-InstructionUniformity
-SIInstrInfo::getGenericInstructionUniformity(const MachineInstr &MI) const {
+ValueUniformity
+SIInstrInfo::getGenericValueUniformity(const MachineInstr &MI) const {
const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
unsigned Opcode = MI.getOpcode();
@@ -10741,8 +10741,8 @@ SIInstrInfo::getGenericInstructionUniformity(const MachineInstr &MI) const {
return SrcAS == AMDGPUAS::PRIVATE_ADDRESS &&
DstAS == AMDGPUAS::FLAT_ADDRESS &&
ST.hasGloballyAddressableScratch()
- ? InstructionUniformity::NeverUniform
- : InstructionUniformity::Default;
+ ? ValueUniformity::NeverUniform
+ : ValueUniformity::Default;
};
// If the target supports globally addressable scratch, the mapping from
@@ -10754,9 +10754,9 @@ SIInstrInfo::getGenericInstructionUniformity(const MachineInstr &MI) const {
if (auto *GI = dyn_cast<GIntrinsic>(&MI)) {
auto IID = GI->getIntrinsicID();
if (AMDGPU::isIntrinsicSourceOfDivergence(IID))
- return InstructionUniformity::NeverUniform;
+ return ValueUniformity::NeverUniform;
if (AMDGPU::isIntrinsicAlwaysUniform(IID))
- return InstructionUniformity::AlwaysUniform;
+ return ValueUniformity::AlwaysUniform;
switch (IID) {
case Intrinsic::amdgcn_addrspacecast_nonnull:
@@ -10767,7 +10767,7 @@ SIInstrInfo::getGenericInstructionUniformity(const MachineInstr &MI) const {
break;
}
- return InstructionUniformity::Default;
+ return ValueUniformity::Default;
}
// Loads from the private and flat address spaces are divergent, because
@@ -10779,25 +10779,25 @@ SIInstrInfo::getGenericInstructionUniformity(const MachineInstr &MI) const {
if (Opcode == AMDGPU::G_LOAD || Opcode == AMDGPU::G_ZEXTLOAD ||
Opcode == AMDGPU::G_SEXTLOAD) {
if (MI.memoperands_empty())
- return InstructionUniformity::NeverUniform; // conservative assumption
+ return ValueUniformity::NeverUniform; // conservative assumption
if (llvm::any_of(MI.memoperands(), [](const MachineMemOperand *mmo) {
return mmo->getAddrSpace() == AMDGPUAS::PRIVATE_ADDRESS ||
mmo->getAddrSpace() == AMDGPUAS::FLAT_ADDRESS;
})) {
// At least one MMO in a non-global address space.
- return InstructionUniformity::NeverUniform;
+ return ValueUniformity::NeverUniform;
}
- return InstructionUniformity::Default;
+ return ValueUniformity::Default;
}
if (SIInstrInfo::isGenericAtomicRMWOpcode(Opcode) ||
Opcode == AMDGPU::G_ATOMIC_CMPXCHG ||
Opcode == AMDGPU::G_ATOMIC_CMPXCHG_WITH_SUCCESS ||
AMDGPU::isGenericAtomic(Opcode)) {
- return InstructionUniformity::NeverUniform;
+ return ValueUniformity::NeverUniform;
}
- return InstructionUniformity::Default;
+ return ValueUniformity::Default;
}
const MIRFormatter *SIInstrInfo::getMIRFormatter() const {
@@ -10806,32 +10806,31 @@ const MIRFormatter *SIInstrInfo::getMIRFormatter() const {
return Formatter.get();
}
-InstructionUniformity
-SIInstrInfo::getInstructionUniformity(const MachineInstr &MI) const {
+ValueUniformity SIInstrInfo::getValueUniformity(const MachineInstr &MI) const {
if (isNeverUniform(MI))
- return InstructionUniformity::NeverUniform;
+ return ValueUniformity::NeverUniform;
unsigned opcode = MI.getOpcode();
if (opcode == AMDGPU::V_READLANE_B32 ||
opcode == AMDGPU::V_READFIRSTLANE_B32 ||
opcode == AMDGPU::SI_RESTORE_S32_FROM_VGPR)
- return InstructionUniformity::AlwaysUniform;
+ return ValueUniformity::AlwaysUniform;
if (isCopyInstr(MI)) {
const MachineOperand &srcOp = MI.getOperand(1);
if (srcOp.isReg() && srcOp.getReg().isPhysical()) {
const TargetRegisterClass *regClass =
RI.getPhysRegBaseClass(srcOp.getReg());
- return RI.isSGPRClass(regClass) ? InstructionUniformity::AlwaysUniform
- : InstructionUniformity::NeverUniform;
+ return RI.isSGPRClass(regClass) ? ValueUniformity::AlwaysUniform
+ : ValueUniformity::NeverUniform;
}
- return InstructionUniformity::Default;
+ return ValueUniformity::Default;
}
// GMIR handling
if (MI.isPreISelOpcode())
- return SIInstrInfo::getGenericInstructionUniformity(MI);
+ return SIInstrInfo::getGenericValueUniformity(MI);
// Atomics are divergent because they are executed sequentially: when an
// atomic operation refers to the same address in each thread, then each
@@ -10839,24 +10838,24 @@ SIInstrInfo::getInstructionUniformity(const MachineInstr &MI) const {
// original value.
if (isAtomic(MI))
- return InstructionUniformity::NeverUniform;
+ return ValueUniformity::NeverUniform;
// Loads from the private and flat address spaces are divergent, because
// threads can execute the load instruction with the same inputs and get
//
diff erent results.
if (isFLAT(MI) && MI.mayLoad()) {
if (MI.memoperands_empty())
- return InstructionUniformity::NeverUniform; // conservative assumption
+ return ValueUniformity::NeverUniform; // conservative assumption
if (llvm::any_of(MI.memoperands(), [](const MachineMemOperand *mmo) {
return mmo->getAddrSpace() == AMDGPUAS::PRIVATE_ADDRESS ||
mmo->getAddrSpace() == AMDGPUAS::FLAT_ADDRESS;
})) {
// At least one MMO in a non-global address space.
- return InstructionUniformity::NeverUniform;
+ return ValueUniformity::NeverUniform;
}
- return InstructionUniformity::Default;
+ return ValueUniformity::Default;
}
const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
@@ -10878,7 +10877,7 @@ SIInstrInfo::getInstructionUniformity(const MachineInstr &MI) const {
// register, which are all scalars.
const RegisterBank *RegBank = RBI->getRegBank(Reg, MRI, RI);
if (RegBank && RegBank->getID() != AMDGPU::SGPRRegBankID)
- return InstructionUniformity::NeverUniform;
+ return ValueUniformity::NeverUniform;
}
// TODO: Uniformity check condtions above can be rearranged for more
@@ -10888,7 +10887,7 @@ SIInstrInfo::getInstructionUniformity(const MachineInstr &MI) const {
// currently turned into no-op COPYs by SelectionDAG ISel and are
// therefore no longer recognizable.
- return InstructionUniformity::Default;
+ return ValueUniformity::Default;
}
unsigned SIInstrInfo::getDSShaderTypeValue(const MachineFunction &MF) {
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index cc0b0408bc09c..a58e281de17a1 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1692,11 +1692,9 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
const MachineOperand &getCalleeOperand(const MachineInstr &MI) const override;
- InstructionUniformity
- getInstructionUniformity(const MachineInstr &MI) const final;
+ ValueUniformity getValueUniformity(const MachineInstr &MI) const final;
- InstructionUniformity
- getGenericInstructionUniformity(const MachineInstr &MI) const;
+ ValueUniformity getGenericValueUniformity(const MachineInstr &MI) const;
const MIRFormatter *getMIRFormatter() const override;
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
index 2965bfa744900..af560bb1f11bd 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
@@ -671,10 +671,9 @@ void NVPTXTTIImpl::collectKernelLaunchBounds(
LB.push_back({"maxntidz", MaxNTID[2]});
}
-InstructionUniformity
-NVPTXTTIImpl::getInstructionUniformity(const Value *V) const {
+ValueUniformity NVPTXTTIImpl::getValueUniformity(const Value *V) const {
if (isSourceOfDivergence(V))
- return InstructionUniformity::NeverUniform;
+ return ValueUniformity::NeverUniform;
- return InstructionUniformity::Default;
+ return ValueUniformity::Default;
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
index 899249db54574..b39c3fc733372 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
@@ -222,7 +222,7 @@ class NVPTXTTIImpl final : public BasicTTIImplBase<NVPTXTTIImpl> {
return false;
}
- InstructionUniformity getInstructionUniformity(const Value *V) const override;
+ ValueUniformity getValueUniformity(const Value *V) const override;
};
} // end namespace llvm
More information about the llvm-commits
mailing list