[llvm] [AArch64] MOVI lowering (PR #185526)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions h,cpp -- llvm/lib/Target/AArch64/AArch64ExpandImm.cpp llvm/lib/Target/AArch64/AArch64ExpandImm.h llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index bc271b9bc..e97263db1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -5098,20 +5098,20 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
         default:
           llvm_unreachable("Unexpected node in expandVectorMOVImm\n");
         }
-        }
+      }
 
-        if (VT.getSizeInBits() < FVT.getSizeInBits())
-          Src = CurDAG->getMachineNode(
-              TargetOpcode::EXTRACT_SUBREG, DL, VT, SDValue(Src, 0),
-              CurDAG->getTargetConstant(
-                  VT.getSizeInBits() == 16 ? AArch64::hsub : AArch64::ssub, DL,
-                  MVT::i32));
+      if (VT.getSizeInBits() < FVT.getSizeInBits())
+        Src = CurDAG->getMachineNode(
+            TargetOpcode::EXTRACT_SUBREG, DL, VT, SDValue(Src, 0),
+            CurDAG->getTargetConstant(VT.getSizeInBits() == 16 ? AArch64::hsub
+                                                               : AArch64::ssub,
+                                      DL, MVT::i32));
 
-        ReplaceNode(Node, Src);
-        return;
-      }
-      break;
+      ReplaceNode(Node, Src);
+      return;
     }
+    break;
+  }
 
   case ISD::FrameIndex: {
     // Selects to ADDXri FI, 0 which in turn will become ADDXri SP, imm.
@@ -7665,9 +7665,9 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
   }
   }
 
-    // Select the default instruction
-    SelectCode(Node);
-  }
+  // Select the default instruction
+  SelectCode(Node);
+}
 
 /// createAArch64ISelDag - This pass converts a legalized DAG into a
 /// AArch64-specific DAG, ready for instruction scheduling.

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https://github.com/llvm/llvm-project/pull/185526