[llvm] [RFC][IR] Add llvm.masked.{udiv, sdiv, urem, srem} intrinsics (PR #189705)

[Luke Lau via llvm-commits]

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@@ -263,6 +270,27 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
                      LHS.getValueType(), LHS, RHS, N->getFlags());
 }
 
+SDValue DAGTypeLegalizer::ScalarizeVecRes_MaskedBinOp(SDNode *N) {
+  SDLoc DL(N);
+  SDValue LHS = GetScalarizedVector(N->getOperand(0));
+  SDValue RHS = GetScalarizedVector(N->getOperand(1));
+  SDValue Mask = N->getOperand(2);
+  EVT MaskVT = Mask.getValueType();
+  // The vselect result and input vectors need scalarizing, but it's
+  // not a given that the mask does. For instance, in AVX512 v1i1 is legal.
+  // See the similar logic in ScalarizeVecRes_SETCC.
+  if (getTypeAction(MaskVT) == TargetLowering::TypeScalarizeVector)
+    Mask = GetScalarizedVector(Mask);
+  else
+    Mask = DAG.getExtractVectorElt(DL, MaskVT.getVectorElementType(), Mask, 0);
+  // Masked binary ops don't have UB on disabled lanes but produce poison, so
+  // use 1 as the divisor to avoid division by zero.
+  SDValue Divisor = DAG.getSelect(DL, LHS.getValueType(), Mask, RHS,
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lukel97 wrote:

I could only find places where we convert scalar boolean contents back to vector boolean contents e.g. `ScalarizeVecOp_VSETCC` which uses `TargetLowering::getExtendForContent`. So I just truncated it to `MVT::i1`, which I think should work for all boolean content types, and let type legalization promote it to the right type with the right extend in b79ad48905152288d384150c5e97de6389b229cb

https://github.com/llvm/llvm-project/pull/189705