[llvm] [AArch64][llvm] Encode `stshh` as a `HINT` alias (NFC) (PR #189926)

[Jonathan Thackray via llvm-commits]

https://github.com/jthackray created https://github.com/llvm/llvm-project/pull/189926

Implement `stshh` as a `HINT` alias instead of a dedicated system opcode.
The Arm ARM says that `stshh` is in the `HINT` encoding space, but it is
currently written as a separate class.

Change this to be an alias of `HINT` and the `PHint` definition to only
use 7 bits. Also update the `stshh` pseudo expansion for the intrinsic
to emit `HINT #0x30 | policy`.

No test changes.

>From 25eb4f419f141f2989db0da8776bca1dde0612a3 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray <jonathan.thackray at arm.com>
Date: Tue, 31 Mar 2026 01:18:43 +0100
Subject: [PATCH] [AArch64][llvm] Encode `stshh` as a `HINT` alias (NFC)

Implement `stshh` as a `HINT` alias instead of a dedicated system opcode.
The Arm ARM says that `stshh` is in the `HINT` encoding space, but it is
currently written as a separate class.

Change this to be an alias of `HINT` and the `PHint` definition to only
use 7 bits. Also update the `stshh` pseudo expansion for the intrinsic
to emit `HINT #0x30 | policy`.

No test changes.
---
 .../Target/AArch64/AArch64ExpandPseudoInsts.cpp  |  4 ++--
 llvm/lib/Target/AArch64/AArch64InstrFormats.td   | 16 ++++++----------
 llvm/lib/Target/AArch64/AArch64InstrInfo.td      |  2 +-
 llvm/lib/Target/AArch64/AArch64SystemOperands.td | 15 +++++----------
 llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h  |  2 +-
 5 files changed, 15 insertions(+), 24 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index 4ab8adeb2c9bc..4be51d67a6045 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -1092,8 +1092,8 @@ bool AArch64ExpandPseudoImpl::expandSTSHHAtomicStore(
   }
 
   // Emit the hint with the retention policy immediate.
-  MachineInstr *Hint = BuildMI(MBB, MBBI, DL, TII->get(AArch64::STSHH))
-                           .addImm(Policy)
+  MachineInstr *Hint = BuildMI(MBB, MBBI, DL, TII->get(AArch64::HINT))
+                           .addImm(0x30 | Policy)
                            .getInstr();
 
   // Emit the associated store instruction.
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 1774927e9297d..31b55242d1d1e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1867,18 +1867,14 @@ def PHintInstOperand : AsmOperandClass {
 def phint_op : Operand<i32> {
     let ParserMatchClass = PHintInstOperand;
     let PrintMethod = "printPHintOp";
+    let MCOperandPredicate = [{
+      if (!MCOp.isImm())
+        return false;
+      return AArch64PHint::lookupPHintByEncoding(MCOp.getImm()) != nullptr;
+    }];
     let OperandType = "OPERAND_IMMEDIATE";
     let MIOperandInfo = (ops i32imm: $policy);
-    let DecoderMethod = "DecodeUImm<3>";
-}
-
-class STSHHI
-    : SimpleSystemI<0, (ins phint_op:$policy), "stshh", "\t$policy", []>,
-      Sched<[WriteHint]> {
-  bits<3> policy;
-  let Inst{20-12} = 0b000110010;
-  let Inst{11-8} = 0b0110;
-  let Inst{7-5} = policy;
+    let DecoderMethod = "DecodeUImm<7>";
 }
 
 // System instructions taking a single literal operand which encodes into
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 08512f6ed8df1..1353568454c7a 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1566,7 +1566,7 @@ def NOP : SystemNoOperands<0b000, "hint\t#0">;
 
 def : InstAlias<"nop", (NOP)>;
 
-def STSHH: STSHHI;
+def : InstAlias<"stshh $policy", (HINT phint_op:$policy)>;
 
 let hasSideEffects = 1, mayStore = 1, isCodeGenOnly = 1 in {
 let Size = 8 in
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index b3f03f9ea0c02..90751829f346d 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -2450,15 +2450,10 @@ def : RWSysReg<"ACTLRALIAS_EL1",  0b11, 0b000, 0b0001, 0b0100, 0b101>;
 // v9.6a PCDPHINT instruction options.
 //===----------------------------------------------------------------------===//
 
-class PHint<bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
-              bits<3> op2, string name> {
+class PHint<string name, bits<7> encoding> {
   string Name = name;
-  bits<16> Encoding;
-  let Encoding{15-14} = op0;
-  let Encoding{13-11} = op1;
-  let Encoding{10-7} = crn;
-  let Encoding{6-3} = crm;
-  let Encoding{2-0} = op2;
+  bits<7> Encoding;
+  let Encoding = encoding;
   code Requires = [{ {} }];
 }
 
@@ -2481,8 +2476,8 @@ def lookupPHintByName : SearchIndex {
   let Key = ["Name"];
 }
 
-def KEEP : PHint<0b00, 0b000, 0b0000, 0b0000, 0b000, "keep">;
-def STRM : PHint<0b00, 0b000, 0b0000, 0b0000, 0b001, "strm">;
+def KEEP : PHint<"keep", 0b0110000>;
+def STRM : PHint<"strm", 0b0110001>;
 
 // v9.6a Realm management extension enhancements
 def : RWSysReg<"GPCBW_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b101>;
diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
index 38b2b3ec1e8dc..786d5ec81c9df 100644
--- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
@@ -711,7 +711,7 @@ struct PHint {
 #include "AArch64GenSystemOperands.inc"
 
 const PHint *lookupPHintByName(StringRef);
-const PHint *lookupPHintByEncoding(uint16_t);
+const PHint *lookupPHintByEncoding(uint8_t);
 } // namespace AArch64PHint
 
 namespace AArch64BTIHint {