[llvm] [LLVM][Intrinsics] Refactor IIT encoding generation (PR #189790)

[Nikita Popov via llvm-commits]

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@@ -243,52 +243,40 @@ def ArgKind {
   int MatchType  = 7;
 }
 
-// Encode placeholder.
-// [15:8] is the ID used how to resolve ArgCode.
-
-// (ACIdx << 3) | ArgCode
-class EncAnyType<int ArgCode=0> {
+// Placeholder to encode the overload index of the current type. We encode bit
+// 8 = 1 to indicate that this entry needs to be patched up with the overload
+// index (to prevent conflict with any valid not-to-be-patched IIT enccoding
+// byte, whose value will be <= 255). The ArgKind itself is in the lower bits.
+// Note that this is just a transient representation till its gets processed
+// by `DoPatchOverloadIndex` below, so this is *not* the encoding of the
+// final type signature.
+class PatchOverloadIndex<int ArgKindVal> {
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nikic wrote:

I find this name confusing, esp. in conjunction with DoPatchOverloadIndex. Maybe OverloadIndexPlaceholder or so?

https://github.com/llvm/llvm-project/pull/189790