[llvm] [RISCV] Remove codegen for vp_lrint, vp_llrint (PR #189714)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 31 23:18:48 PDT 2026
https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/189714
>From c0d2f502c2f7cec654e1ac6be1393be4b4e09502 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 1 Apr 2026 01:01:23 +0800
Subject: [PATCH] [RISCV] Remove codegen for vp_lrint, vp_llrint
Part of the work to remove trivial VP intrinsics from the RISC-V backend, see https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off two intrinsics from #179622.
We need to use the other intrinsic constructor in ExpandVectorPredication.cpp because llrint has multiple overloaded types
---
llvm/lib/CodeGen/ExpandVectorPredication.cpp | 10 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 9 +-
.../Target/RISCV/RISCVTargetTransformInfo.h | 2 -
.../RISCV/rvv/fixed-vectors-llrint-vp.ll | 80 +++++------
.../RISCV/rvv/fixed-vectors-lrint-vp.ll | 120 ++++++++---------
llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll | 53 +++-----
llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll | 125 ++++++++----------
7 files changed, 182 insertions(+), 217 deletions(-)
diff --git a/llvm/lib/CodeGen/ExpandVectorPredication.cpp b/llvm/lib/CodeGen/ExpandVectorPredication.cpp
index fa61a0fa02d73..5f03c9ef9ade3 100644
--- a/llvm/lib/CodeGen/ExpandVectorPredication.cpp
+++ b/llvm/lib/CodeGen/ExpandVectorPredication.cpp
@@ -289,13 +289,15 @@ bool CachingVPExpander::expandPredicationToFPCall(
case Intrinsic::maxnum:
case Intrinsic::minnum:
case Intrinsic::maximum:
- case Intrinsic::minimum: {
+ case Intrinsic::minimum:
+ case Intrinsic::lrint:
+ case Intrinsic::llrint: {
SmallVector<Value *, 2> Argument;
for (unsigned i = 0; i < VPI.getNumOperands() - 3; i++) {
Argument.push_back(VPI.getOperand(i));
}
- Value *NewOp = Builder.CreateIntrinsic(UnpredicatedIntrinsicID,
- {VPI.getType()}, Argument);
+ Value *NewOp = Builder.CreateIntrinsic(VPI.getType(),
+ UnpredicatedIntrinsicID, Argument);
replaceOperation(*NewOp, VPI);
return true;
}
@@ -615,6 +617,8 @@ bool CachingVPExpander::expandPredication(VPIntrinsic &VPI) {
case Intrinsic::vp_minnum:
case Intrinsic::vp_maximum:
case Intrinsic::vp_minimum:
+ case Intrinsic::vp_lrint:
+ case Intrinsic::vp_llrint:
case Intrinsic::vp_fma:
case Intrinsic::vp_fmuladd:
return expandPredicationToFPCall(Builder, VPI,
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 3a8d9270fdd10..53013cd23ba40 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -891,8 +891,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VP_FCEIL, ISD::VP_FFLOOR, ISD::VP_FROUND,
ISD::VP_FROUNDEVEN, ISD::VP_FCOPYSIGN, ISD::VP_FROUNDTOZERO,
ISD::VP_FRINT, ISD::VP_FNEARBYINT, ISD::VP_IS_FPCLASS,
- ISD::VP_LRINT, ISD::VP_LLRINT, ISD::VP_REDUCE_FMINIMUM,
- ISD::VP_REDUCE_FMAXIMUM};
+ ISD::VP_REDUCE_FMINIMUM, ISD::VP_REDUCE_FMAXIMUM};
static const unsigned IntegerVecReduceOps[] = {
ISD::VECREDUCE_ADD, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR,
@@ -3622,8 +3621,6 @@ static RISCVFPRndMode::RoundingMode matchRoundingOp(unsigned Opc) {
case ISD::STRICT_LRINT:
case ISD::STRICT_LLRINT:
case ISD::VP_FRINT:
- case ISD::VP_LRINT:
- case ISD::VP_LLRINT:
return RISCVFPRndMode::DYN;
}
@@ -7711,9 +7708,7 @@ static unsigned getRISCVVLOp(SDValue Op) {
case ISD::VP_FMAXNUM:
return RISCVISD::VFMAX_VL;
case ISD::LRINT:
- case ISD::VP_LRINT:
case ISD::LLRINT:
- case ISD::VP_LLRINT:
return RISCVISD::VFCVT_RM_X_F_VL;
}
// clang-format on
@@ -9050,8 +9045,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::VP_USUBSAT:
case ISD::VP_SADDSAT:
case ISD::VP_SSUBSAT:
- case ISD::VP_LRINT:
- case ISD::VP_LLRINT:
return lowerVPOp(Op, DAG);
case ISD::VP_AND:
case ISD::VP_OR:
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 5ea13b31f2ddf..18e0ab9b72608 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -402,10 +402,8 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
Intrinsic::vp_icmp,
Intrinsic::vp_inttoptr,
Intrinsic::vp_is_fpclass,
- Intrinsic::vp_llrint,
Intrinsic::vp_load,
Intrinsic::vp_load_ff,
- Intrinsic::vp_lrint,
Intrinsic::vp_lshr,
Intrinsic::vp_maxnum,
Intrinsic::vp_merge,
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
index 1282a6f9f8c6d..d9aaab1d168b1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
@@ -7,15 +7,15 @@
define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x, <1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: llrint_v1i64_v1f32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV32-NEXT: vfwcvt.x.f.v v9, v8, v0.t
+; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; RV32-NEXT: vfwcvt.x.f.v v9, v8
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: llrint_v1i64_v1f32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV64-NEXT: vfwcvt.x.f.v v9, v8, v0.t
+; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; RV64-NEXT: vfwcvt.x.f.v v9, v8
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%a = call <1 x i64> @llvm.vp.llrint.v1i64.v1f32(<1 x float> %x, <1 x i1> %m, i32 %evl)
@@ -25,15 +25,15 @@ define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x, <1 x i1> %m, i32 zeroext %e
define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: llrint_v2i64_v2f32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV32-NEXT: vfwcvt.x.f.v v9, v8, v0.t
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV32-NEXT: vfwcvt.x.f.v v9, v8
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: llrint_v2i64_v2f32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV64-NEXT: vfwcvt.x.f.v v9, v8, v0.t
+; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV64-NEXT: vfwcvt.x.f.v v9, v8
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%a = call <2 x i64> @llvm.vp.llrint.v2i64.v2f32(<2 x float> %x, <2 x i1> %m, i32 %evl)
@@ -43,16 +43,16 @@ define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x, <2 x i1> %m, i32 zeroext %e
define <3 x i64> @llrint_v3i64_v3f32(<3 x float> %x, <3 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: llrint_v3i64_v3f32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv1r.v v10, v8
-; RV32-NEXT: vfwcvt.x.f.v v8, v10, v0.t
+; RV32-NEXT: vfwcvt.x.f.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: llrint_v3i64_v3f32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vmv1r.v v10, v8
-; RV64-NEXT: vfwcvt.x.f.v v8, v10, v0.t
+; RV64-NEXT: vfwcvt.x.f.v v8, v10
; RV64-NEXT: ret
%a = call <3 x i64> @llvm.vp.llrint.v3i64.v3f32(<3 x float> %x, <3 x i1> %m, i32 %evl)
ret <3 x i64> %a
@@ -61,16 +61,16 @@ define <3 x i64> @llrint_v3i64_v3f32(<3 x float> %x, <3 x i1> %m, i32 zeroext %e
define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: llrint_v4i64_v4f32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv1r.v v10, v8
-; RV32-NEXT: vfwcvt.x.f.v v8, v10, v0.t
+; RV32-NEXT: vfwcvt.x.f.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: llrint_v4i64_v4f32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vmv1r.v v10, v8
-; RV64-NEXT: vfwcvt.x.f.v v8, v10, v0.t
+; RV64-NEXT: vfwcvt.x.f.v v8, v10
; RV64-NEXT: ret
%a = call <4 x i64> @llvm.vp.llrint.v4i64.v4f32(<4 x float> %x, <4 x i1> %m, i32 %evl)
ret <4 x i64> %a
@@ -79,16 +79,16 @@ define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x, <4 x i1> %m, i32 zeroext %e
define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: llrint_v8i64_v8f32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv2r.v v12, v8
-; RV32-NEXT: vfwcvt.x.f.v v8, v12, v0.t
+; RV32-NEXT: vfwcvt.x.f.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: llrint_v8i64_v8f32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64-NEXT: vmv2r.v v12, v8
-; RV64-NEXT: vfwcvt.x.f.v v8, v12, v0.t
+; RV64-NEXT: vfwcvt.x.f.v v8, v12
; RV64-NEXT: ret
%a = call <8 x i64> @llvm.vp.llrint.v8i64.v8f32(<8 x float> %x, <8 x i1> %m, i32 %evl)
ret <8 x i64> %a
@@ -97,16 +97,16 @@ define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x, <8 x i1> %m, i32 zeroext %e
define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: llrint_v16i64_v16f32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv4r.v v16, v8
-; RV32-NEXT: vfwcvt.x.f.v v8, v16, v0.t
+; RV32-NEXT: vfwcvt.x.f.v v8, v16
; RV32-NEXT: ret
;
; RV64-LABEL: llrint_v16i64_v16f32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-NEXT: vmv4r.v v16, v8
-; RV64-NEXT: vfwcvt.x.f.v v8, v16, v0.t
+; RV64-NEXT: vfwcvt.x.f.v v8, v16
; RV64-NEXT: ret
%a = call <16 x i64> @llvm.vp.llrint.v16i64.v16f32(<16 x float> %x, <16 x i1> %m, i32 %evl)
ret <16 x i64> %a
@@ -115,14 +115,14 @@ define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x, <16 x i1> %m, i32 zeroe
define <1 x i64> @llrint_v1i64_v1f64(<1 x double> %x, <1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: llrint_v1i64_v1f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: ret
;
; RV64-LABEL: llrint_v1i64_v1f64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-NEXT: vfcvt.x.f.v v8, v8
; RV64-NEXT: ret
%a = call <1 x i64> @llvm.vp.llrint.v1i64.v1f64(<1 x double> %x, <1 x i1> %m, i32 %evl)
ret <1 x i64> %a
@@ -131,14 +131,14 @@ define <1 x i64> @llrint_v1i64_v1f64(<1 x double> %x, <1 x i1> %m, i32 zeroext %
define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: llrint_v2i64_v2f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: ret
;
; RV64-LABEL: llrint_v2i64_v2f64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV64-NEXT: vfcvt.x.f.v v8, v8
; RV64-NEXT: ret
%a = call <2 x i64> @llvm.vp.llrint.v2i64.v2f64(<2 x double> %x, <2 x i1> %m, i32 %evl)
ret <2 x i64> %a
@@ -147,14 +147,14 @@ define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x, <2 x i1> %m, i32 zeroext %
define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: llrint_v4i64_v4f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: ret
;
; RV64-LABEL: llrint_v4i64_v4f64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64-NEXT: vfcvt.x.f.v v8, v8
; RV64-NEXT: ret
%a = call <4 x i64> @llvm.vp.llrint.v4i64.v4f64(<4 x double> %x, <4 x i1> %m, i32 %evl)
ret <4 x i64> %a
@@ -163,14 +163,14 @@ define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x, <4 x i1> %m, i32 zeroext %
define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: llrint_v8i64_v8f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: ret
;
; RV64-LABEL: llrint_v8i64_v8f64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64-NEXT: vfcvt.x.f.v v8, v8
; RV64-NEXT: ret
%a = call <8 x i64> @llvm.vp.llrint.v8i64.v8f64(<8 x double> %x, <8 x i1> %m, i32 %evl)
ret <8 x i64> %a
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
index 613e3e1618732..6fd52a3f05c0d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
@@ -9,20 +9,20 @@
define <1 x iXLen> @lrint_v1f32(<1 x float> %x, <1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_v1f32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_v1f32:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v8
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_v1f32:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV64-i64-NEXT: vfwcvt.x.f.v v9, v8, v0.t
+; RV64-i64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; RV64-i64-NEXT: vfwcvt.x.f.v v9, v8
; RV64-i64-NEXT: vmv1r.v v8, v9
; RV64-i64-NEXT: ret
%a = call <1 x iXLen> @llvm.vp.lrint.v1iXLen.v1f32(<1 x float> %x, <1 x i1> %m, i32 %evl)
@@ -32,20 +32,20 @@ define <1 x iXLen> @lrint_v1f32(<1 x float> %x, <1 x i1> %m, i32 zeroext %evl) {
define <2 x iXLen> @lrint_v2f32(<2 x float> %x, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_v2f32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_v2f32:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v8
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_v2f32:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV64-i64-NEXT: vfwcvt.x.f.v v9, v8, v0.t
+; RV64-i64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV64-i64-NEXT: vfwcvt.x.f.v v9, v8
; RV64-i64-NEXT: vmv1r.v v8, v9
; RV64-i64-NEXT: ret
%a = call <2 x iXLen> @llvm.vp.lrint.v2iXLen.v2f32(<2 x float> %x, <2 x i1> %m, i32 %evl)
@@ -55,21 +55,21 @@ define <2 x iXLen> @lrint_v2f32(<2 x float> %x, <2 x i1> %m, i32 zeroext %evl) {
define <3 x iXLen> @lrint_v3f32(<3 x float> %x, <3 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_v3f32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_v3f32:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v8
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_v3f32:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-i64-NEXT: vmv1r.v v10, v8
-; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10, v0.t
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10
; RV64-i64-NEXT: ret
%a = call <3 x iXLen> @llvm.vp.lrint.v3iXLen.v3f32(<3 x float> %x, <3 x i1> %m, i32 %evl)
ret <3 x iXLen> %a
@@ -78,21 +78,21 @@ define <3 x iXLen> @lrint_v3f32(<3 x float> %x, <3 x i1> %m, i32 zeroext %evl) {
define <4 x iXLen> @lrint_v4f32(<4 x float> %x, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_v4f32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_v4f32:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v8
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_v4f32:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-i64-NEXT: vmv1r.v v10, v8
-; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10, v0.t
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10
; RV64-i64-NEXT: ret
%a = call <4 x iXLen> @llvm.vp.lrint.v4iXLen.v4f32(<4 x float> %x, <4 x i1> %m, i32 %evl)
ret <4 x iXLen> %a
@@ -101,21 +101,21 @@ define <4 x iXLen> @lrint_v4f32(<4 x float> %x, <4 x i1> %m, i32 zeroext %evl) {
define <8 x iXLen> @lrint_v8f32(<8 x float> %x, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_v8f32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_v8f32:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v8
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_v8f32:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64-i64-NEXT: vmv2r.v v12, v8
-; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12, v0.t
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12
; RV64-i64-NEXT: ret
%a = call <8 x iXLen> @llvm.vp.lrint.v8iXLen.v8f32(<8 x float> %x, <8 x i1> %m, i32 %evl)
ret <8 x iXLen> %a
@@ -124,21 +124,21 @@ define <8 x iXLen> @lrint_v8f32(<8 x float> %x, <8 x i1> %m, i32 zeroext %evl) {
define <16 x iXLen> @lrint_v16f32(<16 x float> %x, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_v16f32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_v16f32:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v8
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_v16f32:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-i64-NEXT: vmv4r.v v16, v8
-; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16, v0.t
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16
; RV64-i64-NEXT: ret
%a = call <16 x iXLen> @llvm.vp.lrint.v16iXLen.v16f32(<16 x float> %x, <16 x i1> %m, i32 %evl)
ret <16 x iXLen> %a
@@ -147,22 +147,22 @@ define <16 x iXLen> @lrint_v16f32(<16 x float> %x, <16 x i1> %m, i32 zeroext %ev
define <1 x iXLen> @lrint_v1f64(<1 x double> %x, <1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_v1f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV32-NEXT: vfncvt.x.f.w v9, v8, v0.t
+; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; RV32-NEXT: vfncvt.x.f.w v9, v8
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_v1f64:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV64-i32-NEXT: vfncvt.x.f.w v9, v8, v0.t
+; RV64-i32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; RV64-i32-NEXT: vfncvt.x.f.w v9, v8
; RV64-i32-NEXT: vmv1r.v v8, v9
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_v1f64:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV64-i64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; RV64-i64-NEXT: vfcvt.x.f.v v8, v8
; RV64-i64-NEXT: ret
%a = call <1 x iXLen> @llvm.vp.lrint.v1iXLen.v1f64(<1 x double> %x, <1 x i1> %m, i32 %evl)
ret <1 x iXLen> %a
@@ -171,22 +171,22 @@ define <1 x iXLen> @lrint_v1f64(<1 x double> %x, <1 x i1> %m, i32 zeroext %evl)
define <2 x iXLen> @lrint_v2f64(<2 x double> %x, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_v2f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV32-NEXT: vfncvt.x.f.w v9, v8, v0.t
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV32-NEXT: vfncvt.x.f.w v9, v8
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_v2f64:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV64-i32-NEXT: vfncvt.x.f.w v9, v8, v0.t
+; RV64-i32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV64-i32-NEXT: vfncvt.x.f.w v9, v8
; RV64-i32-NEXT: vmv1r.v v8, v9
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_v2f64:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV64-i64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV64-i64-NEXT: vfcvt.x.f.v v8, v8
; RV64-i64-NEXT: ret
%a = call <2 x iXLen> @llvm.vp.lrint.v2iXLen.v2f64(<2 x double> %x, <2 x i1> %m, i32 %evl)
ret <2 x iXLen> %a
@@ -195,22 +195,22 @@ define <2 x iXLen> @lrint_v2f64(<2 x double> %x, <2 x i1> %m, i32 zeroext %evl)
define <4 x iXLen> @lrint_v4f64(<4 x double> %x, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_v4f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; RV32-NEXT: vfncvt.x.f.w v10, v8, v0.t
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT: vfncvt.x.f.w v10, v8
; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_v4f64:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; RV64-i32-NEXT: vfncvt.x.f.w v10, v8, v0.t
+; RV64-i32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV64-i32-NEXT: vfncvt.x.f.w v10, v8
; RV64-i32-NEXT: vmv.v.v v8, v10
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_v4f64:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV64-i64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64-i64-NEXT: vfcvt.x.f.v v8, v8
; RV64-i64-NEXT: ret
%a = call <4 x iXLen> @llvm.vp.lrint.v4iXLen.v4f64(<4 x double> %x, <4 x i1> %m, i32 %evl)
ret <4 x iXLen> %a
@@ -219,22 +219,22 @@ define <4 x iXLen> @lrint_v4f64(<4 x double> %x, <4 x i1> %m, i32 zeroext %evl)
define <8 x iXLen> @lrint_v8f64(<8 x double> %x, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_v8f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; RV32-NEXT: vfncvt.x.f.w v12, v8, v0.t
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV32-NEXT: vfncvt.x.f.w v12, v8
; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_v8f64:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; RV64-i32-NEXT: vfncvt.x.f.w v12, v8, v0.t
+; RV64-i32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64-i32-NEXT: vfncvt.x.f.w v12, v8
; RV64-i32-NEXT: vmv.v.v v8, v12
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_v8f64:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV64-i64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64-i64-NEXT: vfcvt.x.f.v v8, v8
; RV64-i64-NEXT: ret
%a = call <8 x iXLen> @llvm.vp.lrint.v8iXLen.v8f64(<8 x double> %x, <8 x i1> %m, i32 %evl)
ret <8 x iXLen> %a
diff --git a/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
index c0a794afac3ae..4de3dfc6c08a5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
@@ -7,8 +7,8 @@
define <vscale x 1 x i64> @llrint_nxv1i64_nxv1f32(<vscale x 1 x float> %x, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: llrint_nxv1i64_nxv1f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vfwcvt.x.f.v v9, v8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.x.f.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.vp.llrint.nxv1i64.nxv1f32(<vscale x 1 x float> %x, <vscale x 1 x i1> %m, i32 %evl)
@@ -18,9 +18,9 @@ define <vscale x 1 x i64> @llrint_nxv1i64_nxv1f32(<vscale x 1 x float> %x, <vsca
define <vscale x 2 x i64> @llrint_nxv2i64_nxv2f32(<vscale x 2 x float> %x, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: llrint_nxv2i64_nxv2f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vfwcvt.x.f.v v8, v10, v0.t
+; CHECK-NEXT: vfwcvt.x.f.v v8, v10
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.vp.llrint.nxv2i64.nxv2f32(<vscale x 2 x float> %x, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %a
@@ -29,9 +29,9 @@ define <vscale x 2 x i64> @llrint_nxv2i64_nxv2f32(<vscale x 2 x float> %x, <vsca
define <vscale x 4 x i64> @llrint_nxv4i64_nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: llrint_nxv4i64_nxv4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vmv2r.v v12, v8
-; CHECK-NEXT: vfwcvt.x.f.v v8, v12, v0.t
+; CHECK-NEXT: vfwcvt.x.f.v v8, v12
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.vp.llrint.nxv4i64.nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %a
@@ -40,9 +40,9 @@ define <vscale x 4 x i64> @llrint_nxv4i64_nxv4f32(<vscale x 4 x float> %x, <vsca
define <vscale x 8 x i64> @llrint_nxv8i64_nxv8f32(<vscale x 8 x float> %x, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: llrint_nxv8i64_nxv8f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv4r.v v16, v8
-; CHECK-NEXT: vfwcvt.x.f.v v8, v16, v0.t
+; CHECK-NEXT: vfwcvt.x.f.v v8, v16
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.vp.llrint.nxv8i64.nxv8f32(<vscale x 8 x float> %x, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %a
@@ -51,24 +51,9 @@ define <vscale x 8 x i64> @llrint_nxv8i64_nxv8f32(<vscale x 8 x float> %x, <vsca
define <vscale x 16 x i64> @llrint_nxv16i64_nxv16f32(<vscale x 16 x float> %x, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: llrint_nxv16i64_nxv16f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma
-; CHECK-NEXT: vfwcvt.x.f.v v16, v12, v0.t
-; CHECK-NEXT: bltu a0, a1, .LBB4_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB4_2:
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfwcvt.x.f.v v24, v8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vfwcvt.x.f.v v24, v8
+; CHECK-NEXT: vfwcvt.x.f.v v16, v12
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
%a = call <vscale x 16 x i64> @llvm.vp.llrint.nxv16i64.nxv16f32(<vscale x 16 x float> %x, <vscale x 16 x i1> %m, i32 %evl)
@@ -78,8 +63,8 @@ define <vscale x 16 x i64> @llrint_nxv16i64_nxv16f32(<vscale x 16 x float> %x, <
define <vscale x 1 x i64> @llrint_nxv1i64_nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: llrint_nxv1i64_nxv1f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.vp.llrint.nxv1i64.nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %a
@@ -88,8 +73,8 @@ define <vscale x 1 x i64> @llrint_nxv1i64_nxv1f64(<vscale x 1 x double> %x, <vsc
define <vscale x 2 x i64> @llrint_nxv2i64_nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: llrint_nxv2i64_nxv2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.vp.llrint.nxv2i64.nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %a
@@ -98,8 +83,8 @@ define <vscale x 2 x i64> @llrint_nxv2i64_nxv2f64(<vscale x 2 x double> %x, <vsc
define <vscale x 4 x i64> @llrint_nxv4i64_nxv4f64(<vscale x 4 x double> %x, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: llrint_nxv4i64_nxv4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.vp.llrint.nxv4i64.nxv4f64(<vscale x 4 x double> %x, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %a
@@ -108,8 +93,8 @@ define <vscale x 4 x i64> @llrint_nxv4i64_nxv4f64(<vscale x 4 x double> %x, <vsc
define <vscale x 8 x i64> @llrint_nxv8i64_nxv8f64(<vscale x 8 x double> %x, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: llrint_nxv8i64_nxv8f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.vp.llrint.nxv8i64.nxv8f64(<vscale x 8 x double> %x, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %a
diff --git a/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
index c09df1a60d2ae..889f6e62342a0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
@@ -9,20 +9,20 @@
define <vscale x 1 x iXLen> @lrint_nxv1f32(<vscale x 1 x float> %x, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_nxv1f32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_nxv1f32:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v8
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_nxv1f32:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV64-i64-NEXT: vfwcvt.x.f.v v9, v8, v0.t
+; RV64-i64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; RV64-i64-NEXT: vfwcvt.x.f.v v9, v8
; RV64-i64-NEXT: vmv1r.v v8, v9
; RV64-i64-NEXT: ret
%a = call <vscale x 1 x iXLen> @llvm.vp.lrint.nxv1iXLen.nxv1f32(<vscale x 1 x float> %x, <vscale x 1 x i1> %m, i32 %evl)
@@ -32,21 +32,21 @@ define <vscale x 1 x iXLen> @lrint_nxv1f32(<vscale x 1 x float> %x, <vscale x 1
define <vscale x 2 x iXLen> @lrint_nxv2f32(<vscale x 2 x float> %x, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_nxv2f32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_nxv2f32:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v8
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_nxv2f32:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; RV64-i64-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; RV64-i64-NEXT: vmv1r.v v10, v8
-; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10, v0.t
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10
; RV64-i64-NEXT: ret
%a = call <vscale x 2 x iXLen> @llvm.vp.lrint.nxv2iXLen.nxv2f32(<vscale x 2 x float> %x, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x iXLen> %a
@@ -55,21 +55,21 @@ define <vscale x 2 x iXLen> @lrint_nxv2f32(<vscale x 2 x float> %x, <vscale x 2
define <vscale x 4 x iXLen> @lrint_nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_nxv4f32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_nxv4f32:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v8
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_nxv4f32:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; RV64-i64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; RV64-i64-NEXT: vmv2r.v v12, v8
-; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12, v0.t
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12
; RV64-i64-NEXT: ret
%a = call <vscale x 4 x iXLen> @llvm.vp.lrint.nxv4iXLen.nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x iXLen> %a
@@ -78,21 +78,21 @@ define <vscale x 4 x iXLen> @lrint_nxv4f32(<vscale x 4 x float> %x, <vscale x 4
define <vscale x 8 x iXLen> @lrint_nxv8f32(<vscale x 8 x float> %x, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_nxv8f32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_nxv8f32:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i32-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v8
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_nxv8f32:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; RV64-i64-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; RV64-i64-NEXT: vmv4r.v v16, v8
-; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16, v0.t
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16
; RV64-i64-NEXT: ret
%a = call <vscale x 8 x iXLen> @llvm.vp.lrint.nxv8iXLen.nxv8f32(<vscale x 8 x float> %x, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x iXLen> %a
@@ -101,36 +101,21 @@ define <vscale x 8 x iXLen> @lrint_nxv8f32(<vscale x 8 x float> %x, <vscale x 8
define <vscale x 16 x iXLen> @lrint_nxv16f32(<vscale x 16 x float> %x, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_nxv16f32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_nxv16f32:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v8
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_nxv16f32:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; RV64-i64-NEXT: vmv1r.v v24, v0
-; RV64-i64-NEXT: csrr a1, vlenb
-; RV64-i64-NEXT: srli a2, a1, 3
-; RV64-i64-NEXT: sub a3, a0, a1
-; RV64-i64-NEXT: vslidedown.vx v0, v0, a2
-; RV64-i64-NEXT: sltu a2, a0, a3
-; RV64-i64-NEXT: addi a2, a2, -1
-; RV64-i64-NEXT: and a2, a2, a3
-; RV64-i64-NEXT: vsetvli zero, a2, e32, m4, ta, ma
-; RV64-i64-NEXT: vfwcvt.x.f.v v16, v12, v0.t
-; RV64-i64-NEXT: bltu a0, a1, .LBB4_2
-; RV64-i64-NEXT: # %bb.1:
-; RV64-i64-NEXT: mv a0, a1
-; RV64-i64-NEXT: .LBB4_2:
-; RV64-i64-NEXT: vmv1r.v v0, v24
-; RV64-i64-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; RV64-i64-NEXT: vfwcvt.x.f.v v24, v8, v0.t
+; RV64-i64-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; RV64-i64-NEXT: vfwcvt.x.f.v v24, v8
+; RV64-i64-NEXT: vfwcvt.x.f.v v16, v12
; RV64-i64-NEXT: vmv8r.v v8, v24
; RV64-i64-NEXT: ret
%a = call <vscale x 16 x iXLen> @llvm.vp.lrint.nxv16iXLen.nxv16f32(<vscale x 16 x float> %x, <vscale x 16 x i1> %m, i32 %evl)
@@ -140,22 +125,22 @@ define <vscale x 16 x iXLen> @lrint_nxv16f32(<vscale x 16 x float> %x, <vscale x
define <vscale x 1 x iXLen> @lrint_nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_nxv1f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV32-NEXT: vfncvt.x.f.w v9, v8, v0.t
+; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; RV32-NEXT: vfncvt.x.f.w v9, v8
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_nxv1f64:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; RV64-i32-NEXT: vfncvt.x.f.w v9, v8, v0.t
+; RV64-i32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; RV64-i32-NEXT: vfncvt.x.f.w v9, v8
; RV64-i32-NEXT: vmv1r.v v8, v9
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_nxv1f64:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV64-i64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i64-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; RV64-i64-NEXT: vfcvt.x.f.v v8, v8
; RV64-i64-NEXT: ret
%a = call <vscale x 1 x iXLen> @llvm.vp.lrint.nxv1iXLen.nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x iXLen> %a
@@ -164,22 +149,22 @@ define <vscale x 1 x iXLen> @lrint_nxv1f64(<vscale x 1 x double> %x, <vscale x 1
define <vscale x 2 x iXLen> @lrint_nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_nxv2f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; RV32-NEXT: vfncvt.x.f.w v10, v8, v0.t
+; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; RV32-NEXT: vfncvt.x.f.w v10, v8
; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_nxv2f64:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; RV64-i32-NEXT: vfncvt.x.f.w v10, v8, v0.t
+; RV64-i32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; RV64-i32-NEXT: vfncvt.x.f.w v10, v8
; RV64-i32-NEXT: vmv.v.v v8, v10
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_nxv2f64:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV64-i64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i64-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; RV64-i64-NEXT: vfcvt.x.f.v v8, v8
; RV64-i64-NEXT: ret
%a = call <vscale x 2 x iXLen> @llvm.vp.lrint.nxv2iXLen.nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x iXLen> %a
@@ -188,22 +173,22 @@ define <vscale x 2 x iXLen> @lrint_nxv2f64(<vscale x 2 x double> %x, <vscale x 2
define <vscale x 4 x iXLen> @lrint_nxv4f64(<vscale x 4 x double> %x, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_nxv4f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; RV32-NEXT: vfncvt.x.f.w v12, v8, v0.t
+; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; RV32-NEXT: vfncvt.x.f.w v12, v8
; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_nxv4f64:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; RV64-i32-NEXT: vfncvt.x.f.w v12, v8, v0.t
+; RV64-i32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; RV64-i32-NEXT: vfncvt.x.f.w v12, v8
; RV64-i32-NEXT: vmv.v.v v8, v12
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_nxv4f64:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV64-i64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; RV64-i64-NEXT: vfcvt.x.f.v v8, v8
; RV64-i64-NEXT: ret
%a = call <vscale x 4 x iXLen> @llvm.vp.lrint.nxv4iXLen.nxv4f64(<vscale x 4 x double> %x, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x iXLen> %a
@@ -212,22 +197,22 @@ define <vscale x 4 x iXLen> @lrint_nxv4f64(<vscale x 4 x double> %x, <vscale x 4
define <vscale x 8 x iXLen> @lrint_nxv8f64(<vscale x 8 x double> %x, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: lrint_nxv8f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; RV32-NEXT: vfncvt.x.f.w v16, v8, v0.t
+; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; RV32-NEXT: vfncvt.x.f.w v16, v8
; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret
;
; RV64-i32-LABEL: lrint_nxv8f64:
; RV64-i32: # %bb.0:
-; RV64-i32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; RV64-i32-NEXT: vfncvt.x.f.w v16, v8, v0.t
+; RV64-i32-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; RV64-i32-NEXT: vfncvt.x.f.w v16, v8
; RV64-i32-NEXT: vmv.v.v v8, v16
; RV64-i32-NEXT: ret
;
; RV64-i64-LABEL: lrint_nxv8f64:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-i64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-i64-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; RV64-i64-NEXT: vfcvt.x.f.v v8, v8
; RV64-i64-NEXT: ret
%a = call <vscale x 8 x iXLen> @llvm.vp.lrint.nxv8iXLen.nxv8f64(<vscale x 8 x double> %x, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x iXLen> %a
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