[llvm] [RISCV][P-ext] Support i32 avgfloors/avgflooru on RV32. (PR #189736)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/189736.diff


3 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+6) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+4) 
- (modified) llvm/test/CodeGen/RISCV/rv32p.ll (+50) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 3a8d9270fdd10..a9dd98bd99566 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -499,6 +499,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::SSHLSAT, MVT::i32, Legal);
   }
 
+  if (Subtarget.hasStdExtP() && !Subtarget.is64Bit()) {
+    // FIXME: Support i32 on RV64+P by inserting into a v2i32 vector, doing
+    // paadd.w, paaddu.w and extracting.
+    setOperationAction({ISD::AVGFLOORS, ISD::AVGFLOORU}, MVT::i32, Legal);
+  }
+
   if (Subtarget.hasStdExtZbc() || Subtarget.hasStdExtZbkc())
     setOperationAction({ISD::CLMUL, ISD::CLMULH}, XLenVT, Legal);
   if (Subtarget.hasStdExtZbc())
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index f347e407a8a34..1b6db4910e308 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1931,6 +1931,10 @@ let Predicates = [HasStdExtP, IsRV32] in {
   def : PatGprGpr<sshlsat, SSHA>;
   def : PatGprUimmLog2XLen<sshlsat, SSLAI>;
 
+  // 32-bit averaging patterns
+  def : PatGprGpr<avgfloors, AADD, i32>;
+  def : PatGprGpr<avgflooru, AADDU, i32>;
+
   // Narrowing shift patterns (NSRL/NSRA)
   // Immediate shift amount patterns
   def : Pat<(riscv_nsrl GPR:$lo, GPR:$hi, uimm6:$shamt),
diff --git a/llvm/test/CodeGen/RISCV/rv32p.ll b/llvm/test/CodeGen/RISCV/rv32p.ll
index 598f105c91561..374b1bb49b829 100644
--- a/llvm/test/CodeGen/RISCV/rv32p.ll
+++ b/llvm/test/CodeGen/RISCV/rv32p.ll
@@ -747,6 +747,56 @@ define i32 @usub_i32(i32 %x, i32 %y) {
   ret i32 %a
 }
 
+define i32 @aadd_i32(i32 %a, i32 %b) {
+; CHECK-LABEL: aadd_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    aadd a0, a0, a1
+; CHECK-NEXT:    ret
+  %ext.a = sext i32 %a to i64
+  %ext.b = sext i32 %b to i64
+  %add = add i64 %ext.a, %ext.b
+  %shift = ashr i64 %add, 1
+  %res = trunc i64 %shift to i32
+  ret i32 %res
+}
+
+define i32 @aadd2_i32(i32 %a, i32 %b) {
+; CHECK-LABEL: aadd2_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    aadd a0, a0, a1
+; CHECK-NEXT:    ret
+  %and = and i32 %a, %b
+  %xor = xor i32 %a, %b
+  %shift = ashr i32 %xor, 1
+  %res = add i32 %and, %shift
+  ret i32 %res
+}
+
+define i32 @aaddu_i32(i32 %a, i32 %b) {
+; CHECK-LABEL: aaddu_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    aaddu a0, a0, a1
+; CHECK-NEXT:    ret
+  %ext.a = zext i32 %a to i64
+  %ext.b = zext i32 %b to i64
+  %add = add i64 %ext.a, %ext.b
+  %shift = lshr i64 %add, 1
+  %res = trunc i64 %shift to i32
+  ret i32 %res
+}
+
+define i32 @aaddu2_i32(i32 %a, i32 %b) {
+; CHECK-LABEL: aaddu2_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    aaddu a0, a0, a1
+; CHECK-NEXT:    ret
+  %and = and i32 %a, %b
+  %xor = xor i32 %a, %b
+  %shift = lshr i32 %xor, 1
+  %res = add i32 %and, %shift
+  ret i32 %res
+}
+
 define i64 @wmul_i32(i32 %x, i32 %y) {
 ; CHECK-LABEL: wmul_i32:
 ; CHECK:       # %bb.0:

``````````

</details>


https://github.com/llvm/llvm-project/pull/189736