[llvm] [AMDGPU] Add v2i32 and/or patterns for VOP3 AND_OR and OR3 operations (PR #188375)

[Matt Arsenault via llvm-commits]

================
@@ -120,3 +120,153 @@ define amdgpu_ps float @or3_vgpr_const(i32 %a, i32 %b) {
   %bc = bitcast i32 %result to float
   ret float %bc
 }
+
+define <2 x i32> @or3_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+; VI-LABEL: or3_v2i32:
+; VI:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_or_b32_e32 v0, v0, v2
+; VI-DAG:    v_or_b32_e32 v1, v1, v3
+; VI-DAG:    v_or_b32_e32 v0, v0, v4
+; VI-DAG:    v_or_b32_e32 v1, v1, v5
+;
+; GFX9-LABEL: or3_v2i32:
+; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:     v_or3_b32 v0, v0, v2, v4
+; GFX9-DAG:     v_or3_b32 v1, v1, v3, v5
+;
+; GFX10-LABEL: or3_v2i32:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_or3_b32 v0, v0, v2, v4
+; GFX10-DAG:     v_or3_b32 v1, v1, v3, v5
+  %x = or <2 x i32> %a, %b
+  %result = or <2 x i32> %x, %c
+  ret <2 x i32> %result
+}
+
+; ThreeOp instruction variant not used due to Constant Bus Limitations
+define <2 x i32> @or3_v2i32_b(<2 x i32> inreg %a, <2 x i32> %b, <2 x i32> inreg %c) {
+; VI-LABEL: or3_v2i32_b:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_or_b32_e32 v0, s16, v0
+; VI-DAG:    v_or_b32_e32 v1, s17, v1
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, s18, v0
+; VI-DAG:    v_or_b32_e32 v1, s19, v1
+;
+; GFX9-LABEL: or3_v2i32_b:
+; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:    v_or_b32_e32 v0, s16, v0
+; GFX9-DAG:    v_or_b32_e32 v1, s17, v1
+; GFX9-CHECK-NOT: {{.}}
+; GFX9-DAG:    v_or_b32_e32 v0, s18, v0
+; GFX9-DAG:    v_or_b32_e32 v1, s19, v1
+;
+; GFX10-LABEL: or3_v2i32_b:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_or3_b32 v0, s{{[0-9]+}}, v0, s{{[0-9]+}}
+; GFX10-DAG:     v_or3_b32 v1, s{{[0-9]+}}, v1, s{{[0-9]+}}
+  %x = or <2 x i32> %a, %b
+  %result = or <2 x i32> %x, %c
+  ret <2 x i32> %result
+}
+
+define <2 x i32> @or3_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) {
+; VI-LABEL: or3_v2i32_ab:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_or_b32_e32 v0, v0, v2
+; VI-DAG:    v_or_b32_e32 v1, v1, v3
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, s16, v0
+; VI-DAG:    v_or_b32_e32 v1, s17, v1
+;
+; GFX9-LABEL: or3_v2i32_ab:
+; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:     v_or3_b32 v0, v0, v2, s16
+; GFX9-DAG:     v_or3_b32 v1, v1, v3, s17
+;
+; GFX10-LABEL: or3_v2i32_ab:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_or3_b32 v0, v0, v2, s{{[0-9]+}}
+; GFX10-DAG:     v_or3_b32 v1, v1, v3, s{{[0-9]+}}
+  %x = or <2 x i32> %a, %b
+  %result = or <2 x i32> %x, %c
+  ret <2 x i32> %result
+}
+
+define <2 x i32> @or3_v2i32_const(<2 x i32> %a, <2 x i32> %b) {
+; VI-LABEL: or3_v2i32_const:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_or_b32_e32 v0, 4, v0
+; VI-DAG:    v_or_b32_e32 v1, 16, v1
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, v0, v2
+; VI-DAG:    v_or_b32_e32 v1, v1, v3
+;
+; GFX9-LABEL: or3_v2i32_const:
+; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:    v_or3_b32 v0, v0, v2, 4
+; GFX9-DAG:    v_or3_b32 v1, v1, v3, 16
+;
+; GFX10-LABEL: or3_v2i32_const:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_or3_b32 v0, v0, v2, 4
+; GFX10-DAG:     v_or3_b32 v1, v1, v3, 16
+  %x = or <2 x i32> %a, <i32 4, i32 16>
+  %result = or <2 x i32> %x, %b
+  ret <2 x i32> %result
+}
+
+define <2 x i32> @or3_v2i32_inline_const(<2 x i32> %a, <2 x i32> %b) {
+; VI-LABEL: or3_v2i32_inline_const:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_or_b32_e32 v0, 0x808, v0
+; VI-DAG:    v_or_b32_e32 v1, 0x809, v1
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, v0, v2
+; VI-DAG:    v_or_b32_e32 v1, v1, v3
+;
+; GFX9-LABEL: or3_v2i32_inline_const:
+; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_movk_i32 s4, 0x809
+; GFX9-NEXT:    v_or3_b32 v1, v1, v3, s4
+; GFX9-NEXT:    s_movk_i32 s4, 0x808
+; GFX9-NEXT:    v_or3_b32 v0, v0, v2, s4
+;
+; GFX10-LABEL: or3_v2i32_inline_const:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_or3_b32 v0, v0, v2, 0x808
+; GFX10-DAG:     v_or3_b32 v1, v1, v3, 0x809
+  %x = or <2 x i32> %a, <i32 2056, i32 2057>
+  %result = or <2 x i32> %x, %b
+  ret <2 x i32> %result
+}
+
+define <2 x i32> @or3_v2i32_multi_use(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+; VI-LABEL: or3_v2i32_multi_use:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_or_b32_e32 v0, v0, v2
+; VI-DAG:    v_or_b32_e32 v1, v1, v3
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v3, v0, v4
+; VI-DAG:    v_or_b32_e32 v2, v1, v5
+;
+; GFX9-LABEL: or3_v2i32_multi_use:
+; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:    v_or_b32_e32 v0, v0, v2
+; GFX9-DAG:    v_or_b32_e32 v1, v1, v3
+; GFX9-CHECK-NOT: {{.}}
+; GFX9-DAG:    v_or_b32_e32 v{{[0-9]+}}, v0, v4
+; GFX9-DAG:    v_or_b32_e32 v{{[0-9]+}}, v1, v5
+;
+; GFX10-LABEL: or3_v2i32_multi_use:
+; GFX10:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:    v_or_b32_e32 v0, v0, v2
+; GFX10-DAG:    v_or_b32_e32 v1, v1, v3
+; GFX10-CHECK-NOT: {{.}}
+; GFX10-DAG:    v_or_b32_e32 v{{[0-9]+}}, v0, v4
+; GFX10-DAG:    v_or_b32_e32 v{{[0-9]+}}, v1, v5
+  %x = or <2 x i32> %a, %b
+  %y = or <2 x i32> %x, %c
+  %result = add <2 x i32> %x, %y
+  ret <2 x i32> %result
+}
----------------
arsenm wrote:

Same here 

https://github.com/llvm/llvm-project/pull/188375