[llvm] [RISCV] Add RISCVISD::USATI/SATI to computeKnownBitsForTargetNode/ComputeNumSignBitsForTargetNode. (PR #189702)
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llvm-commits at lists.llvm.org
Tue Mar 31 09:09:31 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
Stacked on #<!-- -->189532
---
Patch is 20.29 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/189702.diff
5 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+64-4)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+3)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+20)
- (modified) llvm/test/CodeGen/RISCV/rv32p.ll (+146)
- (modified) llvm/test/CodeGen/RISCV/rv64p.ll (+317-1)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 6a77797918b09..b748da96090d9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -538,7 +538,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::FROUNDEVEN, ISD::FCANONICALIZE};
if (Subtarget.hasStdExtP()) {
- setTargetDAGCombine(ISD::TRUNCATE);
static const MVT RV32VTs[] = {MVT::v2i16, MVT::v4i8};
static const MVT RV64VTs[] = {MVT::v2i32, MVT::v4i16, MVT::v8i8};
ArrayRef<MVT> VTs;
@@ -1894,10 +1893,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
// Allow scalar min/max to be combined with vector reductions.
if (Subtarget.hasVInstructions())
- setTargetDAGCombine({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN});
+ setTargetDAGCombine({ISD::UMAX, ISD::UMIN});
+ if (Subtarget.hasVInstructions() || Subtarget.hasStdExtP())
+ setTargetDAGCombine({ISD::SMAX, ISD::SMIN});
if ((Subtarget.hasStdExtZbs() && Subtarget.is64Bit()) ||
- Subtarget.hasVInstructions())
+ Subtarget.hasVInstructions() || Subtarget.hasStdExtP())
setTargetDAGCombine(ISD::TRUNCATE);
if (Subtarget.hasStdExtZbkb())
@@ -21455,6 +21456,53 @@ static SDValue performSHLCombine(SDNode *N,
Passthru, Mask, VL);
}
+static SDValue combineMinMaxToSat(SDNode *N,
+ TargetLowering::DAGCombinerInfo &DCI,
+ const RISCVSubtarget &Subtarget) {
+ if (!DCI.isAfterLegalizeDAG())
+ return SDValue();
+
+ if (!Subtarget.hasStdExtP())
+ return SDValue();
+
+ EVT VT = N->getValueType(0);
+
+ if (VT != Subtarget.getXLenVT())
+ return SDValue();
+
+ SDValue N0 = N->getOperand(0);
+
+ if ((N0.getOpcode() != ISD::SMIN && N0.getOpcode() != ISD::SMAX) ||
+ !isa<ConstantSDNode>(N->getOperand(1)) ||
+ !isa<ConstantSDNode>(N->getOperand(1)))
+ return SDValue();
+
+ SDValue Min = SDValue(N, 0);
+ SDValue Max = N0;
+ SDValue Input = N0.getOperand(0);
+ if (Min.getOpcode() == ISD::SMAX)
+ std::swap(Min, Max);
+
+ APInt MinC = Min.getConstantOperandAPInt(1);
+ APInt MaxC = Max.getConstantOperandAPInt(1);
+
+ if (Min.getOpcode() != ISD::SMIN || Max.getOpcode() != ISD::SMAX ||
+ !(MinC + 1).isPowerOf2())
+ return SDValue();
+
+ SelectionDAG &DAG = DCI.DAG;
+
+ SDLoc DL(N);
+ if (MinC == ~MaxC)
+ return DAG.getNode(RISCVISD::SATI, DL, VT, Input,
+ DAG.getTargetConstant(MinC.countr_one(), DL, VT));
+ if (MaxC == 0)
+ return DAG.getNode(RISCVISD::USATI, DL, VT, Input,
+ DAG.getTargetConstant(MinC.countr_one(), DL, VT));
+
+ return SDValue();
+}
+
SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
@@ -21816,11 +21864,14 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return SDValue();
return DAG.getNode(RISCVISD::FSGNJX, DL, VT, N1, N0->getOperand(1));
}
- case ISD::FADD:
case ISD::UMAX:
case ISD::UMIN:
case ISD::SMAX:
case ISD::SMIN:
+ if (SDValue V = combineMinMaxToSat(N, DCI, Subtarget))
+ return V;
+ [[fallthrough]];
+ case ISD::FADD:
case ISD::FMAXNUM:
case ISD::FMINNUM: {
if (SDValue V = combineBinOpToReduce(N, DAG, Subtarget))
@@ -23269,6 +23320,11 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
Known.One = computeGREVOrGORC(Known.One.getZExtValue(), 7, IsGORC);
break;
}
+ case RISCVISD::USATI: {
+ unsigned Width = Op.getConstantOperandVal(1);
+ Known.Zero.setBitsFrom(Width);
+ break;
+ }
case RISCVISD::READ_VLENB: {
// We can use the minimum and maximum VLEN values to bound VLENB. We
// know VLEN must be a power of two.
@@ -23370,6 +23426,10 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
case RISCVISD::STRICT_FCVT_WU_RV64:
// TODO: As the result is sign-extended, this is conservatively correct.
return 33;
+ case RISCVISD::SATI: {
+ unsigned Width = Op.getConstantOperandVal(1);
+ return Op.getScalarValueSizeInBits() - Width;
+ }
case RISCVISD::VMV_X_S: {
// The number of sign bits of the scalar result is computed by obtaining the
// element type of the input vector operand, subtracting its width from the
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 089683a43f800..e4197839e36f6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3043,6 +3043,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_UIMM5_PLUS1:
Ok = Imm >= 1 && Imm <= 32;
break;
+ case RISCVOp::OPERAND_UIMM6_PLUS1:
+ Ok = Imm >= 1 && Imm <= 64;
+ break;
case RISCVOp::OPERAND_UIMM8_GE32:
Ok = isUInt<8>(Imm) && Imm >= 32;
break;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 5ca1fc637e9c0..5185974065501 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1750,6 +1750,10 @@ def riscv_psrl : RVSDNode<"PSRL", STD_RISCVPackedShift>;
def riscv_psra : RVSDNode<"PSRA", STD_RISCVPackedShift>;
def riscv_psslai : RVSDNode<"PSSLAI", STD_RISCVPackedShift>;
+// The immediate for these is the number of trailing ones in the max value.
+def riscv_sati : RVSDNode<"SATI", SDTIntBinOp>;
+def riscv_usati : RVSDNode<"USATI", SDTIntBinOp>;
+
// Bitwise merge: res = (~op0 & op1) | (op0 & op2)
def SDT_RISCVMERGE : SDTypeProfile<1, 3, [SDTCisInt<0>,
SDTCisSameAs<0, 1>,
@@ -1757,6 +1761,12 @@ def SDT_RISCVMERGE : SDTypeProfile<1, 3, [SDTCisInt<0>,
SDTCisSameAs<0, 3>]>;
def riscv_merge : RVSDNode<"MERGE", SDT_RISCVMERGE>;
+// Add one to the immediate. Used by RISCVISD::SATI.
+def IncImm : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(N->getZExtValue() + 1, SDLoc(N),
+ N->getValueType(0));
+}]>;
+
let Predicates = [HasStdExtP] in {
def : PatGpr<abs, ABS>;
@@ -1924,6 +1934,11 @@ let Predicates = [HasStdExtP] in {
let Predicates = [HasStdExtP, IsRV32] in {
def : PatGpr<bitreverse, REV_RV32>;
+ def : Pat<(XLenVT (riscv_sati GPR:$rs1, timm:$imm)),
+ (SATI_RV32 GPR:$rs1, (IncImm timm:$imm))>;
+ def : Pat<(XLenVT (riscv_usati GPR:$rs1, timm:$imm)),
+ (USATI_RV32 GPR:$rs1, timm:$imm)>;
+
def : PatGprGpr<saddsat, SADD>;
def : PatGprGpr<ssubsat, SSUB>;
def : PatGprGpr<uaddsat, SADDU>;
@@ -1976,6 +1991,11 @@ let Predicates = [HasStdExtP, IsRV64] in {
def : PatGpr<bitreverse, REV_RV64>;
+ def : Pat<(XLenVT (riscv_sati GPR:$rs1, timm:$imm)),
+ (SATI_RV64 GPR:$rs1, (IncImm timm:$imm))>;
+ def : Pat<(XLenVT (riscv_usati GPR:$rs1, timm:$imm)),
+ (USATI_RV64 GPR:$rs1, timm:$imm)>;
+
// Match a pattern of 2 bytes being inserted into bits [31:16], with bits
// bits [15:0] coming from a zero extended value, and bits [63:32] being
// ignored. We can use ppaire.h with ppaire.b for bits [31:16]. If bits [15:0]
diff --git a/llvm/test/CodeGen/RISCV/rv32p.ll b/llvm/test/CodeGen/RISCV/rv32p.ll
index 598f105c91561..b7c2b8bf01b0f 100644
--- a/llvm/test/CodeGen/RISCV/rv32p.ll
+++ b/llvm/test/CodeGen/RISCV/rv32p.ll
@@ -1274,3 +1274,149 @@ entry:
store i32 %val, ptr %res
ret i1 %obit
}
+
+define i32 @mm_sati_8_i32(i32 %x) {
+; CHECK-LABEL: mm_sati_8_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sati a0, a0, 8
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smin.i32(i32 %x, i32 127)
+ %1 = call i32 @llvm.smax.i32(i32 %0, i32 -128)
+ ret i32 %1
+}
+
+define i32 @mm_sati_16_i32(i32 %x) {
+; CHECK-LABEL: mm_sati_16_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sati a0, a0, 16
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smax.i32(i32 %x, i32 -32768)
+ %1 = call i32 @llvm.smin.i32(i32 %0, i32 32767)
+ ret i32 %1
+}
+
+define i32 @mm_sati_24_i32(i32 %x) {
+; CHECK-LABEL: mm_sati_24_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sati a0, a0, 24
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smin.i32(i32 %x, i32 8388607)
+ %1 = call i32 @llvm.smax.i32(i32 %0, i32 -8388608)
+ ret i32 %1
+}
+
+define i32 @mm_sati_32_i32(i32 %x) {
+; CHECK-LABEL: mm_sati_32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smax.i32(i32 %x, i32 -2147483648)
+ %1 = call i32 @llvm.smin.i32(i32 %0, i32 2147483647)
+ ret i32 %1
+}
+
+define i32 @mm_sati_1_i32(i32 %x) {
+; CHECK-LABEL: mm_sati_1_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sati a0, a0, 1
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smin.i32(i32 %x, i32 0)
+ %1 = call i32 @llvm.smax.i32(i32 %0, i32 -1)
+ ret i32 %1
+}
+
+define i32 @mm_sati_minallones_i32(i32 %x) {
+; CHECK-LABEL: mm_sati_minallones_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smin.i32(i32 %x, i32 -1)
+ %1 = call i32 @llvm.smax.i32(i32 %0, i32 0)
+ ret i32 %1
+}
+
+define i32 @mm_sati_minallones2_i32(i32 %x) {
+; CHECK-LABEL: mm_sati_minallones2_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smax.i32(i32 %x, i32 0)
+ %1 = call i32 @llvm.smin.i32(i32 %0, i32 -1)
+ ret i32 %1
+}
+
+define i32 @mm_usati_8_i32(i32 %x) {
+; CHECK-LABEL: mm_usati_8_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: usati a0, a0, 8
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smin.i32(i32 %x, i32 255)
+ %1 = call i32 @llvm.smax.i32(i32 %0, i32 0)
+ ret i32 %1
+}
+
+define i32 @mm_usati_16_i32(i32 %x) {
+; CHECK-LABEL: mm_usati_16_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: usati a0, a0, 16
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smax.i32(i32 %x, i32 0)
+ %1 = call i32 @llvm.smin.i32(i32 %0, i32 65535)
+ ret i32 %1
+}
+
+define i32 @mm_usati_1_i32(i32 %x) {
+; CHECK-LABEL: mm_usati_1_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: usati a0, a0, 1
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smax.i32(i32 %x, i32 0)
+ %1 = call i32 @llvm.smin.i32(i32 %0, i32 1)
+ ret i32 %1
+}
+
+define i32 @mm_usati_31_i32(i32 %x) {
+; CHECK-LABEL: mm_usati_31_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: max a0, a0, zero
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smin.i32(i32 %x, i32 2147483647)
+ %1 = call i32 @llvm.smax.i32(i32 %0, i32 0)
+ ret i32 %1
+}
+
+define i32 @mm_usati_32_i32(i32 %x) {
+; CHECK-LABEL: mm_usati_32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smax.i32(i32 %x, i32 0)
+ %1 = call i32 @llvm.smin.i32(i32 %0, i32 4294967295)
+ ret i32 %1
+}
+
+; Test that we select pack.
+define i32 @mm_usati_32_knownbits_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: mm_usati_32_knownbits_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: usati a0, a0, 16
+; CHECK-NEXT: pack a0, a0, a1
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smax.i32(i32 %x, i32 0)
+ %1 = call i32 @llvm.smin.i32(i32 %0, i32 65535)
+ %2 = shl i32 %y, 16
+ %3 = or i32 %1, %2
+ ret i32 %3
+}
diff --git a/llvm/test/CodeGen/RISCV/rv64p.ll b/llvm/test/CodeGen/RISCV/rv64p.ll
index d1165aa3afa0f..1d626611b736a 100644
--- a/llvm/test/CodeGen/RISCV/rv64p.ll
+++ b/llvm/test/CodeGen/RISCV/rv64p.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+zbb -verify-machineinstrs \
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+zbb,+m -verify-machineinstrs \
; RUN: < %s | FileCheck %s
define i32 @abs_i32(i32 %x) {
@@ -715,3 +715,319 @@ define i64 @mvmn_xor_i64(i64 %b, i64 %mask, i64 %a) nounwind {
%xor2 = xor i64 %and, %a
ret i64 %xor2
}
+
+define signext i32 @mm_sati_8_i32(i32 signext %x) {
+; CHECK-LABEL: mm_sati_8_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sati a0, a0, 8
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smin.i32(i32 %x, i32 127)
+ %1 = call i32 @llvm.smax.i32(i32 %0, i32 -128)
+ ret i32 %1
+}
+
+define signext i32 @mm_sati_16_i32(i32 signext %x) {
+; CHECK-LABEL: mm_sati_16_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sati a0, a0, 16
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smax.i32(i32 %x, i32 -32768)
+ %1 = call i32 @llvm.smin.i32(i32 %0, i32 32767)
+ ret i32 %1
+}
+
+define signext i32 @mm_sati_24_i32(i32 signext %x) {
+; CHECK-LABEL: mm_sati_24_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sati a0, a0, 24
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smin.i32(i32 %x, i32 8388607)
+ %1 = call i32 @llvm.smax.i32(i32 %0, i32 -8388608)
+ ret i32 %1
+}
+
+define signext i32 @mm_sati_32_i32(i32 signext %x) {
+; CHECK-LABEL: mm_sati_32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smax.i32(i32 %x, i32 -2147483648)
+ %1 = call i32 @llvm.smin.i32(i32 %0, i32 2147483647)
+ ret i32 %1
+}
+
+define signext i32 @mm_sati_1_i32(i32 signext %x) {
+; CHECK-LABEL: mm_sati_1_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sati a0, a0, 1
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smin.i32(i32 %x, i32 0)
+ %1 = call i32 @llvm.smax.i32(i32 %0, i32 -1)
+ ret i32 %1
+}
+
+define signext i32 @mm_sati_minallones_i32(i32 signext %x) {
+; CHECK-LABEL: mm_sati_minallones_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smin.i32(i32 %x, i32 -1)
+ %1 = call i32 @llvm.smax.i32(i32 %0, i32 0)
+ ret i32 %1
+}
+
+define signext i32 @mm_sati_minallones2_i32(i32 signext %x) {
+; CHECK-LABEL: mm_sati_minallones2_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smax.i32(i32 %x, i32 0)
+ %1 = call i32 @llvm.smin.i32(i32 %0, i32 -1)
+ ret i32 %1
+}
+
+define signext i32 @mm_usati_8_i32(i32 signext %x) {
+; CHECK-LABEL: mm_usati_8_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: usati a0, a0, 8
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smin.i32(i32 %x, i32 255)
+ %1 = call i32 @llvm.smax.i32(i32 %0, i32 0)
+ ret i32 %1
+}
+
+define signext i32 @mm_usati_16_i32(i32 signext %x) {
+; CHECK-LABEL: mm_usati_16_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: usati a0, a0, 16
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smax.i32(i32 %x, i32 0)
+ %1 = call i32 @llvm.smin.i32(i32 %0, i32 65535)
+ ret i32 %1
+}
+
+define signext i32 @mm_usati_1_i32(i32 signext %x) {
+; CHECK-LABEL: mm_usati_1_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: usati a0, a0, 1
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smax.i32(i32 %x, i32 0)
+ %1 = call i32 @llvm.smin.i32(i32 %0, i32 1)
+ ret i32 %1
+}
+
+define signext i32 @mm_usati_31_i32(i32 signext %x) {
+; CHECK-LABEL: mm_usati_31_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: max a0, a0, zero
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smin.i32(i32 %x, i32 2147483647)
+ %1 = call i32 @llvm.smax.i32(i32 %0, i32 0)
+ ret i32 %1
+}
+
+define signext i32 @mm_usati_32_i32(i32 signext %x) {
+; CHECK-LABEL: mm_usati_32_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: ret
+entry:
+ %0 = call i32 @llvm.smax.i32(i32 %x, i32 0)
+ %1 = call i32 @llvm.smin.i32(i32 %0, i32 4294967295)
+ ret i32 %1
+}
+
+define i64 @mm_sati_8_i64(i64 %x) {
+; CHECK-LABEL: mm_sati_8_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sati a0, a0, 8
+; CHECK-NEXT: ret
+entry:
+ %0 = call i64 @llvm.smin.i64(i64 %x, i64 127)
+ %1 = call i64 @llvm.smax.i64(i64 %0, i64 -128)
+ ret i64 %1
+}
+
+define i64 @mm_sati_16_i64(i64 %x) {
+; CHECK-LABEL: mm_sati_16_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sati a0, a0, 16
+; CHECK-NEXT: ret
+entry:
+ %0 = call i64 @llvm.smax.i64(i64 %x, i64 -32768)
+ %1 = call i64 @llvm.smin.i64(i64 %0, i64 32767)
+ ret i64 %1
+}
+
+define i64 @mm_sati_24_i64(i64 %x) {
+; CHECK-LABEL: mm_sati_24_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sati a0, a0, 24
+; CHECK-NEXT: ret
+entry:
+ %0 = call i64 @llvm.smin.i64(i64 %x, i64 8388607)
+ %1 = call i64 @llvm.smax.i64(i64 %0, i64 -8388608)
+ ret i64 %1
+}
+
+define i64 @mm_sati_32_i64(i64 %x) {
+; CHECK-LABEL: mm_sati_32_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sati a0, a0, 32
+; CHECK-NEXT: ret
+entry:
+ %0 = call i64 @llvm.smax.i64(i64 %x, i64 -2147483648)
+ %1 = call i64 @llvm.smin.i64(i64 %0, i64 2147483647)
+ ret i64 %1
+}
+
+define i64 @mm_sati_1_i64(i64 %x) {
+; CHECK-LABEL: mm_sati_1_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sati a0, a0, 1
+; CHECK-NEXT: ret
+entry:
+ %0 = call i64 @llvm.smin.i64(i64 %x, i64 0)
+ %1 = call i64 @llvm.smax.i64(i64 %0, i64 -1)
+ ret i64 %1
+}
+
+define i64 @mm_sati_minallones_i64(i64 %x) {
+; CHECK-LABEL: mm_sati_minallones_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+entry:
+ %0 = call i64 @llvm.smin.i64(i64 %x, i64 -1)
+ %1 = call i64 @llvm.smax.i64(i64 %0, i64 0)
+ ret i64 %1
+}
+
+define i64 @mm_sati_minallones2_i64(i64 %x) {
+; CHECK-LABEL: mm_sati_minallones2_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: ret
+entry:
+ %0 = call i64 @llvm.smax.i64(i64 %x, i64 0)
+ %1 = call i64 @llvm.smin.i64(i64 %0, i64 -1)
+ ret i64 %1
+}
+
+define i64 @mm_usati_8_i64(i64 %x) {
+; CHECK-LABEL: mm_usati_8_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: usati a0, a0, 8
+; CHECK-NEXT: ret
+entry:
+ %0 = call i64 @llvm.smin.i64(i64 %x, i64 255)
+ %1 = call i64 @llvm.smax.i64(i64 %0, i64 0)
+ ret i64 %1
+}
+
+define i64 @mm_usati_16_i64(i64 %x) {
+; CHECK-LABEL: mm_usati_16_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: usati a0, a0, 16
+; CHECK-NEXT: ret
+entry:
+ %0 = call i64 @llvm.smax.i64(i64 %x, i64 0)
+ %1 = call i64 @llvm.smin.i64(i64 %0, i64 65535)
+ ret i64 %1
+}
+
+define i64 @mm_usati_1_i64(i64 %x) {
+; CHECK-LABEL: mm_usati_1_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: usati a0, a0, 1
+; CHECK-NEXT: ret
+entry:
+ %0 = call i64 @llvm.smax.i64(i64 %x, i64 0)
+ %1 = call i64 @llvm.smin.i64(i64 %0, i64 1)
+ ret i64 %1
+}
+
+define i64 @mm_usati_31_i64(i64 %x) {
+; CHECK-LABEL: mm_usati_31_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: usati a0, a0, 31
+; CHECK-NEXT: ret
+entry:
+ %0 = call i64 @llvm.smin.i64(i64 %x, i64 2147483647)
+ %1 = call i64 @llvm.smax.i64(i64 %0, i64 0)
+ ret i64 %1
+}
+
+define i64 @mm_usati_32_i64(i64 %x) {
+; CHECK-LABEL: mm_usati_32_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: usati a0, a0, 32
+; CHECK-NEXT: ret
+entry:
+ %0 = call i64 @llvm.smax.i64(i64 %x, i64 0)
+ %1 = call i64 @llvm.smin.i64(i64 %0, i64 4294967295)
+ ret i64 %1
+}
+
+define i64 @mm_usati_55_i64(i64 %x) {
+; CHECK-LABEL: mm_usati_55_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: usati a0, a0, 55
+; CHECK-NEXT: ret
+entry:
+ %0 = call i64 @llvm.smax.i64(i64 %x, i64 0)
+ %1 = call i64 @llvm.smin.i64(i64 %0, i64 u0x7FFFFFFFFFFFFF)
+ ret i64 %1
+}
+
+define i64 @mm_usati_64_i64(i64 %x) {
+; CHECK-LABEL: mm_usati_64_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: ret
+entry:
+ %0 = call i64 @llvm.smax.i64(i64 %x, i64 0)
+ %1 = call i64 @llvm.smin.i64(i64 %0, i64 -1)
+ ret i64 %1
+}
+
+; Test that we select remw.
+define signext i32 @mm_sati_32_numsignbits_i64(i64 %x, i32 %y) {
+; CHECK-LABEL: mm_sati_32_numsignbits_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sati a0, a0, 32
+; CHECK-NEXT: remw a0, a0, a1
+; CHECK-NEXT: ret
+entry:
+ %0 = call i64 @llvm.smax.i64(i64 %x, i64 -2147483648)
+ %1 = call i64 @llvm.smin.i64(i64 %0, i64 2147483647)
+ %2 = sext i32 %y to i64
+ %3 = srem i64 %1, %2
+ %4 = trunc i64 %3 to i32
+ ret i32 %4
+}
+
+; Test that we select pack.
+define i64 @mm_usati_32_knownbits_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: mm_usati_32_knownbits_i64:
+;...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/189702
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