[llvm] [AMDGPU] Add hint for MFMA Dst and OpC (PR #185218)

[Juan Manuel Martinez Caamaño via llvm-commits]

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@@ -245,6 +246,64 @@ bool GCNPreRAOptimizationsImpl::run(MachineFunction &MF) {
   TRI = ST.getRegisterInfo();
 
   bool Changed = false;
+  if (ST.hasMAIInsts()) {
+    EquivalenceClasses<Register> MFMAHints;
+    for (const MachineBasicBlock &MBB : MF) {
+      for (const MachineInstr &MI : MBB) {
+        if (!SIInstrInfo::isMFMA(MI))
+          continue;
+        const MachineOperand *DstMO =
+            TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
+        const MachineOperand *Src2MO =
+            TII->getNamedOperand(MI, AMDGPU::OpName::src2);
+        if (!DstMO || !Src2MO || !DstMO->isReg() || !Src2MO->isReg())
+          continue;
+        Register Dst = DstMO->getReg();
+        Register Src2 = Src2MO->getReg();
+        if (!Dst.isVirtual() || !Src2.isVirtual())
+          continue;
+        LLVM_DEBUG(dbgs() << "Setting hint for "; MI.dump());
+        LLVM_DEBUG(dbgs() << " Dst: "; DstMO->dump(); dbgs() << " Src2: ";
+                   Src2MO->dump());
+        MFMAHints.unionSets(Dst, Src2);
+      }
+    }
+
+    auto CheckAllCompatibleRC =
+        [&](const EquivalenceClasses<llvm::Register>::ECValue *I) -> bool {
+      for (Register A : MFMAHints.members(*I)) {
+        assert(A.isVirtual());
+        for (Register B : MFMAHints.members(*I)) {
+          assert(B.isVirtual());
+          if (A == B)
+            continue;
+
+          const TargetRegisterClass *ARC = MRI->getRegClass(A);
+          const TargetRegisterClass *BRC = MRI->getRegClass(B);
+          if (!TRI->getCommonSubClass(ARC, BRC))
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jmmartinez wrote:

Just passing by.

Is `getCommonSubClass(A,B) == getCommonSubClass(B,A)` ? If that is the case, is it possible to iterate only once over each `(A,B)` pair?

Same for the `addRegAllocationHint` loop nest below.

https://github.com/llvm/llvm-project/pull/185218