[llvm] AMDGPU: Fix generation for dot2 VOPD with sgpr inputs (PR #189667)
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 31 06:43:26 PDT 2026
https://github.com/petar-avramovic created https://github.com/llvm/llvm-project/pull/189667
There was no check for sgpr operand in src1 operand.
>From 9bed667698828d64a32a3af8f5e477ba9c22634c Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Tue, 31 Mar 2026 15:37:28 +0200
Subject: [PATCH] AMDGPU: Fix generation for dot2 VOPD with sgpr inputs
There was no check for sgpr operand in src1 operand.
---
llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp | 7 +-
.../AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll | 109 +++++++++
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll | 212 ++++++++++++++++++
3 files changed, 327 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
index 4659dcd1a78cb..8e9cb739f944d 100644
--- a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
@@ -49,7 +49,12 @@ static bool canMapVOP3PToVOPD(const MachineInstr &MI) {
if (MI.getOperand(Src1ModsIdx).getImm() != SISrcMods::OP_SEL_1)
return false;
int16_t Src1Idx = getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
- if (!MI.getOperand(Src1Idx).isReg())
+ const MachineFunction *MF = MI.getMF();
+ const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
+ const SIRegisterInfo *TRI = ST.getRegisterInfo();
+ const MachineRegisterInfo &MRI = MF->getRegInfo();
+ if (!MI.getOperand(Src1Idx).isReg() ||
+ !TRI->isVGPR(MRI, MI.getOperand(Src1Idx).getReg()))
return false;
int16_t Src2ModsIdx = getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers);
if (MI.getOperand(Src2ModsIdx).getImm() != SISrcMods::OP_SEL_1)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
index 9e5a8c672deb3..fb470c7596a96 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
@@ -403,6 +403,115 @@ define float @v_fdot2_f32_bf16_dual(<2 x bfloat> %a, <2 x bfloat> %b, float %c,
ret float %r
}
+define float @v_fdot2_f32_bf16_dual_sgpr_src0_x(<2 x bfloat> inreg %a, <2 x bfloat> %b, float %c, <2 x bfloat> %d, <2 x bfloat> %e, float %f) {
+; GFX950-LABEL: v_fdot2_f32_bf16_dual_sgpr_src0_x:
+; GFX950: ; %bb.0:
+; GFX950: v_dot2c_f32_bf16_e32 v1, s0, v0
+; GFX950: v_dot2c_f32_bf16_e32 v4, v2, v3
+; GFX950: v_add_f32_e32 v0, v1, v4
+;
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_dual_sgpr_src0_x:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_dual_dot2acc_f32_bf16 v1, s0, v0 :: v_dual_dot2acc_f32_bf16 v4, v2, v3
+; GFX11PLUS: v_add_f32_e32 v0, v1, v4
+ %r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c, i1 false)
+ %r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false)
+ %r = fadd float %r0, %r1
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_dual_sgpr_src1_x(<2 x bfloat> %a, <2 x bfloat> inreg %b, float %c, <2 x bfloat> %d, <2 x bfloat> %e, float %f) {
+; GFX950-LABEL: v_fdot2_f32_bf16_dual_sgpr_src1_x:
+; GFX950: ; %bb.0:
+; GFX950: v_dot2c_f32_bf16_e32 v1, s0, v0
+; GFX950: v_dot2c_f32_bf16_e32 v4, v2, v3
+; GFX950: v_add_f32_e32 v0, v1, v4
+;
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_dual_sgpr_src1_x:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_dot2_f32_bf16 v1, v0, s0, v1
+; GFX11PLUS: v_dot2_f32_bf16 v4, v2, v3, v4
+; GFX11PLUS: v_add_f32_e32 v0, v1, v4
+ %r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c, i1 false)
+ %r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false)
+ %r = fadd float %r0, %r1
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_dual_sgpr_src2_x(<2 x bfloat> %a, <2 x bfloat> %b, float inreg %c, <2 x bfloat> %d, <2 x bfloat> %e, float %f) {
+; GFX950-LABEL: v_fdot2_f32_bf16_dual_sgpr_src2_x:
+; GFX950: ; %bb.0:
+; GFX950: v_mov_b32_e32 v5, s0
+; GFX950: v_dot2c_f32_bf16_e32 v5, v0, v1
+; GFX950: v_dot2c_f32_bf16_e32 v4, v2, v3
+; GFX950: v_add_f32_e32 v0, v5, v4
+;
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_dual_sgpr_src2_x:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, s0
+; GFX11PLUS: v_dot2_f32_bf16 v4, v2, v3, v4
+; GFX11PLUS: v_add_f32_e32 v0, v0, v4
+ %r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c, i1 false)
+ %r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false)
+ %r = fadd float %r0, %r1
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_dual_sgpr_src0_y(<2 x bfloat> %a, <2 x bfloat> %b, float %c, <2 x bfloat> inreg %d, <2 x bfloat> %e, float %f) {
+; GFX950-LABEL: v_fdot2_f32_bf16_dual_sgpr_src0_y:
+; GFX950: ; %bb.0:
+; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1
+; GFX950: v_dot2c_f32_bf16_e32 v4, s0, v3
+; GFX950: v_add_f32_e32 v0, v2, v4
+;
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_dual_sgpr_src0_y:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_dot2_f32_bf16 v2, v0, v1, v2
+; GFX11PLUS: v_dot2_f32_bf16 v4, s0, v3, v4
+; GFX11PLUS: v_add_f32_e32 v0, v2, v4
+ %r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c, i1 false)
+ %r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false)
+ %r = fadd float %r0, %r1
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_dual_sgpr_src1_y(<2 x bfloat> %a, <2 x bfloat> %b, float %c, <2 x bfloat> %d, <2 x bfloat> inreg %e, float %f) {
+; GFX950-LABEL: v_fdot2_f32_bf16_dual_sgpr_src1_y:
+; GFX950: ; %bb.0:
+; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1
+; GFX950: v_dot2c_f32_bf16_e32 v4, s0, v3
+; GFX950: v_add_f32_e32 v0, v2, v4
+;
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_dual_sgpr_src1_y:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_dot2_f32_bf16 v2, v0, v1, v2
+; GFX11PLUS: v_dot2_f32_bf16 v4, v3, s0, v4
+; GFX11PLUS: v_add_f32_e32 v0, v2, v4
+ %r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c, i1 false)
+ %r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false)
+ %r = fadd float %r0, %r1
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_dual_sgpr_src2_y(<2 x bfloat> %a, <2 x bfloat> %b, float %c, <2 x bfloat> %d, <2 x bfloat> %e, float inreg %f) {
+; GFX950-LABEL: v_fdot2_f32_bf16_dual_sgpr_src2_y:
+; GFX950: ; %bb.0:
+; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1
+; GFX950: v_mov_b32_e32 v0, s0
+; GFX950: v_dot2c_f32_bf16_e32 v0, v3, v4
+; GFX950: v_add_f32_e32 v0, v2, v0
+;
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_dual_sgpr_src2_y:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_dot2_f32_bf16 v2, v0, v1, v2
+; GFX11PLUS: v_dot2_f32_bf16 v0, v3, v4, s0
+; GFX11PLUS: v_add_f32_e32 v0, v2, v0
+ %r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c, i1 false)
+ %r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false)
+ %r = fadd float %r0, %r1
+ ret float %r
+}
+
define float @v_fdot2_f32_bf16_neg_a_dual(<2 x bfloat> %a, <2 x bfloat> %b, float %c, <2 x bfloat> %d, <2 x bfloat> %e, float %f) {
; GFX950-LABEL: v_fdot2_f32_bf16_neg_a_dual:
; GFX950: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
index 73410d8f32ff9..af402c644c92e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
@@ -636,6 +636,218 @@ define float @v_fdot2_dual(<2 x half> %a, <2 x half> %b, float %c, <2 x half> %d
ret float %r
}
+define float @v_fdot2_dual_sgpr_src0_x(<2 x half> inreg %a, <2 x half> %b, float %c, <2 x half> %d, <2 x half> %e, float %f) {
+; GFX906-LABEL: v_fdot2_dual_sgpr_src0_x:
+; GFX906: ; %bb.0:
+; GFX906: v_dot2_f32_f16 v1, s16, v0, v1
+; GFX906: v_dot2_f32_f16 v4, v2, v3, v4
+; GFX906: v_add_f32_e32 v0, v1, v4
+;
+; GFX950-LABEL: v_fdot2_dual_sgpr_src0_x:
+; GFX950: ; %bb.0:
+; GFX950: v_dot2c_f32_f16_e32 v1, s0, v0
+; GFX950: v_dot2c_f32_f16_e32 v4, v2, v3
+; GFX950: v_add_f32_e32 v0, v1, v4
+;
+; GFX10-LABEL: v_fdot2_dual_sgpr_src0_x:
+; GFX10: ; %bb.0:
+; GFX10: v_dot2c_f32_f16 v1, s16, v0
+; GFX10: v_dot2c_f32_f16 v4, v2, v3
+; GFX10: v_add_f32_e32 v0, v1, v4
+;
+; GFX11PLUS-LABEL: v_fdot2_dual_sgpr_src0_x:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_dual_dot2acc_f32_f16 v1, s0, v0 :: v_dual_dot2acc_f32_f16 v4, v2, v3
+; GFX11PLUS: v_add_f32_e32 v0, v1, v4
+ %r0 = call float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %b, float %c, i1 false)
+ %r1 = call float @llvm.amdgcn.fdot2(<2 x half> %d, <2 x half> %e, float %f, i1 false)
+ %r = fadd float %r0, %r1
+ ret float %r
+}
+
+define float @v_fdot2_dual_sgpr_src1_x(<2 x half> %a, <2 x half> inreg %b, float %c, <2 x half> %d, <2 x half> %e, float %f) {
+; GFX906-LABEL: v_fdot2_dual_sgpr_src1_x:
+; GFX906: ; %bb.0:
+; GFX906: v_dot2_f32_f16 v1, v0, s16, v1
+; GFX906: v_dot2_f32_f16 v4, v2, v3, v4
+; GFX906: v_add_f32_e32 v0, v1, v4
+;
+; GFX950-LABEL: v_fdot2_dual_sgpr_src1_x:
+; GFX950: ; %bb.0:
+; GFX950: v_dot2c_f32_f16_e32 v1, s0, v0
+; GFX950: v_dot2c_f32_f16_e32 v4, v2, v3
+; GFX950: v_add_f32_e32 v0, v1, v4
+;
+; GFX10-LABEL: v_fdot2_dual_sgpr_src1_x:
+; GFX10: ; %bb.0:
+; GFX10: v_dot2c_f32_f16 v1, s16, v0
+; GFX10: v_dot2c_f32_f16 v4, v2, v3
+; GFX10: v_add_f32_e32 v0, v1, v4
+;
+; GFX11-LABEL: v_fdot2_dual_sgpr_src1_x:
+; GFX11: ; %bb.0:
+; GFX11: v_dual_dot2acc_f32_f16 v1, s0, v0 :: v_dual_dot2acc_f32_f16 v4, v2, v3
+; GFX11: v_add_f32_e32 v0, v1, v4
+;
+; GFX1170-GFX12-LABEL: v_fdot2_dual_sgpr_src1_x:
+; GFX1170-GFX12: ; %bb.0:
+; GFX1170-GFX12: v_dot2_f32_f16 v1, v0, s0, v1
+; GFX1170-GFX12: v_dot2_f32_f16 v4, v2, v3, v4
+; GFX1170-GFX12: v_add_f32_e32 v0, v1, v4
+ %r0 = call float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %b, float %c, i1 false)
+ %r1 = call float @llvm.amdgcn.fdot2(<2 x half> %d, <2 x half> %e, float %f, i1 false)
+ %r = fadd float %r0, %r1
+ ret float %r
+}
+
+define float @v_fdot2_dual_sgpr_src2_x(<2 x half> %a, <2 x half> %b, float inreg %c, <2 x half> %d, <2 x half> %e, float %f) {
+; GFX906-LABEL: v_fdot2_dual_sgpr_src2_x:
+; GFX906: ; %bb.0:
+; GFX906: v_dot2_f32_f16 v0, v0, v1, s16
+; GFX906: v_dot2_f32_f16 v4, v2, v3, v4
+; GFX906: v_add_f32_e32 v0, v0, v4
+;
+; GFX950-LABEL: v_fdot2_dual_sgpr_src2_x:
+; GFX950: ; %bb.0:
+; GFX950: v_mov_b32_e32 v5, s0
+; GFX950: v_dot2c_f32_f16_e32 v5, v0, v1
+; GFX950: v_dot2c_f32_f16_e32 v4, v2, v3
+; GFX950: v_add_f32_e32 v0, v5, v4
+;
+; GFX10-LABEL: v_fdot2_dual_sgpr_src2_x:
+; GFX10: ; %bb.0:
+; GFX10: v_mov_b32_e32 v5, s16
+; GFX10: v_dot2c_f32_f16 v4, v2, v3
+; GFX10: v_dot2c_f32_f16 v5, v0, v1
+; GFX10: v_add_f32_e32 v0, v5, v4
+;
+; GFX11-LABEL: v_fdot2_dual_sgpr_src2_x:
+; GFX11: ; %bb.0:
+; GFX11: v_dual_mov_b32 v5, s0 :: v_dual_dot2acc_f32_f16 v4, v2, v3
+; GFX11: v_dot2acc_f32_f16 v5, v0, v1
+; GFX11: v_add_f32_e32 v0, v5, v4
+;
+; GFX1170-GFX12-LABEL: v_fdot2_dual_sgpr_src2_x:
+; GFX1170-GFX12: ; %bb.0:
+; GFX1170-GFX12: v_dot2_f32_f16 v0, v0, v1, s0
+; GFX1170-GFX12: v_dot2_f32_f16 v4, v2, v3, v4
+; GFX1170-GFX12: v_add_f32_e32 v0, v0, v4
+ %r0 = call float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %b, float %c, i1 false)
+ %r1 = call float @llvm.amdgcn.fdot2(<2 x half> %d, <2 x half> %e, float %f, i1 false)
+ %r = fadd float %r0, %r1
+ ret float %r
+}
+
+define float @v_fdot2_dual_sgpr_src0_y(<2 x half> %a, <2 x half> %b, float %c, <2 x half> inreg %d, <2 x half> %e, float %f) {
+; GFX906-LABEL: v_fdot2_dual_sgpr_src0_y:
+; GFX906: ; %bb.0:
+; GFX906: v_dot2_f32_f16 v2, v0, v1, v2
+; GFX906: v_dot2_f32_f16 v4, s16, v3, v4
+; GFX906: v_add_f32_e32 v0, v2, v4
+;
+; GFX950-LABEL: v_fdot2_dual_sgpr_src0_y:
+; GFX950: ; %bb.0:
+; GFX950: v_dot2c_f32_f16_e32 v2, v0, v1
+; GFX950: v_dot2c_f32_f16_e32 v4, s0, v3
+; GFX950: v_add_f32_e32 v0, v2, v4
+;
+; GFX10-LABEL: v_fdot2_dual_sgpr_src0_y:
+; GFX10: ; %bb.0:
+; GFX10: v_dot2c_f32_f16 v2, v0, v1
+; GFX10: v_dot2c_f32_f16 v4, s16, v3
+; GFX10: v_add_f32_e32 v0, v2, v4
+;
+; GFX11-LABEL: v_fdot2_dual_sgpr_src0_y:
+; GFX11: ; %bb.0:
+; GFX11: v_dot2acc_f32_f16 v2, v0, v1
+; GFX11: v_dot2acc_f32_f16 v4, s0, v3
+; GFX11: v_add_f32_e32 v0, v2, v4
+;
+; GFX1170-GFX12-LABEL: v_fdot2_dual_sgpr_src0_y:
+; GFX1170-GFX12: ; %bb.0:
+; GFX1170-GFX12: v_dot2_f32_f16 v2, v0, v1, v2
+; GFX1170-GFX12: v_dot2_f32_f16 v4, s0, v3, v4
+; GFX1170-GFX12: v_add_f32_e32 v0, v2, v4
+ %r0 = call float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %b, float %c, i1 false)
+ %r1 = call float @llvm.amdgcn.fdot2(<2 x half> %d, <2 x half> %e, float %f, i1 false)
+ %r = fadd float %r0, %r1
+ ret float %r
+}
+
+define float @v_fdot2_dual_sgpr_src1_y(<2 x half> %a, <2 x half> %b, float %c, <2 x half> %d, <2 x half> inreg %e, float %f) {
+; GFX906-LABEL: v_fdot2_dual_sgpr_src1_y:
+; GFX906: ; %bb.0:
+; GFX906: v_dot2_f32_f16 v2, v0, v1, v2
+; GFX906: v_dot2_f32_f16 v4, v3, s16, v4
+; GFX906: v_add_f32_e32 v0, v2, v4
+;
+; GFX950-LABEL: v_fdot2_dual_sgpr_src1_y:
+; GFX950: ; %bb.0:
+; GFX950: v_dot2c_f32_f16_e32 v2, v0, v1
+; GFX950: v_dot2c_f32_f16_e32 v4, s0, v3
+; GFX950: v_add_f32_e32 v0, v2, v4
+;
+; GFX10-LABEL: v_fdot2_dual_sgpr_src1_y:
+; GFX10: ; %bb.0:
+; GFX10: v_dot2c_f32_f16 v2, v0, v1
+; GFX10: v_dot2c_f32_f16 v4, s16, v3
+; GFX10: v_add_f32_e32 v0, v2, v4
+;
+; GFX11-LABEL: v_fdot2_dual_sgpr_src1_y:
+; GFX11: ; %bb.0:
+; GFX11: v_dot2acc_f32_f16 v2, v0, v1
+; GFX11: v_dot2acc_f32_f16 v4, s0, v3
+; GFX11: v_add_f32_e32 v0, v2, v4
+;
+; GFX1170-GFX12-LABEL: v_fdot2_dual_sgpr_src1_y:
+; GFX1170-GFX12: ; %bb.0:
+; GFX1170-GFX12: v_dot2_f32_f16 v2, v0, v1, v2
+; GFX1170-GFX12: v_dot2_f32_f16 v4, v3, s0, v4
+; GFX1170-GFX12: v_add_f32_e32 v0, v2, v4
+ %r0 = call float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %b, float %c, i1 false)
+ %r1 = call float @llvm.amdgcn.fdot2(<2 x half> %d, <2 x half> %e, float %f, i1 false)
+ %r = fadd float %r0, %r1
+ ret float %r
+}
+
+define float @v_fdot2_dual_sgpr_src2_y(<2 x half> %a, <2 x half> %b, float %c, <2 x half> %d, <2 x half> %e, float inreg %f) {
+; GFX906-LABEL: v_fdot2_dual_sgpr_src2_y:
+; GFX906: ; %bb.0:
+; GFX906: v_dot2_f32_f16 v2, v0, v1, v2
+; GFX906: v_dot2_f32_f16 v0, v3, v4, s16
+; GFX906: v_add_f32_e32 v0, v2, v0
+;
+; GFX950-LABEL: v_fdot2_dual_sgpr_src2_y:
+; GFX950: ; %bb.0:
+; GFX950: v_dot2c_f32_f16_e32 v2, v0, v1
+; GFX950: v_mov_b32_e32 v0, s0
+; GFX950: v_dot2c_f32_f16_e32 v0, v3, v4
+; GFX950: v_add_f32_e32 v0, v2, v0
+;
+; GFX10-LABEL: v_fdot2_dual_sgpr_src2_y:
+; GFX10: ; %bb.0:
+; GFX10: v_mov_b32_e32 v5, s16
+; GFX10: v_dot2c_f32_f16 v2, v0, v1
+; GFX10: v_dot2c_f32_f16 v5, v3, v4
+; GFX10: v_add_f32_e32 v0, v2, v5
+;
+; GFX11-LABEL: v_fdot2_dual_sgpr_src2_y:
+; GFX11: ; %bb.0:
+; GFX11: v_dual_mov_b32 v5, s0 :: v_dual_dot2acc_f32_f16 v2, v0, v1
+; GFX11: v_dot2acc_f32_f16 v5, v3, v4
+; GFX11: v_add_f32_e32 v0, v2, v5
+;
+; GFX1170-GFX12-LABEL: v_fdot2_dual_sgpr_src2_y:
+; GFX1170-GFX12: ; %bb.0:
+; GFX1170-GFX12: v_dot2_f32_f16 v2, v0, v1, v2
+; GFX1170-GFX12: v_dot2_f32_f16 v0, v3, v4, s0
+; GFX1170-GFX12: v_add_f32_e32 v0, v2, v0
+ %r0 = call float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %b, float %c, i1 false)
+ %r1 = call float @llvm.amdgcn.fdot2(<2 x half> %d, <2 x half> %e, float %f, i1 false)
+ %r = fadd float %r0, %r1
+ ret float %r
+}
+
define float @v_fdot2_neg_a_dual(<2 x half> %a, <2 x half> %b, float %c, <2 x half> %d, <2 x half> %e, float %f) {
; GFX906-LABEL: v_fdot2_neg_a_dual:
; GFX906: ; %bb.0:
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