[llvm] 67d4842 - [NFC][AMDGPU] New test for untested case in SILowerSGPRSpills (#189426)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 31 05:12:36 PDT 2026
Author: ambergorzynski
Date: 2026-03-31T13:12:29+01:00
New Revision: 67d4842910b8cb79f31b9041bdf56c206cd768e9
URL: https://github.com/llvm/llvm-project/commit/67d4842910b8cb79f31b9041bdf56c206cd768e9
DIFF: https://github.com/llvm/llvm-project/commit/67d4842910b8cb79f31b9041bdf56c206cd768e9.diff
LOG: [NFC][AMDGPU] New test for untested case in SILowerSGPRSpills (#189426)
[This
case](https://github.com/llvm/llvm-project/blob/f380a878d515024fe02662471e81cd72a8b3eb93/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp#L343-L345)
is not covered by any existing tests (checked using code coverage and by
inserting an `abort` at that line). I propose a new test that tests this
line.
This is demonstrated by showing that it is the only test that fails in
the presence of the `abort`.
Added:
Modified:
llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
index 2de7d86223eb2..1332e33b9f2d1 100644
--- a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
@@ -1,20 +1,86 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s
-# CHECK-LABEL: name: empty_entry_block
-# CHECK: SI_SPILL_S32_TO_VGPR
-# CHECK-NEXT: SI_SPILL_S32_TO_VGPR
-# CHECK-NEXT: SI_SPILL_S32_TO_VGPR
-# CHECK-NEXT: SI_SPILL_S32_TO_VGPR
-# CHECK: SI_RESTORE_S32_FROM_VGPR
-# CHECK-NEXT: SI_RESTORE_S32_FROM_VGPR
-# CHECK-NEXT: SI_RESTORE_S32_FROM_VGPR
-# CHECK-NEXT: SI_RESTORE_S32_FROM_VGPR
---
name: empty_entry_block
body: |
+ ; CHECK-LABEL: name: empty_entry_block
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $sgpr34, $sgpr35, $sgpr36, $sgpr37, $vgpr63
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr34, 0, $vgpr63
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr35, 1, $vgpr63
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr36, 2, $vgpr63
+ ; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr37, 3, $vgpr63
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $vgpr63
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $sgpr36_sgpr37 = S_XOR_B64 renamable $vcc, -1, implicit-def dead $scc
+ ; CHECK-NEXT: $sgpr34_sgpr35 = S_AND_SAVEEXEC_B64 $sgpr36_sgpr37, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; CHECK-NEXT: $sgpr37 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 3
+ ; CHECK-NEXT: $sgpr36 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 2
+ ; CHECK-NEXT: $sgpr35 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 1
+ ; CHECK-NEXT: $sgpr34 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 0
+ ; CHECK-NEXT: S_ENDPGM 0
bb.0:
bb.1:
renamable $sgpr36_sgpr37 = S_XOR_B64 renamable $vcc, -1, implicit-def dead $scc
$sgpr34_sgpr35 = S_AND_SAVEEXEC_B64 $sgpr36_sgpr37, implicit-def $exec, implicit-def $scc, implicit $exec
S_ENDPGM 0
+...
+---
+name: lane-vgpr-spill-ncd
+tracksRegLiveness: true
+
+stack:
+ - { id: 0, type: spill-slot, size: 8, stack-id: sgpr-spill }
+machineFunctionInfo:
+ hasSpilledSGPRs: true
+ stackPtrOffsetReg: '$sgpr32'
+
+body: |
+ ; CHECK-LABEL: name: lane-vgpr-spill-ncd
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: S_BRANCH %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $sgpr6 = SI_RESTORE_S32_FROM_VGPR %0, 0, implicit-def $sgpr6_sgpr7
+ ; CHECK-NEXT: $sgpr7 = SI_RESTORE_S32_FROM_VGPR %0, 1
+ ; CHECK-NEXT: $sgpr4 = S_MOV_B32 32
+ ; CHECK-NEXT: $sgpr4_sgpr5 = S_LSHR_B64 $sgpr6_sgpr7, killed $sgpr4, implicit-def dead $scc
+ ; CHECK-NEXT: $sgpr4 = COPY $sgpr4, implicit killed $sgpr4_sgpr5
+ ; CHECK-NEXT: $sgpr5 = COPY $sgpr6, implicit killed $sgpr6_sgpr7
+ ; CHECK-NEXT: $vgpr0 = COPY killed $sgpr5
+ ; CHECK-NEXT: $vgpr1 = COPY killed $sgpr4
+ ; CHECK-NEXT: SI_RETURN implicit killed $vgpr0, implicit killed $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $sgpr4_sgpr5 = S_MOV_B64 0
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, [[DEF]], implicit-def $sgpr4_sgpr5, implicit $sgpr4_sgpr5
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr5, 1, [[DEF]], implicit killed $sgpr4_sgpr5
+ ; CHECK-NEXT: S_BRANCH %bb.1
+ bb.0:
+ S_BRANCH %bb.2
+
+ bb.1:
+ $sgpr6_sgpr7 = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load (s64) from %stack.0)
+ $sgpr4 = S_MOV_B32 32
+ $sgpr4_sgpr5 = S_LSHR_B64 $sgpr6_sgpr7, killed $sgpr4, implicit-def dead $scc
+ $sgpr4 = COPY $sgpr4, implicit killed $sgpr4_sgpr5
+ $sgpr5 = COPY $sgpr6, implicit killed $sgpr6_sgpr7
+ $vgpr0 = COPY killed $sgpr5
+ $vgpr1 = COPY killed $sgpr4
+ SI_RETURN implicit killed $vgpr0, implicit killed $vgpr1
+
+ bb.2:
+ $sgpr4_sgpr5 = S_MOV_B64 0
+ SI_SPILL_S64_SAVE killed $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s64) into %stack.0)
+ S_BRANCH %bb.1
More information about the llvm-commits
mailing list