[llvm] 63e0ab7 - [RISCV] Explicitly list supported VP intrinsics. NFC (#189547)

[via llvm-commits]

Author: Luke Lau
Date: 2026-03-31T16:55:11+08:00
New Revision: 63e0ab7b4b51db7d93bf247b645c33b63f8ef747

URL: https://github.com/llvm/llvm-project/commit/63e0ab7b4b51db7d93bf247b645c33b63f8ef747
DIFF: https://github.com/llvm/llvm-project/commit/63e0ab7b4b51db7d93bf247b645c33b63f8ef747.diff

LOG: [RISCV] Explicitly list supported VP intrinsics. NFC (#189547)

In preparation for splitting off #179622, list all vp intrinsics in a
list. Future PRs will remove intrinsics from this list when the
corresponding codegen support is removed.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 99d213311ed69..97f4b9ae9a05d 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -364,11 +364,107 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
   TargetTransformInfo::VPLegalization
   getVPLegalizationStrategy(const VPIntrinsic &PI) const override {
     using VPLegalization = TargetTransformInfo::VPLegalization;
+    static const Intrinsic::ID Supported[] = {
+        Intrinsic::experimental_vp_strided_load,
+        Intrinsic::experimental_vp_strided_store,
+        Intrinsic::experimental_vp_reverse,
+        Intrinsic::experimental_vp_splice,
+        Intrinsic::vp_abs,
+        Intrinsic::vp_add,
+        Intrinsic::vp_and,
+        Intrinsic::vp_ashr,
+        Intrinsic::vp_bitreverse,
+        Intrinsic::vp_bswap,
+        Intrinsic::vp_ceil,
+        Intrinsic::vp_copysign,
+        Intrinsic::vp_ctlz,
+        Intrinsic::vp_ctpop,
+        Intrinsic::vp_cttz,
+        Intrinsic::vp_cttz_elts,
+        Intrinsic::vp_fabs,
+        Intrinsic::vp_fadd,
+        Intrinsic::vp_fcmp,
+        Intrinsic::vp_fdiv,
+        Intrinsic::vp_floor,
+        Intrinsic::vp_fma,
+        Intrinsic::vp_fmul,
+        Intrinsic::vp_fmuladd,
+        Intrinsic::vp_fneg,
+        Intrinsic::vp_fpext,
+        Intrinsic::vp_fptosi,
+        Intrinsic::vp_fptoui,
+        Intrinsic::vp_fptrunc,
+        Intrinsic::vp_frem,
+        Intrinsic::vp_fshl,
+        Intrinsic::vp_fshr,
+        Intrinsic::vp_fsub,
+        Intrinsic::vp_gather,
+        Intrinsic::vp_icmp,
+        Intrinsic::vp_inttoptr,
+        Intrinsic::vp_is_fpclass,
+        Intrinsic::vp_llrint,
+        Intrinsic::vp_load,
+        Intrinsic::vp_load_ff,
+        Intrinsic::vp_lrint,
+        Intrinsic::vp_lshr,
+        Intrinsic::vp_maximum,
+        Intrinsic::vp_maxnum,
+        Intrinsic::vp_merge,
+        Intrinsic::vp_minimum,
+        Intrinsic::vp_minnum,
+        Intrinsic::vp_mul,
+        Intrinsic::vp_nearbyint,
+        Intrinsic::vp_or,
+        Intrinsic::vp_ptrtoint,
+        Intrinsic::vp_reduce_add,
+        Intrinsic::vp_reduce_and,
+        Intrinsic::vp_reduce_fadd,
+        Intrinsic::vp_reduce_fmax,
+        Intrinsic::vp_reduce_fmaximum,
+        Intrinsic::vp_reduce_fmin,
+        Intrinsic::vp_reduce_fminimum,
+        Intrinsic::vp_reduce_fmul,
+        Intrinsic::vp_reduce_mul,
+        Intrinsic::vp_reduce_or,
+        Intrinsic::vp_reduce_smax,
+        Intrinsic::vp_reduce_smin,
+        Intrinsic::vp_reduce_umax,
+        Intrinsic::vp_reduce_umin,
+        Intrinsic::vp_reduce_xor,
+        Intrinsic::vp_rint,
+        Intrinsic::vp_round,
+        Intrinsic::vp_roundeven,
+        Intrinsic::vp_roundtozero,
+        Intrinsic::vp_sadd_sat,
+        Intrinsic::vp_scatter,
+        Intrinsic::vp_sdiv,
+        Intrinsic::vp_select,
+        Intrinsic::vp_sext,
+        Intrinsic::vp_shl,
+        Intrinsic::vp_sitofp,
+        Intrinsic::vp_smax,
+        Intrinsic::vp_smin,
+        Intrinsic::vp_sqrt,
+        Intrinsic::vp_srem,
+        Intrinsic::vp_ssub_sat,
+        Intrinsic::vp_store,
+        Intrinsic::vp_sub,
+        Intrinsic::vp_trunc,
+        Intrinsic::vp_uadd_sat,
+        Intrinsic::vp_udiv,
+        Intrinsic::vp_uitofp,
+        Intrinsic::vp_umax,
+        Intrinsic::vp_umin,
+        Intrinsic::vp_urem,
+        Intrinsic::vp_usub_sat,
+        Intrinsic::vp_xor,
+        Intrinsic::vp_zext};
     if (!ST->hasVInstructions() ||
         (PI.getIntrinsicID() == Intrinsic::vp_reduce_mul &&
          cast<VectorType>(PI.getArgOperand(1)->getType())
                  ->getElementType()
-                 ->getIntegerBitWidth() != 1))
+                 ->getIntegerBitWidth() != 1) ||
+        !is_contained(Supported, PI.getIntrinsicID()))
       return VPLegalization(VPLegalization::Discard, VPLegalization::Convert);
     return VPLegalization(VPLegalization::Legal, VPLegalization::Legal);
   }