[llvm] [MachineVerifier] Disallow subregister defs in SSA form (PR #189403)

[Jay Foad via llvm-commits]

jayfoad wrote:

> > I don't know how to test this since MIRParser will complain if it sees a subregister def in an isSSA function.
> 
> It's really a pain when the assembler decides to enforce some rules that overlap with the verifier

Maybe the assembler should only infer isSSA when there is no explicit isSSA property? The extra check for "has explicit property IsSSA, but is not valid SSA" is redundant with MachineVerifier.

https://github.com/llvm/llvm-project/pull/189403