[llvm] [MachineVerifier] Disallow subregister defs in SSA form (PR #189403)

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 31 01:10:26 PDT 2026


arsenm wrote:

> I don't know how to test this since MIRParser will complain if it sees a subregister def in an isSSA function.

It's really a pain when the assembler decides to enforce some rules that overlap with the verifier

https://github.com/llvm/llvm-project/pull/189403


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