[clang] [llvm] [RISCV] Add Zvzip intrinsics (PR #186342)

[Pengcheng Wang via llvm-commits]

================
@@ -29,3 +29,96 @@ let Predicates = [HasStdExtZvzip], Constraints = "@earlyclobber $vd" in {
     def VPAIRO_VV : VALUVV<0b001111, OPMVV, "vpairo.vv">;
   }
 } // Predicates = [HasStdExtZvzip]
+
+defset list<VTypeInfoToWide> AllZvzipVectors = {
+  def : VTypeInfoToWide<VI8MF8,  VI8MF4>;
+  def : VTypeInfoToWide<VI8MF4,  VI8MF2>;
+  def : VTypeInfoToWide<VI8MF2,  VI8M1>;
+  def : VTypeInfoToWide<VI8M1,   VI8M2>;
+  def : VTypeInfoToWide<VI8M2,   VI8M4>;
+  def : VTypeInfoToWide<VI8M4,   VI8M8>;
+
+  def : VTypeInfoToWide<VI16MF4, VI16MF2>;
+  def : VTypeInfoToWide<VI16MF2, VI16M1>;
+  def : VTypeInfoToWide<VI16M1,  VI16M2>;
+  def : VTypeInfoToWide<VI16M2,  VI16M4>;
+  def : VTypeInfoToWide<VI16M4,  VI16M8>;
+
+  def : VTypeInfoToWide<VI32MF2, VI32M1>;
+  def : VTypeInfoToWide<VI32M1,  VI32M2>;
+  def : VTypeInfoToWide<VI32M2,  VI32M4>;
+  def : VTypeInfoToWide<VI32M4,  VI32M8>;
+
+  def : VTypeInfoToWide<VI64M1,  VI64M2>;
+  def : VTypeInfoToWide<VI64M2,  VI64M4>;
+  def : VTypeInfoToWide<VI64M4,  VI64M8>;
+
+  // Floating-point 16-bit
+  def : VTypeInfoToWide<VF16MF4, VF16MF2>;
+  def : VTypeInfoToWide<VF16MF2, VF16M1>;
+  def : VTypeInfoToWide<VF16M1,  VF16M2>;
+  def : VTypeInfoToWide<VF16M2,  VF16M4>;
+  def : VTypeInfoToWide<VF16M4,  VF16M8>;
+
+  // Floating-point 32-bit
+  def : VTypeInfoToWide<VF32MF2, VF32M1>;
+  def : VTypeInfoToWide<VF32M1,  VF32M2>;
+  def : VTypeInfoToWide<VF32M2,  VF32M4>;
+  def : VTypeInfoToWide<VF32M4,  VF32M8>;
+
+  // Floating-point 64-bit
+  def : VTypeInfoToWide<VF64M1,  VF64M2>;
+  def : VTypeInfoToWide<VF64M2,  VF64M4>;
+  def : VTypeInfoToWide<VF64M4,  VF64M8>;
+}
+
+multiclass VPseudoVZIP {
+  foreach m = MxListW in
+    defm "" : VPseudoBinaryW_VV<m, Commutable=0>,
+              SchedBinary<"WriteVIWALUV", "ReadVIWALUV", "ReadVIWALUV", m.MX,
+                          forcePassthruRead=true>;
+}
+
+multiclass VPseudoVUNZIP {
+  foreach m = MxListW in {
+    defvar mx = m.MX;
+    let VLMul = m.value in {
+      def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.wvrclass>,
+                       SchedUnary<"WriteVIALUV", "ReadVIALUV", mx, forcePassthruRead=true>;
+      def "_V_" # mx # "_MASK" :
+        VPseudoUnaryMask<m.vrclass, m.wvrclass>,
+        RISCVMaskedPseudo<MaskIdx=2>,
+        SchedUnary<"WriteVIALUV", "ReadVIALUV", mx, forcePassthruRead=true>;
+    }
+  }
+}
+
+let Predicates = [HasStdExtZvzip],
+    Constraints = "@earlyclobber $rd, $rd = $passthru" in {
+  defm PseudoVZIP    : VPseudoVZIP;
+  defm PseudoVUNZIPE : VPseudoVUNZIP;
+  defm PseudoVUNZIPO : VPseudoVUNZIP;
+  defm PseudoVPAIRE  : VPseudoVALU_VV;
+  defm PseudoVPAIRO  : VPseudoVALU_VV;
+}
+
+multiclass VPatVUNZIPIntrinsic<string intrinsic_name, string instruction_name> {
+  foreach VtiToWti = AllZvzipVectors in {
+    defvar vti = VtiToWti.Vti;
+    defvar wti = VtiToWti.Wti;
+    let Predicates = !listconcat(GetVTypePredicates<wti>.Predicates, [HasStdExtZvzip]) in {
+      def : VPatUnaryNoMask<intrinsic_name, instruction_name, "V",
+                            vti.Vector, wti.Vector, vti.Log2SEW,
+                            vti.LMul, vti.RegClass, wti.RegClass>;
+      def : VPatUnaryMask<intrinsic_name, instruction_name, "V",
+                          vti.Vector, wti.Vector, vti.Mask, vti.Log2SEW,
+                          vti.LMul, vti.RegClass, wti.RegClass>;
+    }
+  }
+}
+
+defm : VPatVUNZIPIntrinsic<"int_riscv_vunzipe", "PseudoVUNZIPE">;
+defm : VPatVUNZIPIntrinsic<"int_riscv_vunzipo", "PseudoVUNZIPO">;
+defm : VPatBinaryV_VV<"int_riscv_vpaire", "PseudoVPAIRE", AllVectors>;
+defm : VPatBinaryV_VV<"int_riscv_vpairo", "PseudoVPAIRO", AllVectors>;
+defm : VPatBinaryW_VV<"int_riscv_vzip", "PseudoVZIP", AllZvzipVectors>;
----------------
wangpc-pp wrote:

Done in https://github.com/llvm/llvm-project/pull/186342/commits/723d028563053e6f17b54e0e20ac48ac5c71a751.

https://github.com/llvm/llvm-project/pull/186342