[llvm] [NewPM] Adds a port for AArch64PostCoalescerPass (PR #189520)
Anshul Nigham via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 30 18:58:21 PDT 2026
https://github.com/nigham created https://github.com/llvm/llvm-project/pull/189520
Adds a standard porting for AArch64PostCoalescer to NewPM.
>From d52322051622f807a0e287732451cd5f53afc4b7 Mon Sep 17 00:00:00 2001
From: Anshul Nigham <nigham at google.com>
Date: Thu, 26 Mar 2026 14:34:21 -0700
Subject: [PATCH 1/2] [NewPM] Adds a port for AArch64PostCoalescerPass
---
llvm/lib/Target/AArch64/AArch64.h | 9 ++-
.../Target/AArch64/AArch64PassRegistry.def | 1 +
.../AArch64/AArch64PostCoalescerPass.cpp | 61 +++++++++++++------
.../Target/AArch64/AArch64TargetMachine.cpp | 2 +-
.../AArch64/aarch64-post-coalescer.mir | 1 +
5 files changed, 54 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h
index a4910df6957c9..81d44a2947d2e 100644
--- a/llvm/lib/Target/AArch64/AArch64.h
+++ b/llvm/lib/Target/AArch64/AArch64.h
@@ -99,7 +99,7 @@ void initializeAArch64LoadStoreOptLegacyPass(PassRegistry &);
void initializeAArch64LowerHomogeneousPrologEpilogPass(PassRegistry &);
void initializeAArch64MIPeepholeOptLegacyPass(PassRegistry &);
void initializeAArch64O0PreLegalizerCombinerPass(PassRegistry &);
-void initializeAArch64PostCoalescerPass(PassRegistry &);
+void initializeAArch64PostCoalescerLegacyPass(PassRegistry &);
void initializeAArch64PostLegalizerCombinerPass(PassRegistry &);
void initializeAArch64PostLegalizerLoweringPass(PassRegistry &);
void initializeAArch64PostSelectOptimizePass(PassRegistry &);
@@ -195,6 +195,13 @@ class AArch64PointerAuthPass : public PassInfoMixin<AArch64PointerAuthPass> {
MachineFunctionAnalysisManager &MFAM);
};
+class AArch64PostCoalescerPass
+ : public PassInfoMixin<AArch64PostCoalescerPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+
} // end namespace llvm
#endif
diff --git a/llvm/lib/Target/AArch64/AArch64PassRegistry.def b/llvm/lib/Target/AArch64/AArch64PassRegistry.def
index 9567d76ccf64c..fb37537ba9547 100644
--- a/llvm/lib/Target/AArch64/AArch64PassRegistry.def
+++ b/llvm/lib/Target/AArch64/AArch64PassRegistry.def
@@ -35,6 +35,7 @@ MACHINE_FUNCTION_PASS("aarch64-fix-cortex-a53-835769", AArch64A53Fix835769Pass()
MACHINE_FUNCTION_PASS("aarch64-jump-tables", AArch64CompressJumpTablesPass())
MACHINE_FUNCTION_PASS("aarch64-ldst-opt", AArch64LoadStoreOptPass())
MACHINE_FUNCTION_PASS("aarch64-mi-peephole-opt", AArch64MIPeepholeOptPass())
+MACHINE_FUNCTION_PASS("aarch64-post-coalescer-pass", AArch64PostCoalescerPass())
MACHINE_FUNCTION_PASS("aarch64-ptrauth", AArch64PointerAuthPass())
MACHINE_FUNCTION_PASS("aarch64-simd-scalar", AArch64AdvSIMDScalarPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp b/llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
index a90950ddaaa96..76c460ab337f2 100644
--- a/llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
+++ b/llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
@@ -7,8 +7,10 @@
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
+#include "AArch64.h"
#include "AArch64MachineFunctionInfo.h"
#include "llvm/CodeGen/LiveIntervals.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/InitializePasses.h"
@@ -18,13 +20,18 @@ using namespace llvm;
namespace {
-struct AArch64PostCoalescer : public MachineFunctionPass {
- static char ID;
+struct AArch64PostCoalescerImpl {
+ LiveIntervals &LIS;
+ MachineRegisterInfo *MRI;
- AArch64PostCoalescer() : MachineFunctionPass(ID) {}
+ explicit AArch64PostCoalescerImpl(LiveIntervals &LIS) : LIS(LIS) {}
+ bool run(MachineFunction &MF);
+};
- LiveIntervals *LIS;
- MachineRegisterInfo *MRI;
+struct AArch64PostCoalescerLegacy : public MachineFunctionPass {
+ static char ID;
+
+ AArch64PostCoalescerLegacy() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override;
@@ -33,32 +40,29 @@ struct AArch64PostCoalescer : public MachineFunctionPass {
}
void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.setPreservesAll();
+ AU.setPreservesCFG();
AU.addRequired<LiveIntervalsWrapperPass>();
+ AU.addPreserved<LiveIntervalsWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
};
-char AArch64PostCoalescer::ID = 0;
+char AArch64PostCoalescerLegacy::ID = 0;
} // end anonymous namespace
-INITIALIZE_PASS_BEGIN(AArch64PostCoalescer, "aarch64-post-coalescer-pass",
+INITIALIZE_PASS_BEGIN(AArch64PostCoalescerLegacy, "aarch64-post-coalescer-pass",
"AArch64 Post Coalescer Pass", false, false)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
-INITIALIZE_PASS_END(AArch64PostCoalescer, "aarch64-post-coalescer-pass",
+INITIALIZE_PASS_END(AArch64PostCoalescerLegacy, "aarch64-post-coalescer-pass",
"AArch64 Post Coalescer Pass", false, false)
-bool AArch64PostCoalescer::runOnMachineFunction(MachineFunction &MF) {
- if (skipFunction(MF.getFunction()))
- return false;
-
+bool AArch64PostCoalescerImpl::run(MachineFunction &MF) {
AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
if (!FuncInfo->hasStreamingModeChanges())
return false;
MRI = &MF.getRegInfo();
- LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
bool Changed = false;
for (MachineBasicBlock &MBB : MF) {
@@ -81,11 +85,11 @@ bool AArch64PostCoalescer::runOnMachineFunction(MachineFunction &MF) {
// MI must be erased from the basic block before recalculating the live
// interval.
- LIS->RemoveMachineInstrFromMaps(MI);
+ LIS.RemoveMachineInstrFromMaps(MI);
MI.eraseFromParent();
- LIS->removeInterval(Src);
- LIS->createAndComputeVirtRegInterval(Src);
+ LIS.removeInterval(Src);
+ LIS.createAndComputeVirtRegInterval(Src);
Changed = true;
break;
@@ -97,6 +101,27 @@ bool AArch64PostCoalescer::runOnMachineFunction(MachineFunction &MF) {
return Changed;
}
+bool AArch64PostCoalescerLegacy::runOnMachineFunction(MachineFunction &MF) {
+ if (skipFunction(MF.getFunction()))
+ return false;
+
+ auto &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
+ return AArch64PostCoalescerImpl(LIS).run(MF);
+}
+
+PreservedAnalyses
+AArch64PostCoalescerPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ auto &LIS = MFAM.getResult<LiveIntervalsAnalysis>(MF);
+ const bool Changed = AArch64PostCoalescerImpl(LIS).run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+ PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ PA.preserve<LiveIntervalsAnalysis>();
+ return PA;
+}
+
FunctionPass *llvm::createAArch64PostCoalescerPass() {
- return new AArch64PostCoalescer();
+ return new AArch64PostCoalescerLegacy();
}
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index b8c2c96301b69..d8a8210f22be2 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -260,7 +260,7 @@ LLVMInitializeAArch64Target() {
initializeAArch64O0PreLegalizerCombinerPass(PR);
initializeAArch64PreLegalizerCombinerPass(PR);
initializeAArch64PointerAuthLegacyPass(PR);
- initializeAArch64PostCoalescerPass(PR);
+ initializeAArch64PostCoalescerLegacyPass(PR);
initializeAArch64PostLegalizerCombinerPass(PR);
initializeAArch64PostLegalizerLoweringPass(PR);
initializeAArch64PostSelectOptimizePass(PR);
diff --git a/llvm/test/CodeGen/AArch64/aarch64-post-coalescer.mir b/llvm/test/CodeGen/AArch64/aarch64-post-coalescer.mir
index 654016014be98..03278bdda8603 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-post-coalescer.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64-post-coalescer.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=aarch64 -mattr=+sme -run-pass=aarch64-post-coalescer-pass -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64 -mattr=+sme -passes=aarch64-post-coalescer-pass -o - %s | FileCheck %s
---
name: foo
>From f20822347b809ef41b6ba43ec8e9593cdd5acb05 Mon Sep 17 00:00:00 2001
From: Anshul Nigham <nigham at google.com>
Date: Mon, 30 Mar 2026 18:55:54 -0700
Subject: [PATCH 2/2] Update to mark SlotIndexes preserved in NewPM pass
---
llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp b/llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
index 31caad3b86c28..1696e62e7d3f9 100644
--- a/llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
+++ b/llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
@@ -121,6 +121,7 @@ AArch64PostCoalescerPass::run(MachineFunction &MF,
PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
PA.preserveSet<CFGAnalyses>();
PA.preserve<LiveIntervalsAnalysis>();
+ PA.preserve<SlotIndexesAnalysis>();
return PA;
}
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