[llvm] 9de3ebd - [RISCV] Avoid creating unnecessary node. Add missing break to switch. NFC (#189511)

[via llvm-commits]

Author: Craig Topper
Date: 2026-03-30T17:56:28-07:00
New Revision: 9de3ebde1c8c0f5d51fe8906fcb8a88899970031

URL: https://github.com/llvm/llvm-project/commit/9de3ebde1c8c0f5d51fe8906fcb8a88899970031
DIFF: https://github.com/llvm/llvm-project/commit/9de3ebde1c8c0f5d51fe8906fcb8a88899970031.diff

LOG: [RISCV] Avoid creating unnecessary node. Add missing break to switch. NFC (#189511)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 55996148c07e9..6a77797918b09 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -12357,8 +12357,11 @@ SDValue RISCVTargetLowering::lowerVECREDUCE(SDValue Op,
 
   auto [Mask, VL] = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
 
-  SDValue StartV = DAG.getNeutralElement(BaseOpc, DL, VecEltVT, SDNodeFlags());
+  SDValue StartV;
   switch (BaseOpc) {
+  default:
+    StartV = DAG.getNeutralElement(BaseOpc, DL, VecEltVT, SDNodeFlags());
+    break;
   case ISD::AND:
   case ISD::OR:
   case ISD::UMAX:
@@ -12366,6 +12369,7 @@ SDValue RISCVTargetLowering::lowerVECREDUCE(SDValue Op,
   case ISD::SMAX:
   case ISD::SMIN:
     StartV = DAG.getExtractVectorElt(DL, VecEltVT, Vec, 0);
+    break;
   }
   return lowerReductionSeq(RVVOpcode, Op.getSimpleValueType(), StartV, Vec,
                            Mask, VL, DL, DAG, Subtarget);