[llvm] 306e86b - [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (#187400)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 30 07:35:50 PDT 2026
Author: Jonathan Thackray
Date: 2026-03-30T14:35:40Z
New Revision: 306e86be5108f70c8d54f52d95daec6b8614c7e6
URL: https://github.com/llvm/llvm-project/commit/306e86be5108f70c8d54f52d95daec6b8614c7e6
DIFF: https://github.com/llvm/llvm-project/commit/306e86be5108f70c8d54f52d95daec6b8614c7e6.diff
LOG: [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (#187400)
Added:
Modified:
llvm/lib/Target/AArch64/AArch64SystemOperands.td
llvm/test/MC/AArch64/armv8.7a-xs.s
llvm/test/MC/AArch64/armv9.5a-tlbiw.s
llvm/test/MC/AArch64/armv9a-tlbip.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 8129dde0658cf..67d8e852822b8 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -866,13 +866,14 @@ def REG_NONE : RegValue;
def REG_OPTIONAL : RegValue;
def REG_REQUIRED : RegValue;
-class TLBICommon<string name, bits<3> op1, bits<4> crn, bits<4> crm,
- bits<3> op2, RegValue reguse> {
+class TLBICommon<string name, bits<3> op1, bits<4> crm, bits<3> op2, bit nxs,
+ RegValue reguse> {
string Name = name;
bits<14> Encoding;
RegValue RegUse = reguse;
let Encoding{13-11} = op1;
- let Encoding{10-7} = crn;
+ let Encoding{10-8} = 0b100;
+ let Encoding{7} = nxs;
let Encoding{6-3} = crm;
let Encoding{2-0} = op2;
list<string> Requires = [];
@@ -880,13 +881,13 @@ class TLBICommon<string name, bits<3> op1, bits<4> crn, bits<4> crm,
code RequiresStr = [{ { }] # !interleave(Requires # ExtraRequires, [{, }]) # [{ } }];
}
-class TLBIEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
- bits<3> op2, RegValue reguse>
- : TLBICommon<name, op1, crn, crm, op2, reguse>;
+class TLBIEntry<string name, bits<3> op1, bits<4> crm, bits<3> op2, bit nxs,
+ RegValue reguse>
+ : TLBICommon<name, op1, crm, op2, nxs, reguse>;
-class TLBIPEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
- bits<3> op2, RegValue reguse>
- : TLBICommon<name, op1, crn, crm, op2, reguse>;
+class TLBIPEntry<string name, bits<3> op1, bits<4> crm, bits<3> op2, bit nxs,
+ RegValue reguse>
+ : TLBICommon<name, op1, crm, op2, nxs, reguse>;
multiclass TLBITableBase {
def NAME # Table : GenericTable {
@@ -906,128 +907,163 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI<string name, bit hasTLBIP, bits<3> op1, bits<4> crn, bits<4> crm,
- bits<3> op2, RegValue reguse> {
- def : TLBIEntry<name, op1, crn, crm, op2, reguse>;
- def : TLBIEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, reguse> {
- let Encoding{7} = 1;
+class TLBI<string name, bits<3> op1, bits<4> crm, bits<3> op2,
+ RegValue reguse, bit hasTLBIP = 0> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ RegValue RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ // name op1 CRm op2 reguse hasTLBIP
+ TLBI<"IPAS2E1IS", 0b100, 0b0000, 0b001, REG_REQUIRED, 1>,
+ TLBI<"IPAS2LE1IS", 0b100, 0b0000, 0b101, REG_REQUIRED, 1>,
+ TLBI<"VMALLE1IS", 0b000, 0b0011, 0b000, REG_OPTIONAL, 0>,
+ TLBI<"ALLE2IS", 0b100, 0b0011, 0b000, REG_OPTIONAL, 0>,
+ TLBI<"ALLE3IS", 0b110, 0b0011, 0b000, REG_OPTIONAL, 0>,
+ TLBI<"VAE1IS", 0b000, 0b0011, 0b001, REG_REQUIRED, 1>,
+ TLBI<"VAE2IS", 0b100, 0b0011, 0b001, REG_REQUIRED, 1>,
+ TLBI<"VAE3IS", 0b110, 0b0011, 0b001, REG_REQUIRED, 1>,
+ TLBI<"ASIDE1IS", 0b000, 0b0011, 0b010, REG_REQUIRED, 0>,
+ TLBI<"VAAE1IS", 0b000, 0b0011, 0b011, REG_REQUIRED, 1>,
+ TLBI<"ALLE1IS", 0b100, 0b0011, 0b100, REG_OPTIONAL, 0>,
+ TLBI<"VALE1IS", 0b000, 0b0011, 0b101, REG_REQUIRED, 1>,
+ TLBI<"VALE2IS", 0b100, 0b0011, 0b101, REG_REQUIRED, 1>,
+ TLBI<"VALE3IS", 0b110, 0b0011, 0b101, REG_REQUIRED, 1>,
+ TLBI<"VMALLS12E1IS", 0b100, 0b0011, 0b110, REG_OPTIONAL, 0>,
+ TLBI<"VAALE1IS", 0b000, 0b0011, 0b111, REG_REQUIRED, 1>,
+ TLBI<"IPAS2E1", 0b100, 0b0100, 0b001, REG_REQUIRED, 1>,
+ TLBI<"IPAS2LE1", 0b100, 0b0100, 0b101, REG_REQUIRED, 1>,
+ TLBI<"VMALLE1", 0b000, 0b0111, 0b000, REG_NONE, 0>,
+ TLBI<"ALLE2", 0b100, 0b0111, 0b000, REG_NONE, 0>,
+ TLBI<"ALLE3", 0b110, 0b0111, 0b000, REG_NONE, 0>,
+ TLBI<"VAE1", 0b000, 0b0111, 0b001, REG_REQUIRED, 1>,
+ TLBI<"VAE2", 0b100, 0b0111, 0b001, REG_REQUIRED, 1>,
+ TLBI<"VAE3", 0b110, 0b0111, 0b001, REG_REQUIRED, 1>,
+ TLBI<"ASIDE1", 0b000, 0b0111, 0b010, REG_REQUIRED, 0>,
+ TLBI<"VAAE1", 0b000, 0b0111, 0b011, REG_REQUIRED, 1>,
+ TLBI<"ALLE1", 0b100, 0b0111, 0b100, REG_NONE, 0>,
+ TLBI<"VALE1", 0b000, 0b0111, 0b101, REG_REQUIRED, 1>,
+ TLBI<"VALE2", 0b100, 0b0111, 0b101, REG_REQUIRED, 1>,
+ TLBI<"VALE3", 0b110, 0b0111, 0b101, REG_REQUIRED, 1>,
+ TLBI<"VMALLS12E1", 0b100, 0b0111, 0b110, REG_NONE, 0>,
+ TLBI<"VAALE1", 0b000, 0b0111, 0b111, REG_REQUIRED, 1>
+];
+
+foreach I = TLBIBase in {
+ def : TLBIEntry<I.Name, I.Op1, I.CRm, I.Op2, 0, I.RegUse>;
+ def : TLBIEntry<!strconcat(I.Name, "nXS"), I.Op1, I.CRm, I.Op2, 1, I.RegUse> {
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
- def : TLBIPEntry<name, op1, crn, crm, op2, reguse> {
- let ExtraRequires = ["AArch64::FeatureD128"];
- }
- def : TLBIPEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, reguse> {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if I.HasTLBIP then {
+ let Requires = ["AArch64::FeatureD128"] in {
+ def : TLBIPEntry<I.Name, I.Op1, I.CRm, I.Op2, 0, I.RegUse>;
+ def : TLBIPEntry<!strconcat(I.Name, "nXS"), I.Op1, I.CRm, I.Op2, 1, I.RegUse>;
}
}
}
-// hasTLBIP op1 CRn CRm op2 reguse
-defm : TLBI<"IPAS2E1IS", 1, 0b100, 0b1000, 0b0000, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b0000, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1IS", 0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
-defm : TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>;
-defm : TLBI<"ALLE2", 0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>;
-defm : TLBI<"ALLE3", 0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>;
-defm : TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1", 1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1", 0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>;
-defm : TLBI<"VALE1", 1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE2", 1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE3", 1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
-defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
-// Armv8.4-A Outer Sharable TLB Maintenance instructions:
-// hasTLBIP op1 CRn CRm op2 reguse
-defm : TLBI<"VMALLE1OS", 0, 0b000, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011, REG_REQUIRED>;
-defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1OS", 1, 0b100, 0b1000, 0b0100, 0b000, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100, REG_REQUIRED>;
-defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAE3OS", 1, 0b110, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE3OS", 1, 0b110, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"ALLE2OS", 0, 0b100, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE1OS", 0, 0b100, 0b1000, 0b0001, 0b100, REG_OPTIONAL>;
-defm : TLBI<"ALLE3OS", 0, 0b110, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-
-// Armv8.4-A TLB Range Maintenance instructions:
-// hasTLBIP op1 CRn CRm op2
-defm : TLBI<"RVAE1", 1, 0b000, 0b1000, 0b0110, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1", 1, 0b000, 0b1000, 0b0110, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1", 1, 0b000, 0b1000, 0b0110, 0b101, REG_REQUIRED>;
-defm : TLBI<"RVAALE1", 1, 0b000, 0b1000, 0b0110, 0b111, REG_REQUIRED>;
-defm : TLBI<"RVAE1IS", 1, 0b000, 0b1000, 0b0010, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1IS", 1, 0b000, 0b1000, 0b0010, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1IS", 1, 0b000, 0b1000, 0b0010, 0b101, REG_REQUIRED>;
-defm : TLBI<"RVAALE1IS", 1, 0b000, 0b1000, 0b0010, 0b111, REG_REQUIRED>;
-defm : TLBI<"RVAE1OS", 1, 0b000, 0b1000, 0b0101, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1OS", 1, 0b000, 0b1000, 0b0101, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1OS", 1, 0b000, 0b1000, 0b0101, 0b101, REG_REQUIRED>;
-defm : TLBI<"RVAALE1OS", 1, 0b000, 0b1000, 0b0101, 0b111, REG_REQUIRED>;
-defm : TLBI<"RIPAS2E1IS", 1, 0b100, 0b1000, 0b0000, 0b010, REG_REQUIRED>;
-defm : TLBI<"RIPAS2LE1IS", 1, 0b100, 0b1000, 0b0000, 0b110, REG_REQUIRED>;
-defm : TLBI<"RIPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b010, REG_REQUIRED>;
-defm : TLBI<"RIPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b110, REG_REQUIRED>;
-defm : TLBI<"RIPAS2E1OS", 1, 0b100, 0b1000, 0b0100, 0b011, REG_REQUIRED>;
-defm : TLBI<"RIPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b111, REG_REQUIRED>;
-defm : TLBI<"RVAE2", 1, 0b100, 0b1000, 0b0110, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVALE2", 1, 0b100, 0b1000, 0b0110, 0b101, REG_REQUIRED>;
-defm : TLBI<"RVAE2IS", 1, 0b100, 0b1000, 0b0010, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVALE2IS", 1, 0b100, 0b1000, 0b0010, 0b101, REG_REQUIRED>;
-defm : TLBI<"RVAE2OS", 1, 0b100, 0b1000, 0b0101, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVALE2OS", 1, 0b100, 0b1000, 0b0101, 0b101, REG_REQUIRED>;
-defm : TLBI<"RVAE3", 1, 0b110, 0b1000, 0b0110, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVALE3", 1, 0b110, 0b1000, 0b0110, 0b101, REG_REQUIRED>;
-defm : TLBI<"RVAE3IS", 1, 0b110, 0b1000, 0b0010, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVALE3IS", 1, 0b110, 0b1000, 0b0010, 0b101, REG_REQUIRED>;
-defm : TLBI<"RVAE3OS", 1, 0b110, 0b1000, 0b0101, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVALE3OS", 1, 0b110, 0b1000, 0b0101, 0b101, REG_REQUIRED>;
-} //FeatureTLB_RMI
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
+defvar TLBIRMI = [
+ // name op1 CRm op2 reguse hasTLBIP
+ TLBI<"VMALLE1OS", 0b000, 0b0001, 0b000, REG_OPTIONAL, 0>,
+ TLBI<"VAE1OS", 0b000, 0b0001, 0b001, REG_REQUIRED, 1>,
+ TLBI<"ASIDE1OS", 0b000, 0b0001, 0b010, REG_REQUIRED, 0>,
+ TLBI<"VAAE1OS", 0b000, 0b0001, 0b011, REG_REQUIRED, 1>,
+ TLBI<"VALE1OS", 0b000, 0b0001, 0b101, REG_REQUIRED, 1>,
+ TLBI<"VAALE1OS", 0b000, 0b0001, 0b111, REG_REQUIRED, 1>,
+ TLBI<"IPAS2E1OS", 0b100, 0b0100, 0b000, REG_REQUIRED, 1>,
+ TLBI<"IPAS2LE1OS", 0b100, 0b0100, 0b100, REG_REQUIRED, 1>,
+ TLBI<"VAE2OS", 0b100, 0b0001, 0b001, REG_REQUIRED, 1>,
+ TLBI<"VALE2OS", 0b100, 0b0001, 0b101, REG_REQUIRED, 1>,
+ TLBI<"VMALLS12E1OS", 0b100, 0b0001, 0b110, REG_OPTIONAL, 0>,
+ TLBI<"VAE3OS", 0b110, 0b0001, 0b001, REG_REQUIRED, 1>,
+ TLBI<"VALE3OS", 0b110, 0b0001, 0b101, REG_REQUIRED, 1>,
+ TLBI<"ALLE2OS", 0b100, 0b0001, 0b000, REG_OPTIONAL, 0>,
+ TLBI<"ALLE1OS", 0b100, 0b0001, 0b100, REG_OPTIONAL, 0>,
+ TLBI<"ALLE3OS", 0b110, 0b0001, 0b000, REG_OPTIONAL, 0>,
+ TLBI<"RVAE1", 0b000, 0b0110, 0b001, REG_REQUIRED, 1>,
+ TLBI<"RVAAE1", 0b000, 0b0110, 0b011, REG_REQUIRED, 1>,
+ TLBI<"RVALE1", 0b000, 0b0110, 0b101, REG_REQUIRED, 1>,
+ TLBI<"RVAALE1", 0b000, 0b0110, 0b111, REG_REQUIRED, 1>,
+ TLBI<"RVAE1IS", 0b000, 0b0010, 0b001, REG_REQUIRED, 1>,
+ TLBI<"RVAAE1IS", 0b000, 0b0010, 0b011, REG_REQUIRED, 1>,
+ TLBI<"RVALE1IS", 0b000, 0b0010, 0b101, REG_REQUIRED, 1>,
+ TLBI<"RVAALE1IS", 0b000, 0b0010, 0b111, REG_REQUIRED, 1>,
+ TLBI<"RVAE1OS", 0b000, 0b0101, 0b001, REG_REQUIRED, 1>,
+ TLBI<"RVAAE1OS", 0b000, 0b0101, 0b011, REG_REQUIRED, 1>,
+ TLBI<"RVALE1OS", 0b000, 0b0101, 0b101, REG_REQUIRED, 1>,
+ TLBI<"RVAALE1OS", 0b000, 0b0101, 0b111, REG_REQUIRED, 1>,
+ TLBI<"RIPAS2E1IS", 0b100, 0b0000, 0b010, REG_REQUIRED, 1>,
+ TLBI<"RIPAS2LE1IS", 0b100, 0b0000, 0b110, REG_REQUIRED, 1>,
+ TLBI<"RIPAS2E1", 0b100, 0b0100, 0b010, REG_REQUIRED, 1>,
+ TLBI<"RIPAS2LE1", 0b100, 0b0100, 0b110, REG_REQUIRED, 1>,
+ TLBI<"RIPAS2E1OS", 0b100, 0b0100, 0b011, REG_REQUIRED, 1>,
+ TLBI<"RIPAS2LE1OS", 0b100, 0b0100, 0b111, REG_REQUIRED, 1>,
+ TLBI<"RVAE2", 0b100, 0b0110, 0b001, REG_REQUIRED, 1>,
+ TLBI<"RVALE2", 0b100, 0b0110, 0b101, REG_REQUIRED, 1>,
+ TLBI<"RVAE2IS", 0b100, 0b0010, 0b001, REG_REQUIRED, 1>,
+ TLBI<"RVALE2IS", 0b100, 0b0010, 0b101, REG_REQUIRED, 1>,
+ TLBI<"RVAE2OS", 0b100, 0b0101, 0b001, REG_REQUIRED, 1>,
+ TLBI<"RVALE2OS", 0b100, 0b0101, 0b101, REG_REQUIRED, 1>,
+ TLBI<"RVAE3", 0b110, 0b0110, 0b001, REG_REQUIRED, 1>,
+ TLBI<"RVALE3", 0b110, 0b0110, 0b101, REG_REQUIRED, 1>,
+ TLBI<"RVAE3IS", 0b110, 0b0010, 0b001, REG_REQUIRED, 1>,
+ TLBI<"RVALE3IS", 0b110, 0b0010, 0b101, REG_REQUIRED, 1>,
+ TLBI<"RVAE3OS", 0b110, 0b0101, 0b001, REG_REQUIRED, 1>,
+ TLBI<"RVALE3OS", 0b110, 0b0101, 0b101, REG_REQUIRED, 1>
+];
+
+foreach I = TLBIRMI in {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+ def : TLBIEntry<I.Name, I.Op1, I.CRm, I.Op2, 0, I.RegUse>;
+ }
+
+ let Requires = ["AArch64::FeatureXS"] in {
+ def : TLBIEntry<!strconcat(I.Name, "nXS"), I.Op1, I.CRm, I.Op2, 1, I.RegUse>;
+ }
+
+ if I.HasTLBIP then {
+ let Requires = ["AArch64::FeatureD128"] in {
+ def : TLBIPEntry<I.Name, I.Op1, I.CRm, I.Op2, 0, I.RegUse>;
+ def : TLBIPEntry<!strconcat(I.Name, "nXS"), I.Op1, I.CRm, I.Op2, 1, I.RegUse>;
+ }
+ }
+}
// Armv9-A Realm Management Extension TLBI Instructions
+defvar TLBIRME = [
+ // name op1 CRm op2 reguse
+ TLBI<"RPAOS", 0b110, 0b0100, 0b011, REG_REQUIRED>,
+ TLBI<"RPALOS", 0b110, 0b0100, 0b111, REG_REQUIRED>,
+ TLBI<"PAALLOS", 0b110, 0b0001, 0b100, REG_NONE>,
+ TLBI<"PAALL", 0b110, 0b0111, 0b100, REG_NONE>
+];
+
let Requires = ["AArch64::FeatureRME"] in {
-// hasTLBIP op1 CRn CRm op2 reguse
-defm : TLBI<"RPAOS", 0, 0b110, 0b1000, 0b0100, 0b011, REG_REQUIRED>;
-defm : TLBI<"RPALOS", 0, 0b110, 0b1000, 0b0100, 0b111, REG_REQUIRED>;
-defm : TLBI<"PAALLOS", 0, 0b110, 0b1000, 0b0001, 0b100, REG_NONE>;
-defm : TLBI<"PAALL", 0, 0b110, 0b1000, 0b0111, 0b100, REG_NONE>;
+ foreach I = TLBIRME in {
+ def : TLBIEntry<I.Name, I.Op1, I.CRm, I.Op2, 0, I.RegUse>;
+ }
}
// Armv9.5-A TLBI VMALL for Dirty State
+defvar TLBITLBIW = [
+ // name op1 CRm op2 reguse
+ TLBI<"VMALLWS2E1", 0b100, 0b0110, 0b010, REG_NONE>,
+ TLBI<"VMALLWS2E1IS", 0b100, 0b0010, 0b010, REG_OPTIONAL>,
+ TLBI<"VMALLWS2E1OS", 0b100, 0b0101, 0b010, REG_OPTIONAL>
+];
+
let Requires = ["AArch64::FeatureTLBIW"] in {
-// hasTLBIP op1 CRn CRm op2 reguse
-defm : TLBI<"VMALLWS2E1", 0, 0b100, 0b1000, 0b0110, 0b010, REG_NONE>;
-defm : TLBI<"VMALLWS2E1IS", 0, 0b100, 0b1000, 0b0010, 0b010, REG_OPTIONAL>;
-defm : TLBI<"VMALLWS2E1OS", 0, 0b100, 0b1000, 0b0101, 0b010, REG_OPTIONAL>;
+ foreach I = TLBITLBIW in {
+ def : TLBIEntry<I.Name, I.Op1, I.CRm, I.Op2, 0, I.RegUse>;
+ def : TLBIEntry<!strconcat(I.Name, "nXS"), I.Op1, I.CRm, I.Op2, 1, I.RegUse>;
+ }
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/AArch64/armv8.7a-xs.s b/llvm/test/MC/AArch64/armv8.7a-xs.s
index e3a1e12aae9a5..da9fa98b2d78d 100644
--- a/llvm/test/MC/AArch64/armv8.7a-xs.s
+++ b/llvm/test/MC/AArch64/armv8.7a-xs.s
@@ -1,9 +1,11 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+xs < %s 2>%t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERR %s < %t
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,+xs < %s 2>%t | FileCheck %s
// RUN: FileCheck --check-prefix=CHECK-ERR %s < %t
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.7a < %s 2>%t | FileCheck %s
// RUN: FileCheck --check-prefix=CHECK-ERR %s < %t
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a < %s 2> %t
-// RUN: FileCheck --check-prefixes=CHECK-ERR,CHECK-NO-XS-ERR %s < %t
+// RUN: FileCheck --check-prefixes=CHECK-ERR,CHECK_NO_XS_ERR %s < %t
dsb #16
dsb #20
@@ -21,14 +23,14 @@
// CHECK: dsb nshnxs // encoding: [0x3f,0x36,0x03,0xd5]
// CHECK: dsb ishnxs // encoding: [0x3f,0x3a,0x03,0xd5]
// CHECK: dsb synxs // encoding: [0x3f,0x3e,0x03,0xd5]
-// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
-// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
-// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
-// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
-// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
-// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
-// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
-// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-16]]:3: error: instruction requires: xs
dsb #17
dsb nshstnxs
@@ -128,7 +130,6 @@
// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE1nXS requires: xs
// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE1nXS requires: xs
// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE2nXS requires: xs
-// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE2nXS requires: xs
// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE3nXS requires: xs
// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VMALLS12E1nXS requires: xs
// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAALE1nXS requires: xs
@@ -225,49 +226,49 @@
// CHECK: tlbi rvale3isnxs, x1 // encoding: [0xa1,0x92,0x0e,0xd5]
// CHECK: tlbi rvae3osnxs, x1 // encoding: [0x21,0x95,0x0e,0xd5]
// CHECK: tlbi rvale3osnxs, x1 // encoding: [0xa1,0x95,0x0e,0xd5]
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VMALLE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ASIDE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAAE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VALE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAALE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI IPAS2E1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI IPAS2LE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAE2OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VALE2OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VMALLS12E1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAE3OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VALE3OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ALLE2OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ALLE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ALLE3OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE1nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAAE1nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE1nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAALE1nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE1ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAAE1ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE1ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAALE1ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAAE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAALE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE2nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE2nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE2ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE2ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE2OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE2OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE3nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE3nXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE3ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE3ISnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE3OSnXS requires: tlb-rmi, xs
-// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE3OSnXS requires: tlb-rmi, xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VMALLE1OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAE1OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ASIDE1OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAAE1OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VALE1OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAALE1OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI IPAS2E1OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI IPAS2LE1OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAE2OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VALE2OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VMALLS12E1OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAE3OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VALE3OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ALLE2OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ALLE1OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ALLE3OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE1nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAAE1nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE1nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAALE1nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE1ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAAE1ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE1ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAALE1ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE1OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAAE1OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE1OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAALE1OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE2nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE2nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE2ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE2ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE2OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE2OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE3nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE3nXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE3ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE3ISnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE3OSnXS requires: xs
+// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE3OSnXS requires: xs
diff --git a/llvm/test/MC/AArch64/armv9.5a-tlbiw.s b/llvm/test/MC/AArch64/armv9.5a-tlbiw.s
index efd410c1c2c59..faee34d5dea4f 100644
--- a/llvm/test/MC/AArch64/armv9.5a-tlbiw.s
+++ b/llvm/test/MC/AArch64/armv9.5a-tlbiw.s
@@ -1,15 +1,15 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+tlbiw,+xs < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+tlbiw < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+tlbiw,+xs < %s \
-// RUN: | llvm-objdump -d --mattr=+tlbiw,+xs --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+tlbiw,+xs < %s \
-// RUN: | llvm-objdump -d --mattr=-tlbiw,-xs --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+tlbiw < %s \
+// RUN: | llvm-objdump -d --mattr=+tlbiw --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+tlbiw < %s \
+// RUN: | llvm-objdump -d --mattr=-tlbiw --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+tlbiw,+xs < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+tlbiw < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
-// RUN: | llvm-mc -triple=aarch64 -mattr=+tlbiw,+xs -disassemble -show-encoding \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+tlbiw -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
@@ -34,17 +34,17 @@ tlbi VMALLWS2E1OS
tlbi VMALLWS2E1nXS
// CHECK-INST: tlbi vmallws2e1nxs
// CHECK-ENCODING: encoding: [0x5f,0x96,0x0c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:6: error: TLBI VMALLWS2E1nXS requires: xs, tlbiw
+// CHECK-ERROR: :[[@LINE-3]]:6: error: TLBI VMALLWS2E1nXS requires: tlbiw
// CHECK-UNKNOWN: d50c965f sys #4, c9, c6, #2
tlbi VMALLWS2E1ISnXS
// CHECK-INST: tlbi vmallws2e1isnxs
// CHECK-ENCODING: encoding: [0x5f,0x92,0x0c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:6: error: TLBI VMALLWS2E1ISnXS requires: xs, tlbiw
+// CHECK-ERROR: :[[@LINE-3]]:6: error: TLBI VMALLWS2E1ISnXS requires: tlbiw
// CHECK-UNKNOWN: d50c925f sys #4, c9, c2, #2
tlbi VMALLWS2E1OSnXS
// CHECK-INST: tlbi vmallws2e1osnxs
// CHECK-ENCODING: encoding: [0x5f,0x95,0x0c,0xd5]
-// CHECK-ERROR: :[[@LINE-3]]:6: error: TLBI VMALLWS2E1OSnXS requires: xs, tlbiw
+// CHECK-ERROR: :[[@LINE-3]]:6: error: TLBI VMALLWS2E1OSnXS requires: tlbiw
// CHECK-UNKNOWN: d50c955f sys #4, c9, c5, #2
diff --git a/llvm/test/MC/AArch64/armv9a-tlbip.s b/llvm/test/MC/AArch64/armv9a-tlbip.s
index 7985b3d0c2e2e..263059cb7a007 100644
--- a/llvm/test/MC/AArch64/armv9a-tlbip.s
+++ b/llvm/test/MC/AArch64/armv9a-tlbip.s
@@ -1,19 +1,18 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+tlb-rmi < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
-// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+tlb-rmi < %s 2>&1 \
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128,+tlb-rmi < %s \
-// RUN: | llvm-objdump -d --mattr=+d128,+tlb-rmi --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128,+tlb-rmi < %s \
-// RUN: | llvm-objdump -d --mattr=-d128,-tlb-rmi --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128 < %s \
+// RUN: | llvm-objdump -d --mattr=+d128 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128 < %s \
+// RUN: | llvm-objdump -d --mattr=-d128 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+tlb-rmi < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
-// RUN: | llvm-mc -triple=aarch64 -mattr=+d128,+tlb-rmi -disassemble -show-encoding \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+d128 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// +d128 required for tlbip
-// +tbl-rmi required for RIPA*/RVA*
tlbip IPAS2E1, x4, x5
// CHECK-INST: tlbip ipas2e1, x4, x5
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