[llvm] [CodeGen][AMDGPU] Insert IMPLICIT_DEF for undef subreg operands in REG_SEQUENCE and preserve them during register coalescing (PR #189153)

[Matt Arsenault via llvm-commits]

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@@ -2876,7 +2876,10 @@ JoinVals::ConflictResolution JoinVals::analyzeValue(unsigned ValNo,
         //
         // Clearing the valid lanes is deferred until it is sure this can be
         // erased.
-        V.ErasableImplicitDef = true;
+        // IMPLICIT_DEF can also be used to initialize the undef sub-parts
+        // of a tuple. We want to retain those IMPLICIT_DEFs.
+        if (DefMI->getOperand(0).getSubReg() == 0)
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arsenm wrote:

See the above comment - this should still be treated as erasable. 

https://github.com/llvm/llvm-project/pull/189153