[llvm] [SelectionDAG] Expand CTTZ_ELTS[_ZERO_POISON] and handle legalization (PR #188691)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 30 04:08:25 PDT 2026
================
@@ -12591,6 +12600,34 @@ SDValue TargetLowering::expandVECTOR_COMPRESS(SDNode *Node,
return DAG.getLoad(VecVT, DL, Chain, StackPtr, PtrInfo);
}
+SDValue TargetLowering::expandCttzElts(SDNode *Node, SelectionDAG &DAG) const {
+ SDLoc DL(Node);
+ EVT VT = Node->getValueType(0);
+
+ bool ZeroIsPoison = Node->getOpcode() == ISD::CTTZ_ELTS_ZERO_POISON;
+ auto [Mask, StepVec] =
+ getLegalStepVector(Node->getOperand(0), ZeroIsPoison, DL, DAG);
+ EVT StepVecVT = StepVec.getValueType();
+ EVT StepVT = StepVecVT.getVectorElementType();
+
+ // Promote the scalar result type early to avoid redundant zexts.
+ if (getTypeAction(StepVT.getSimpleVT()) == TypePromoteInteger)
+ StepVT = getTypeToTransformTo(*DAG.getContext(), StepVT);
+
+ SDValue VL =
+ DAG.getElementCount(DL, StepVT, StepVecVT.getVectorElementCount());
+ SDValue SplatVL = DAG.getSplat(StepVecVT, DL, VL);
+ StepVec = DAG.getNode(ISD::SUB, DL, StepVecVT, SplatVL, StepVec);
+ SDValue Zeroes = DAG.getConstant(0, DL, StepVecVT);
+ SDValue Select = DAG.getSelect(DL, StepVecVT, Mask, StepVec, Zeroes);
+ SDValue Max = DAG.getNode(ISD::VECREDUCE_UMAX, DL,
+ StepVecVT.getVectorElementType(), Select);
----------------
lukel97 wrote:
StepVT might be promoted earlier on line 12615 which would leave the high bits of the result undefined IIUC, I think that was an issue that was caught during the review of the original PR https://github.com/llvm/llvm-project/pull/185605#discussion_r2975245012
https://github.com/llvm/llvm-project/pull/188691
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