[llvm] [RegisterScavenging] Respect early-clobber when scavenging registers (PR #184814)

[Dominik Steenken via llvm-commits]

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@@ -299,10 +299,34 @@ Register RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
   const MachineBasicBlock &MBB = *To->getParent();
   const MachineFunction &MF = *MBB.getParent();
 
+  // Obtain a list of candidate registers in allocation order of RC.
+  // If the instruction at MBBI has any early-clobber def regs, we must exclude
+  // them from the candidates, without including the whole of that instruction's
+  // constraints. We achieve this by filtering the allocation order of RC.
+  // First, determine if there are any such early-clobber def regs.
+  SmallVector<MCPhysReg> FilteredAllocationOrder;
+  SmallVector<MCPhysReg> ECDefs;
+  if ((MBBI != MBB.end()) && (MBBI != MBB.begin()))
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dominik-steenken wrote:

Ok, i have updated the code so that the need for looking at MBBI now derives from `NextInstructionNeedsVReg`. This required threading a new parm through into `scavengeRegisterBackwards`, but defaulting to `false` keeps the needed changes to a minimum.

With this update, the `AMDGPU` test no longer needs a change in this PR. Could you please take another look?

https://github.com/llvm/llvm-project/pull/184814