[llvm] AMDGPU: Skip last corrections in afn f64 reciprocal (PR #183696)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 28 11:22:19 PDT 2026
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/183696
>From 9015a18594bb8488cd02c382564ee4c43cd1a799 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 26 Feb 2026 21:39:55 +0100
Subject: [PATCH] AMDGPU: Skip last corrections in afn f64 reciprocal
Device libs has a fast reciprocal macro that is close
to the fast division expansion, but skips the last terms
compared to the full division.
The basic reciprocal handling has identical output to this
macro. The negative reciprocal case has different fneg placement
and smaller code size, but I believe should be the same.
---
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 18 ++-
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 17 +-
.../CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll | 44 +++++-
llvm/test/CodeGen/AMDGPU/fdiv.f64.ll | 14 +-
llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll | 4 -
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll | 2 -
llvm/test/CodeGen/AMDGPU/rsq.f64.ll | 148 ++++--------------
7 files changed, 114 insertions(+), 133 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index c78ef16b00983..089ee01763d0d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -5493,12 +5493,21 @@ bool AMDGPULegalizerInfo::legalizeFastUnsafeFDIV64(MachineInstr &MI,
if (!AllowInaccurateRcp)
return false;
- auto NegY = B.buildFNeg(ResTy, Y);
+ const ConstantFP *CLHS = getConstantFPVRegVal(X, MRI);
+ bool IsNegRcp = CLHS && CLHS->isExactlyValue(-1.0);
+
+ // Pull out the negation so it folds for free into the source modifiers.
+ if (IsNegRcp)
+ X = B.buildFConstant(ResTy, 1.0).getReg(0);
+
+ Register NegY = IsNegRcp ? Y : B.buildFNeg(ResTy, Y).getReg(0);
auto One = B.buildFConstant(ResTy, 1.0);
auto R = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {ResTy})
.addUse(Y)
.setMIFlags(Flags);
+ if (IsNegRcp)
+ R = B.buildFNeg(ResTy, R);
auto Tmp0 = B.buildFMA(ResTy, NegY, R, One);
R = B.buildFMA(ResTy, Tmp0, R, R);
@@ -5506,6 +5515,13 @@ bool AMDGPULegalizerInfo::legalizeFastUnsafeFDIV64(MachineInstr &MI,
auto Tmp1 = B.buildFMA(ResTy, NegY, R, One);
R = B.buildFMA(ResTy, Tmp1, R, R);
+ // Skip the last 2 correction terms for reciprocal.
+ if (IsNegRcp || (CLHS && CLHS->isExactlyValue(1.0))) {
+ B.buildCopy(Res, R);
+ MI.eraseFromParent();
+ return true;
+ }
+
auto Ret = B.buildFMul(ResTy, X, R);
auto Tmp2 = B.buildFMA(ResTy, NegY, Ret, X);
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 0bc509c4a6b29..343fe178c07a5 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -12785,15 +12785,30 @@ SDValue SITargetLowering::lowerFastUnsafeFDIV64(SDValue Op,
if (!AllowInaccurateDiv)
return SDValue();
- SDValue NegY = DAG.getNode(ISD::FNEG, SL, VT, Y);
+ const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(X);
+ bool IsNegRcp = CLHS && CLHS->isExactlyValue(-1.0);
+
+ // Pull out the negation so it folds for free into the source modifiers.
+ if (IsNegRcp)
+ X = DAG.getConstantFP(1.0, SL, VT);
+
+ SDValue NegY = IsNegRcp ? Y : DAG.getNode(ISD::FNEG, SL, VT, Y);
SDValue One = DAG.getConstantFP(1.0, SL, VT);
SDValue R = DAG.getNode(AMDGPUISD::RCP, SL, VT, Y);
+ if (IsNegRcp)
+ R = DAG.getNode(ISD::FNEG, SL, VT, R);
+
SDValue Tmp0 = DAG.getNode(ISD::FMA, SL, VT, NegY, R, One);
R = DAG.getNode(ISD::FMA, SL, VT, Tmp0, R, R);
SDValue Tmp1 = DAG.getNode(ISD::FMA, SL, VT, NegY, R, One);
R = DAG.getNode(ISD::FMA, SL, VT, Tmp1, R, R);
+
+ // Skip the last 2 correction terms for reciprocal.
+ if (IsNegRcp || (CLHS && CLHS->isExactlyValue(1.0)))
+ return R;
+
SDValue Ret = DAG.getNode(ISD::FMUL, SL, VT, X, R);
SDValue Tmp2 = DAG.getNode(ISD::FMA, SL, VT, NegY, Ret, X);
return DAG.getNode(ISD::FMA, SL, VT, Tmp2, R, Ret);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
index 3f6a6ac44f543..776226549048e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
@@ -438,8 +438,6 @@ define double @v_rcp_f64_arcp_afn(double %x) {
; GCN-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; GCN-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GCN-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; GCN-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; GCN-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; GCN-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; GCN-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; GCN-NEXT: s_setpc_b64 s[30:31]
@@ -450,8 +448,6 @@ define double @v_rcp_f64_arcp_afn(double %x) {
; GFX10-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; GFX10-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX10-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; GFX10-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; GFX10-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; GFX10-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; GFX10-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -464,9 +460,6 @@ define double @v_rcp_f64_arcp_afn(double %x) {
; GFX11-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; GFX11-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; GFX11-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
@@ -475,6 +468,43 @@ define double @v_rcp_f64_arcp_afn(double %x) {
ret double %fdiv
}
+define double @v_neg_rcp_f64_afn(double %x) {
+; GCN-LABEL: v_neg_rcp_f64_afn:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
+; GCN-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; GCN-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; GCN-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; GCN-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_neg_rcp_f64_afn:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
+; GFX10-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; GFX10-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; GFX10-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; GFX10-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_neg_rcp_f64_afn:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+ %fdiv = fdiv afn double -1.0, %x
+ ret double %fdiv
+}
+
define double @v_rcp_f64_ulp25(double %x) {
; GFX6-LABEL: v_rcp_f64_ulp25:
; GFX6: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/fdiv.f64.ll b/llvm/test/CodeGen/AMDGPU/fdiv.f64.ll
index 11476a6aa862e..96dc7caa5b2ed 100644
--- a/llvm/test/CodeGen/AMDGPU/fdiv.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/fdiv.f64.ll
@@ -57,8 +57,6 @@ define double @v_fdiv_f64_afn(double %x, double %y) #0 {
; GCN: v_rcp_f64_e32 v[2:3], v[0:1]
; GCN: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GCN: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; GCN: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; GCN: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; GCN: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; GCN: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; GCN: s_setpc_b64
@@ -67,6 +65,18 @@ define double @v_rcp_f64_afn(double %x) #0 {
ret double %result
}
+; GCN-LABEL: {{^}}v_neg_rcp_f64_afn:
+; GCN: v_rcp_f64_e32 v[2:3], v[0:1]
+; GCN: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; GCN: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; GCN: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; GCN: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
+; GCN: s_setpc_b64
+define double @v_neg_rcp_f64_afn(double %x) #0 {
+ %result = fdiv afn double -1.0, %x
+ ret double %result
+}
+
; GCN-LABEL: {{^}}fdiv_f64_s_v:
define amdgpu_kernel void @fdiv_f64_s_v(ptr addrspace(1) %out, ptr addrspace(1) %in, double %num) #0 {
%den = load double, ptr addrspace(1) %in
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
index e1fef9083e132..3cbde439cdf99 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
@@ -721,8 +721,6 @@ define amdgpu_ps double @fneg_fadd_0_nsz_f64(double inreg %tmp2, double inreg %t
; SI-NEXT: v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
; SI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
; SI-NEXT: v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
-; SI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
-; SI-NEXT: v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
; SI-NEXT: s_brev_b32 s3, 1
@@ -744,8 +742,6 @@ define amdgpu_ps double @fneg_fadd_0_nsz_f64(double inreg %tmp2, double inreg %t
; VI-NEXT: v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
; VI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
; VI-NEXT: v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
-; VI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
-; VI-NEXT: v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
; VI-NEXT: s_mov_b32 s2, 0
; VI-NEXT: s_brev_b32 s3, 1
; VI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
index 130de84a9407d..58cac9e3c8cf3 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
@@ -145,8 +145,6 @@ define amdgpu_kernel void @rcp_pat_f64(ptr addrspace(1) %out, double %src) #1 {
; SI: v_fma_f64
; SI: v_fma_f64
; SI: v_fma_f64
-; SI: v_fma_f64
-; SI: v_fma_f64
define amdgpu_kernel void @unsafe_rcp_pat_f64(ptr addrspace(1) %out, double %src) #2 {
%rcp = fdiv afn double 1.0, %src
store double %rcp, ptr addrspace(1) %out, align 8
diff --git a/llvm/test/CodeGen/AMDGPU/rsq.f64.ll b/llvm/test/CodeGen/AMDGPU/rsq.f64.ll
index 238cff87f2d5f..6602956f6fc89 100644
--- a/llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/rsq.f64.ll
@@ -3786,8 +3786,6 @@ define double @v_rsq_f64__afn_fdiv(double %x) {
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -3821,8 +3819,6 @@ define double @v_rsq_f64__afn_fdiv(double %x) {
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -3856,8 +3852,6 @@ define double @v_rsq_f64__afn_fdiv(double %x) {
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -3891,8 +3885,6 @@ define double @v_rsq_f64__afn_fdiv(double %x) {
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -3988,8 +3980,6 @@ define double @v_rsq_f64__afn(double %x) {
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4012,8 +4002,6 @@ define double @v_rsq_f64__afn(double %x) {
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4036,8 +4024,6 @@ define double @v_rsq_f64__afn(double %x) {
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4060,8 +4046,6 @@ define double @v_rsq_f64__afn(double %x) {
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4155,13 +4139,10 @@ define double @v_neg_rsq_f64__afn(double %x) {
; SI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_mul_f64 v[4:5], v[2:3], -1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[4:5], -1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
+; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
;
; SI-GISEL-CG-LABEL: v_neg_rsq_f64__afn:
@@ -4180,12 +4161,10 @@ define double @v_neg_rsq_f64__afn(double %x) {
; SI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -v[2:3]
+; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-CG-LABEL: v_neg_rsq_f64__afn:
@@ -4204,13 +4183,10 @@ define double @v_neg_rsq_f64__afn(double %x) {
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_mul_f64 v[4:5], v[2:3], -1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[4:5], -1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
+; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-CG-LABEL: v_neg_rsq_f64__afn:
@@ -4229,12 +4205,10 @@ define double @v_neg_rsq_f64__afn(double %x) {
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -v[2:3]
+; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract afn double @llvm.sqrt.f64(double %x)
%rsq = fdiv contract afn double -1.0, %sqrt
@@ -4311,8 +4285,6 @@ define double @v_rsq_f64__afn_ninf(double %x) {
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4334,8 +4306,6 @@ define double @v_rsq_f64__afn_ninf(double %x) {
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4357,8 +4327,6 @@ define double @v_rsq_f64__afn_ninf(double %x) {
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4380,8 +4348,6 @@ define double @v_rsq_f64__afn_ninf(double %x) {
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4477,8 +4443,6 @@ define double @v_rsq_f64__afn_nnan(double %x) {
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4501,8 +4465,6 @@ define double @v_rsq_f64__afn_nnan(double %x) {
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4525,8 +4487,6 @@ define double @v_rsq_f64__afn_nnan(double %x) {
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4549,8 +4509,6 @@ define double @v_rsq_f64__afn_nnan(double %x) {
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4629,8 +4587,6 @@ define double @v_rsq_f64__afn_nnan_ninf(double %x) {
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4652,8 +4608,6 @@ define double @v_rsq_f64__afn_nnan_ninf(double %x) {
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4675,8 +4629,6 @@ define double @v_rsq_f64__afn_nnan_ninf(double %x) {
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4698,8 +4650,6 @@ define double @v_rsq_f64__afn_nnan_ninf(double %x) {
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -4776,13 +4726,10 @@ define double @v_neg_rsq_f64__afn_nnan_ninf(double %x) {
; SI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_mul_f64 v[4:5], v[2:3], -1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[4:5], -1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
+; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
;
; SI-GISEL-CG-LABEL: v_neg_rsq_f64__afn_nnan_ninf:
@@ -4800,12 +4747,10 @@ define double @v_neg_rsq_f64__afn_nnan_ninf(double %x) {
; SI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -v[2:3]
+; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-CG-LABEL: v_neg_rsq_f64__afn_nnan_ninf:
@@ -4823,13 +4768,10 @@ define double @v_neg_rsq_f64__afn_nnan_ninf(double %x) {
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-SDAG-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_mul_f64 v[4:5], v[2:3], -1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[4:5], -1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
+; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-CG-LABEL: v_neg_rsq_f64__afn_nnan_ninf:
@@ -4847,12 +4789,10 @@ define double @v_neg_rsq_f64__afn_nnan_ninf(double %x) {
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-GISEL-CG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -v[2:3]
+; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], v[0:1], -v[2:3], 1.0
+; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], -v[2:3], -v[2:3]
+; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], 1.0
+; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract afn nnan ninf double @llvm.sqrt.f64(double %x)
%rsq = fdiv contract afn nnan ninf double -1.0, %sqrt
@@ -5183,10 +5123,6 @@ define <2 x double> @v_rsq_v2f64__afn_nnan_ninf(<2 x double> %x) {
; SI-SDAG-CG-NEXT: v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[6:7], v[10:11], v[6:7], v[6:7]
; SI-SDAG-CG-NEXT: v_fma_f64 v[8:9], -v[0:1], v[4:5], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[4:5]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[6:7], v[10:11], v[6:7], v[6:7]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[8:9], -v[0:1], v[4:5], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[4:5]
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[6:7]
@@ -5266,10 +5202,6 @@ define <2 x double> @v_rsq_v2f64__afn_nnan_ninf(<2 x double> %x) {
; VI-SDAG-CG-NEXT: v_fma_f64 v[11:12], -v[2:3], v[7:8], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], v[9:10], v[5:6], v[5:6]
; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], v[11:12], v[7:8], v[7:8]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[8:9], -v[0:1], v[4:5], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[4:5]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[6:7], v[10:11], v[6:7], v[6:7]
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[4:5], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], v[4:5]
@@ -5421,8 +5353,6 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_unsafe(double inreg %x) {
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: v_readfirstlane_b32 s0, v0
@@ -5448,8 +5378,6 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_unsafe(double inreg %x) {
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: v_readfirstlane_b32 s0, v0
@@ -5475,8 +5403,6 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_unsafe(double inreg %x) {
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: v_readfirstlane_b32 s0, v0
@@ -5502,8 +5428,6 @@ define amdgpu_ps <2 x i32> @s_rsq_f64_unsafe(double inreg %x) {
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: v_readfirstlane_b32 s0, v0
@@ -5608,8 +5532,6 @@ define double @v_rsq_f64_unsafe(double %x) {
; SI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -5632,8 +5554,6 @@ define double @v_rsq_f64_unsafe(double %x) {
; SI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; SI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; SI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; SI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
@@ -5656,8 +5576,6 @@ define double @v_rsq_f64_unsafe(double %x) {
; VI-SDAG-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-SDAG-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-SDAG-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-SDAG-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-SDAG-CG-NEXT: s_setpc_b64 s[30:31]
@@ -5680,8 +5598,6 @@ define double @v_rsq_f64_unsafe(double %x) {
; VI-GISEL-CG-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
-; VI-GISEL-CG-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-GISEL-CG-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
; VI-GISEL-CG-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
; VI-GISEL-CG-NEXT: s_setpc_b64 s[30:31]
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