[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for wqm_vote, kill (PR #188382)

[via llvm-commits]

================
@@ -1,59 +1,254 @@
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=CHECK,WAVE64 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=CHECK,WAVE64 %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=CHECK,WAVE32 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=CHECK,WAVE32 %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=CHECK,WAVE32 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=CHECK,WAVE32 %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=WAVE64,WAVE64-SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=WAVE64,WAVE64-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
 
-;CHECK-LABEL: {{^}}ret:
-;CHECK: v_cmp_eq_u32_e32 [[CMP:[^,]+]], v0, v1
-;WAVE64: s_wqm_b64 [[WQM:[^,]+]], [[CMP]]
-;WAVE32: s_wqm_b32 [[WQM:[^,]+]], [[CMP]]
-;CHECK: v_cndmask_b32_e64 v0, 0, 1.0, [[WQM]]
 define amdgpu_ps float @ret(i32 %v0, i32 %v1) #1 {
+; WAVE64-LABEL: ret:
+; WAVE64:       ; %bb.0: ; %main_body
+; WAVE64-NEXT:    v_cmp_eq_u32_e32 vcc, v0, v1
+; WAVE64-NEXT:    s_wqm_b64 s[0:1], vcc
+; WAVE64-NEXT:    v_cndmask_b32_e64 v0, 0, 1.0, s[0:1]
+; WAVE64-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: ret:
+; GFX10:       ; %bb.0: ; %main_body
+; GFX10-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v0, v1
+; GFX10-NEXT:    s_wqm_b32 s0, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1.0, s0
+; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX11-LABEL: ret:
+; GFX11:       ; %bb.0: ; %main_body
+; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v0, v1
+; GFX11-NEXT:    s_wqm_b32 s0, vcc_lo
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1.0, s0
+; GFX11-NEXT:    ; return to shader part epilog
 main_body:
   %c = icmp eq i32 %v0, %v1
   %w = call i1 @llvm.amdgcn.wqm.vote(i1 %c)
   %r = select i1 %w, float 1.0, float 0.0
   ret float %r
 }
 
-;CHECK-LABEL: {{^}}true:
-;WAVE64: s_wqm_b64
-;WAVE32: s_wqm_b32
 define amdgpu_ps float @true() #1 {
+; WAVE64-SDAG-LABEL: true:
+; WAVE64-SDAG:       ; %bb.0: ; %main_body
+; WAVE64-SDAG-NEXT:    s_wqm_b64 s[0:1], -1
+; WAVE64-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1.0, s[0:1]
+; WAVE64-SDAG-NEXT:    ; return to shader part epilog
+;
+; WAVE64-GISEL-LABEL: true:
+; WAVE64-GISEL:       ; %bb.0: ; %main_body
+; WAVE64-GISEL-NEXT:    s_wqm_b64 s[0:1], exec
+; WAVE64-GISEL-NEXT:    s_cselect_b32 s0, 1.0, 0
+; WAVE64-GISEL-NEXT:    v_mov_b32_e32 v0, s0
+; WAVE64-GISEL-NEXT:    ; return to shader part epilog
+;
+; GFX10-SDAG-LABEL: true:
+; GFX10-SDAG:       ; %bb.0: ; %main_body
+; GFX10-SDAG-NEXT:    s_wqm_b32 s0, -1
+; GFX10-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1.0, s0
+; GFX10-SDAG-NEXT:    ; return to shader part epilog
+;
+; GFX10-GISEL-LABEL: true:
+; GFX10-GISEL:       ; %bb.0: ; %main_body
+; GFX10-GISEL-NEXT:    s_wqm_b32 s0, exec_lo
+; GFX10-GISEL-NEXT:    s_cselect_b32 s0, 1.0, 0
+; GFX10-GISEL-NEXT:    v_mov_b32_e32 v0, s0
+; GFX10-GISEL-NEXT:    ; return to shader part epilog
+;
+; GFX11-SDAG-LABEL: true:
+; GFX11-SDAG:       ; %bb.0: ; %main_body
+; GFX11-SDAG-NEXT:    s_wqm_b32 s0, -1
+; GFX11-SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1.0, s0
+; GFX11-SDAG-NEXT:    ; return to shader part epilog
+;
+; GFX11-GISEL-LABEL: true:
+; GFX11-GISEL:       ; %bb.0: ; %main_body
+; GFX11-GISEL-NEXT:    s_wqm_b32 s0, exec_lo
+; GFX11-GISEL-NEXT:    s_cselect_b32 s0, 1.0, 0
----------------
vangthao95 wrote:

Hi @jayfoad, can you confirm we don't need any special handling here? Result from wqm is being treated as uniform in SCC and this would set 1.0 for all lanes, even dead ones.

https://github.com/llvm/llvm-project/pull/188382