[llvm] [X86] Add alwaysILP tuning flag (PR #189034)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-x86

Author: Gergo Stomfai (stomfaig)

<details>
<summary>Changes</summary>

part of #<!-- -->62952

---
Full diff: https://github.com/llvm/llvm-project/pull/189034.diff


2 Files Affected:

- (modified) llvm/lib/Target/X86/X86.td (+5-1) 
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+3-3) 


``````````diff
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index c42d3453e0729..d275985369395 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -798,6 +798,9 @@ def TuningPreferLegacySetCC
     : SubtargetFeature<"prefer-legacy-setcc", "PreferLegacySetCC", "true",
                        "Prefer to emit legacy SetCC.">;
 
+def TuningAlwaysILP : SubtargetFeature<"always-ilp", "AlwaysILP", "true",
+                       "Always use ILP instruction selection.">;
+
 //===----------------------------------------------------------------------===//
 // X86 CPU Families
 // TODO: Remove these - use general tuning features to determine codegen.
@@ -1231,7 +1234,8 @@ def ProcessorFeatures {
                                        TuningLEAUsesAG,
                                        TuningPadShortFunctions,
                                        TuningInsertVZEROUPPER,
-                                       TuningNoDomainDelay];
+                                       TuningNoDomainDelay,
+                                       TuningAlwaysILP];
 
   // Silvermont
   list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42,
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 76bb9db5c5b85..3f689acca4365 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -146,9 +146,9 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
   setOperationAction(ISD::CLEAR_CACHE, MVT::Other, Expand);
 
   // For 64-bit, since we have so many registers, use the ILP scheduler.
-  // For 32-bit, use the register pressure specific scheduling.
-  // For Atom, always use ILP scheduling.
-  if (Subtarget.isAtom())
+  // For 32-bit, use the register pressure specific scheduling, unless
+  // target wants ILP (e.g. Atom)
+  if (Subtarget.alwaysILP())
     setSchedulingPreference(Sched::ILP);
   else if (Subtarget.is64Bit())
     setSchedulingPreference(Sched::ILP);

``````````

</details>


https://github.com/llvm/llvm-project/pull/189034