[llvm] [SDAG][X86] Uplift pseudo fmin/fmax from X86 (PR #188489)

[Nikita Popov via llvm-commits]

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@@ -175,7 +175,7 @@ define float @test_v16f32(<16 x float> %a0) {
 ; AVX512-LABEL: test_v16f32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vextractf64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT:    vmaxps %ymm1, %ymm0, %ymm0
+; AVX512-NEXT:    vmaxps %zmm1, %zmm0, %zmm0
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nikic wrote:

Doing this in EXTRACT_SUBVECTOR doesn't work out because there's two extracts here.

I tried adding an API that allows specifying the preferred size for an op: https://gist.github.com/nikic/587bd14df076cccfe4cc1e38277afb21

This does work to recover these cases. I was struggling to find an existing op for which this doesn't cause regressions though (I found fsub, so I could submit it separately with that). For things like add this causes regressions, mostly for hadd and sadb patterns.

Do you think this kind of API would make sense?

An alternative would be to just allow targets to hook into demanded element simplification even for non-target nodes. (I don't think there's any particular reason we have to prevent this? After all we can register DAG combines for any node, not just target nodes.)

https://github.com/llvm/llvm-project/pull/188489