[llvm] [AMDGPU][SILowerSGPRSpills] Correct insertion of IMPLICIT_DEF in cycle headers (PR #186348)

[Chris Jackson via llvm-commits]

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@@ -340,6 +366,13 @@ void SILowerSGPRSpills::updateLaneVGPRDomInstr(
       // Find the common dominator block between PrevInsertPt and the
       // current spill.
       DomMBB = MDT->findNearestCommonDominator(DomMBB, MBB);
+      // If the insertion point is a cycle header move it to the preheader.
+      // This ensures the IMPLICIT_DEF dominates and is live-in to the header.
+      // WWM regalloc will then insert a wwm restore in the header.
+      MachineCycle *C = MCI->getCycle(DomMBB);
+      if (C && C->isEntry(DomMBB))
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chrisjbris wrote:

I've added the functionality to support moving the IMPLICIT_DEF from any block in the cycle, not just the header. However the code is more complex as I found cases where the new target block for the insertion point was empty. Of course I could add functionality to populate the block and add IMPLICIT_DEF but I think the implementation is complex enough now.

https://github.com/llvm/llvm-project/pull/186348