[llvm] d5824db - [AMDGPU] Rework NeedNopBeforeSetVGPRMSB flag. NFC. (#187520)

[via llvm-commits]

Author: Jay Foad
Date: 2026-03-26T12:09:09Z
New Revision: d5824db2d42db188aa16d72342f3bd08b897730c

URL: https://github.com/llvm/llvm-project/commit/d5824db2d42db188aa16d72342f3bd08b897730c
DIFF: https://github.com/llvm/llvm-project/commit/d5824db2d42db188aa16d72342f3bd08b897730c.diff

LOG: [AMDGPU] Rework NeedNopBeforeSetVGPRMSB flag. NFC. (#187520)

This avoids tracking state with a flag when it is conceptually simpler
to look at the preceding instructions to detemine whether a NOP is
needed.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
index f9e21f2a77879..bcac1dc35ae53 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
@@ -159,11 +159,6 @@ class AMDGPULowerVGPREncoding {
   // instruction that we inserted, which implicitly waits for XCNT==0.
   bool XCntIsZero;
 
-  /// S_SET_VGPR_MSB immediately after S_SETREG_IMM32_B32 targeting MODE is
-  /// silently dropped on GFX1250. When set, the next S_SET_VGPR_MSB insertion
-  /// must be preceded by S_NOP to avoid the hazard.
-  bool NeedNopBeforeSetVGPRMSB;
-
   /// Insert mode change before \p I. \returns true if mode was changed.
   bool setMode(ModeTy NewMode, MachineBasicBlock::instr_iterator I);
 
@@ -201,6 +196,11 @@ class AMDGPULowerVGPREncoding {
   MachineBasicBlock::instr_iterator
   handleCoissue(MachineBasicBlock::instr_iterator I);
 
+  /// S_SET_VGPR_MSB immediately after S_SETREG_IMM32_B32 targeting MODE is
+  /// silently dropped on GFX1250. When set, the next S_SET_VGPR_MSB insertion
+  /// must be preceded by S_NOP to avoid the hazard.
+  bool needNopBeforeSetVGPRMSB(MachineBasicBlock::instr_iterator I);
+
   /// Handle S_SETREG_IMM32_B32 targeting MODE register. On certain hardware,
   /// this instruction clobbers VGPR MSB bits[12:19], so we need to restore
   /// the current mode. \returns true if the instruction was modified or a
@@ -264,10 +264,8 @@ bool AMDGPULowerVGPREncoding::setMode(ModeTy NewMode,
   // current MSBs, but the next VALU needs 
diff erent MSBs, so this
   // S_SET_VGPR_MSB would land right after the setreg. Insert S_NOP to
   // prevent it from being silently dropped.
-  if (NeedNopBeforeSetVGPRMSB) {
+  if (needNopBeforeSetVGPRMSB(I))
     BuildMI(*MBB, InsertPt, {}, TII->get(AMDGPU::S_NOP)).addImm(0);
-    NeedNopBeforeSetVGPRMSB = false;
-  }
   MostRecentModeSet =
       BuildMI(*MBB, InsertPt, {}, TII->get(AMDGPU::S_SET_VGPR_MSB))
           .addImm(NewMode.encode() | OldModeBits);
@@ -444,6 +442,26 @@ AMDGPULowerVGPREncoding::handleCoissue(MachineBasicBlock::instr_iterator I) {
   return I;
 }
 
+bool AMDGPULowerVGPREncoding::needNopBeforeSetVGPRMSB(
+    MachineBasicBlock::instr_iterator I) {
+  while (I != MBB->begin()) {
+    I = std::prev(I);
+    if (I->getOpcode() == AMDGPU::S_SETREG_IMM32_B32) {
+      MachineOperand *SIMM16Op =
+          TII->getNamedOperand(*I, AMDGPU::OpName::simm16);
+      auto [HwRegId, Offset, Size] =
+          AMDGPU::Hwreg::HwregEncoding::decode(SIMM16Op->getImm());
+      if (HwRegId == AMDGPU::Hwreg::ID_MODE)
+        return true;
+    }
+    if (!I->isMetaInstruction())
+      return false;
+  }
+  // FIXME: Return true if the previous MBB falls through and ends with
+  // S_SETREG_IMM32_B32.
+  return false;
+}
+
 /// Convert mode value from S_SET_VGPR_MSB format to MODE register format.
 /// S_SET_VGPR_MSB uses: (src0[0-1], src1[2-3], src2[4-5], dst[6-7])
 /// MODE register uses:  (dst[0-1], src0[2-3], src1[4-5], src2[6-7])
@@ -532,7 +550,6 @@ bool AMDGPULowerVGPREncoding::handleSetregMode(MachineInstr &MI) {
     // via piggybacking (bits[12:19] are meaningful), so if CurrentMode changes,
     // a new s_set_vgpr_msb will be inserted after this instruction.
     MostRecentModeSet = nullptr;
-    NeedNopBeforeSetVGPRMSB = true;
     LLVM_DEBUG(dbgs() << "    -> bits[12:19] already correct, "
                          "invalidated MostRecentModeSet\n");
     return false;
@@ -569,7 +586,6 @@ bool AMDGPULowerVGPREncoding::run(MachineFunction &MF) {
   for (auto &MBB : MF) {
     MostRecentModeSet = nullptr;
     XCntIsZero = false;
-    NeedNopBeforeSetVGPRMSB = false;
     this->MBB = &MBB;
 
     LLVM_DEBUG(dbgs() << "BB#" << MBB.getNumber() << ' ' << MBB.getName()
@@ -586,7 +602,6 @@ bool AMDGPULowerVGPREncoding::run(MachineFunction &MF) {
           CurrentMode = {};
         else
           resetMode(MI.getIterator());
-        NeedNopBeforeSetVGPRMSB = false;
         continue;
       }
 
@@ -594,7 +609,6 @@ bool AMDGPULowerVGPREncoding::run(MachineFunction &MF) {
         LLVM_DEBUG(dbgs() << "  inline asm: " << MI);
         if (TII->hasVGPRUses(MI))
           resetMode(MI.getIterator());
-        NeedNopBeforeSetVGPRMSB = false;
         continue;
       }
 
@@ -624,7 +638,6 @@ bool AMDGPULowerVGPREncoding::run(MachineFunction &MF) {
       }
 
       Changed |= runOnMachineInstr(MI);
-      NeedNopBeforeSetVGPRMSB = false;
 
       // Any VMEM or SMEM instruction may increment XCNT.
       if (SIInstrInfo::isVMEM(MI) || SIInstrInfo::isSMRD(MI))