[clang] [compiler-rt] [llvm] [X86] Hygon Processors Initial enablement (PR #187622)
Xiaomeng Zhang via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 25 23:49:22 PDT 2026
https://github.com/zhangxiaomeng-hygon updated https://github.com/llvm/llvm-project/pull/187622
>From 8f803462d19fc97f4cb552aa6c79899e934b7a57 Mon Sep 17 00:00:00 2001
From: zhangxiaomeng <zhangxiaomeng at hygon.cn>
Date: Thu, 19 Mar 2026 15:49:38 +0800
Subject: [PATCH 1/7] [X86] Hygon Processors Initial enablement
This patch adds initial support for several Hygon architectures.
The Hygon architectures include:
c86-4g-m4
c86-4g-m6
c86-4g-m7
This patch includes:
Added Hygon architectures CPU targets recognition in Clang and LLVM
Added Hygon architectures to target parser and host CPU detection
Updated compiler-rt CPU model detection for Hygon architectures
Added Hygon architectures to various optimizer tests
---
clang/lib/Basic/Targets/X86.cpp | 13 +
clang/test/CodeGen/target-builtin-noerror.c | 3 +
clang/test/Driver/x86-march.c | 12 +
clang/test/Frontend/x86-target-cpu.c | 3 +
clang/test/Misc/target-invalid-cpu-note/x86.c | 12 +
.../Preprocessor/predefined-arch-macros.c | 298 ++++++++++++++++++
compiler-rt/lib/builtins/cpu_model/x86.c | 50 +++
llvm/include/llvm/TargetParser/Host.h | 1 +
.../llvm/TargetParser/X86TargetParser.def | 4 +
.../llvm/TargetParser/X86TargetParser.h | 3 +
llvm/lib/Target/X86/X86.td | 84 +++++
llvm/lib/TargetParser/Host.cpp | 40 +++
llvm/lib/TargetParser/X86TargetParser.cpp | 25 ++
.../CodeGen/X86/bypass-slow-division-64.ll | 3 +
llvm/test/CodeGen/X86/cmp16.ll | 3 +
llvm/test/CodeGen/X86/cpus-hygon.ll | 10 +
llvm/test/CodeGen/X86/rdpru.ll | 3 +
llvm/test/CodeGen/X86/slow-unaligned-mem.ll | 6 +
llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll | 3 +
.../X86/vector-shuffle-fast-per-lane.ll | 3 +
.../CodeGen/X86/x86-64-double-shifts-var.ll | 3 +
llvm/test/MC/X86/x86_long_nop.s | 6 +
22 files changed, 588 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/cpus-hygon.ll
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index cb941c94c84a7..fd30c7f8d61b9 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -729,6 +729,15 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
case CK_Geode:
defineCPUMacros(Builder, "geode");
break;
+ case CK_C86_4G_M4:
+ defineCPUMacros(Builder, "c86-4g-m4");
+ break;
+ case CK_C86_4G_M6:
+ defineCPUMacros(Builder, "c86-4g-m6");
+ break;
+ case CK_C86_4G_M7:
+ defineCPUMacros(Builder, "c86-4g-m7");
+ break;
}
// Target properties.
@@ -1657,6 +1666,10 @@ std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
case CK_ZNVER4:
case CK_ZNVER5:
case CK_ZNVER6:
+ // Hygon
+ case CK_C86_4G_M4:
+ case CK_C86_4G_M6:
+ case CK_C86_4G_M7:
// Deprecated
case CK_x86_64:
case CK_x86_64_v2:
diff --git a/clang/test/CodeGen/target-builtin-noerror.c b/clang/test/CodeGen/target-builtin-noerror.c
index a65a07d81b8c0..bb4c65991ab50 100644
--- a/clang/test/CodeGen/target-builtin-noerror.c
+++ b/clang/test/CodeGen/target-builtin-noerror.c
@@ -211,4 +211,7 @@ void verifycpustrings(void) {
(void)__builtin_cpu_is("znver5");
(void)__builtin_cpu_is("znver6");
(void)__builtin_cpu_is("diamondrapids");
+ (void)__builtin_cpu_is("c86-4g-m4");
+ (void)__builtin_cpu_is("c86-4g-m6");
+ (void)__builtin_cpu_is("c86-4g-m7");
}
diff --git a/clang/test/Driver/x86-march.c b/clang/test/Driver/x86-march.c
index 6a3ef5be67d8a..b05e025fca81c 100644
--- a/clang/test/Driver/x86-march.c
+++ b/clang/test/Driver/x86-march.c
@@ -263,6 +263,18 @@
// RUN: | FileCheck %s -check-prefix=znver6
// znver6: "-target-cpu" "znver6"
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=c86-4g-m4 2>&1 \
+// RUN: | FileCheck %s -check-prefix=c86-4g-m4
+// c86-4g-m4: "-target-cpu" "c86-4g-m4"
+
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=c86-4g-m6 2>&1 \
+// RUN: | FileCheck %s -check-prefix=c86-4g-m6
+// c86-4g-m6: "-target-cpu" "c86-4g-m6"
+
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=c86-4g-m7 2>&1 \
+// RUN: | FileCheck %s -check-prefix=c86-4g-m7
+// c86-4g-m7: "-target-cpu" "c86-4g-m7"
+
// RUN: %clang -target x86_64 -c -### %s -march=x86-64 2>&1 | FileCheck %s --check-prefix=x86-64
// x86-64: "-target-cpu" "x86-64"
// RUN: %clang -target x86_64 -c -### %s -march=x86-64-v2 2>&1 | FileCheck %s --check-prefix=x86-64-v2
diff --git a/clang/test/Frontend/x86-target-cpu.c b/clang/test/Frontend/x86-target-cpu.c
index 7dc7f5474687e..281e41c03c4d0 100644
--- a/clang/test/Frontend/x86-target-cpu.c
+++ b/clang/test/Frontend/x86-target-cpu.c
@@ -40,5 +40,8 @@
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver4 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver5 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver6 -verify %s
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu c86-4g-m4 -verify %s
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu c86-4g-m6 -verify %s
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu c86-4g-m7 -verify %s
//
// expected-no-diagnostics
diff --git a/clang/test/Misc/target-invalid-cpu-note/x86.c b/clang/test/Misc/target-invalid-cpu-note/x86.c
index 766bd679796f5..921c4b7c5cab0 100644
--- a/clang/test/Misc/target-invalid-cpu-note/x86.c
+++ b/clang/test/Misc/target-invalid-cpu-note/x86.c
@@ -104,6 +104,9 @@
// X86-SAME: {{^}}, znver4
// X86-SAME: {{^}}, znver5
// X86-SAME: {{^}}, znver6
+// X86-SAME: {{^}}, c86-4g-m4
+// X86-SAME: {{^}}, c86-4g-m6
+// X86-SAME: {{^}}, c86-4g-m7
// X86-SAME: {{^}}, x86-64
// X86-SAME: {{^}}, x86-64-v2
// X86-SAME: {{^}}, x86-64-v3
@@ -185,6 +188,9 @@
// X86_64-SAME: {{^}}, znver4
// X86_64-SAME: {{^}}, znver5
// X86_64-SAME: {{^}}, znver6
+// X86_64-SAME: {{^}}, c86-4g-m4
+// X86_64-SAME: {{^}}, c86-4g-m6
+// X86_64-SAME: {{^}}, c86-4g-m7
// X86_64-SAME: {{^}}, x86-64
// X86_64-SAME: {{^}}, x86-64-v2
// X86_64-SAME: {{^}}, x86-64-v3
@@ -293,6 +299,9 @@
// TUNE_X86-SAME: {{^}}, znver4
// TUNE_X86-SAME: {{^}}, znver5
// TUNE_X86-SAME: {{^}}, znver6
+// TUNE_X86-SAME: {{^}}, c86-4g-m4
+// TUNE_X86-SAME: {{^}}, c86-4g-m6
+// TUNE_X86-SAME: {{^}}, c86-4g-m7
// TUNE_X86-SAME: {{^}}, x86-64
// TUNE_X86-SAME: {{^}}, geode
// TUNE_X86-SAME: {{$}}
@@ -399,6 +408,9 @@
// TUNE_X86_64-SAME: {{^}}, znver4
// TUNE_X86_64-SAME: {{^}}, znver5
// TUNE_X86_64-SAME: {{^}}, znver6
+// TUNE_X86_64-SAME: {{^}}, c86-4g-m4
+// TUNE_X86_64-SAME: {{^}}, c86-4g-m6
+// TUNE_X86_64-SAME: {{^}}, c86-4g-m7
// TUNE_X86_64-SAME: {{^}}, x86-64
// TUNE_X86_64-SAME: {{^}}, geode
// TUNE_X86_64-SAME: {{$}}
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c
index cb2d13d59d8bf..bc950f5ecee9c 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -4287,6 +4287,304 @@
// CHECK_ZNVER6_M64: #define __znver6 1
// CHECK_ZNVER6_M64: #define __znver6__ 1
+// RUN: %clang -march=c86-4g-m4 -m32 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM4_M32
+// CHECK_C864GM4_M32: #define __ADX__ 1
+// CHECK_C864GM4_M32: #define __AES__ 1
+// CHECK_C864GM4_M32: #define __AVX2__ 1
+// CHECK_C864GM4_M32: #define __AVX__ 1
+// CHECK_C864GM4_M32: #define __BMI2__ 1
+// CHECK_C864GM4_M32: #define __BMI__ 1
+// CHECK_C864GM4_M32: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM4_M32: #define __CLZERO__ 1
+// CHECK_C864GM4_M32: #define __CRC32__ 1
+// CHECK_C864GM4_M32: #define __F16C__ 1
+// CHECK_C864GM4_M32: #define __FMA__ 1
+// CHECK_C864GM4_M32: #define __FSGSBASE__ 1
+// CHECK_C864GM4_M32: #define __FXSR__ 1
+// CHECK_C864GM4_M32: #define __LZCNT__ 1
+// CHECK_C864GM4_M32: #define __MMX__ 1
+// CHECK_C864GM4_M32: #define __MOVBE__ 1
+// CHECK_C864GM4_M32: #define __MWAITX__ 1
+// CHECK_C864GM4_M32: #define __PCLMUL__ 1
+// CHECK_C864GM4_M32: #define __POPCNT__ 1
+// CHECK_C864GM4_M32: #define __PRFCHW__ 1
+// CHECK_C864GM4_M32: #define __RDRND__ 1
+// CHECK_C864GM4_M32: #define __RDSEED__ 1
+// CHECK_C864GM4_M32: #define __SHA__ 1
+// CHECK_C864GM4_M32: #define __SSE2_MATH__ 1
+// CHECK_C864GM4_M32: #define __SSE2__ 1
+// CHECK_C864GM4_M32: #define __SSE3__ 1
+// CHECK_C864GM4_M32: #define __SSE4A__ 1
+// CHECK_C864GM4_M32: #define __SSE4_1__ 1
+// CHECK_C864GM4_M32: #define __SSE4_2__ 1
+// CHECK_C864GM4_M32: #define __SSE_MATH__ 1
+// CHECK_C864GM4_M32: #define __SSE__ 1
+// CHECK_C864GM4_M32: #define __SSSE3__ 1
+// CHECK_C864GM4_M32: #define __XSAVEC__ 1
+// CHECK_C864GM4_M32: #define __XSAVEOPT__ 1
+// CHECK_C864GM4_M32: #define __XSAVES__ 1
+// CHECK_C864GM4_M32: #define __XSAVE__ 1
+// CHECK_C864GM4_M32: #define __c86 -4g-m4__ 1
+// CHECK_C864GM4_M32: #define __i386 1
+// CHECK_C864GM4_M32: #define __i386__ 1
+// CHECK_C864GM4_M32: #define __tune_c86 -4g-m4__ 1
+
+// RUN: %clang -march=c86-4g-m4 -m64 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM4_M64
+// CHECK_C864GM4_M64: #define __ADX__ 1
+// CHECK_C864GM4_M64: #define __AES__ 1
+// CHECK_C864GM4_M64: #define __AVX2__ 1
+// CHECK_C864GM4_M64: #define __AVX__ 1
+// CHECK_C864GM4_M64: #define __BMI2__ 1
+// CHECK_C864GM4_M64: #define __BMI__ 1
+// CHECK_C864GM4_M64: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM4_M64: #define __CLZERO__ 1
+// CHECK_C864GM4_M64: #define __CRC32__ 1
+// CHECK_C864GM4_M64: #define __F16C__ 1
+// CHECK_C864GM4_M64: #define __FMA__ 1
+// CHECK_C864GM4_M64: #define __FSGSBASE__ 1
+// CHECK_C864GM4_M64: #define __FXSR__ 1
+// CHECK_C864GM4_M64: #define __LZCNT__ 1
+// CHECK_C864GM4_M64: #define __MMX__ 1
+// CHECK_C864GM4_M64: #define __MOVBE__ 1
+// CHECK_C864GM4_M64: #define __MWAITX__ 1
+// CHECK_C864GM4_M64: #define __PCLMUL__ 1
+// CHECK_C864GM4_M64: #define __POPCNT__ 1
+// CHECK_C864GM4_M64: #define __PRFCHW__ 1
+// CHECK_C864GM4_M64: #define __RDRND__ 1
+// CHECK_C864GM4_M64: #define __RDSEED__ 1
+// CHECK_C864GM4_M64: #define __SHA__ 1
+// CHECK_C864GM4_M64: #define __SSE2_MATH__ 1
+// CHECK_C864GM4_M64: #define __SSE2__ 1
+// CHECK_C864GM4_M64: #define __SSE3__ 1
+// CHECK_C864GM4_M64: #define __SSE4A__ 1
+// CHECK_C864GM4_M64: #define __SSE4_1__ 1
+// CHECK_C864GM4_M64: #define __SSE4_2__ 1
+// CHECK_C864GM4_M64: #define __SSE_MATH__ 1
+// CHECK_C864GM4_M64: #define __SSE__ 1
+// CHECK_C864GM4_M64: #define __SSSE3__ 1
+// CHECK_C864GM4_M64: #define __XSAVEC__ 1
+// CHECK_C864GM4_M64: #define __XSAVEOPT__ 1
+// CHECK_C864GM4_M64: #define __XSAVES__ 1
+// CHECK_C864GM4_M64: #define __XSAVE__ 1
+// CHECK_C864GM4_M64: #define __c86 -4g-m4__ 1
+// CHECK_C864GM4_M64: #define __tune_c86 -4g-m4__ 1
+// CHECK_C864GM4_M64: #define __x86_64 1
+// CHECK_C864GM4_M64: #define __x86_64__ 1
+
+// RUN: %clang -march=c86-4g-m6 -m32 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM6_M32
+// CHECK_C864GM6_M32: #define __ADX__ 1
+// CHECK_C864GM6_M32: #define __AES__ 1
+// CHECK_C864GM6_M32: #define __AVX2__ 1
+// CHECK_C864GM6_M32: #define __AVX__ 1
+// CHECK_C864GM6_M32: #define __BMI2__ 1
+// CHECK_C864GM6_M32: #define __BMI__ 1
+// CHECK_C864GM6_M32: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM6_M32: #define __CLZERO__ 1
+// CHECK_C864GM6_M32: #define __CRC32__ 1
+// CHECK_C864GM6_M32: #define __F16C__ 1
+// CHECK_C864GM6_M32: #define __FMA__ 1
+// CHECK_C864GM6_M32: #define __FSGSBASE__ 1
+// CHECK_C864GM6_M32: #define __FXSR__ 1
+// CHECK_C864GM6_M32: #define __LZCNT__ 1
+// CHECK_C864GM6_M32: #define __MMX__ 1
+// CHECK_C864GM6_M32: #define __MOVBE__ 1
+// CHECK_C864GM6_M32: #define __MWAITX__ 1
+// CHECK_C864GM6_M32: #define __PCLMUL__ 1
+// CHECK_C864GM6_M32: #define __POPCNT__ 1
+// CHECK_C864GM6_M32: #define __PRFCHW__ 1
+// CHECK_C864GM6_M32: #define __RDRND__ 1
+// CHECK_C864GM6_M32: #define __RDSEED__ 1
+// CHECK_C864GM6_M32: #define __SHA__ 1
+// CHECK_C864GM6_M32: #define __SSE2_MATH__ 1
+// CHECK_C864GM6_M32: #define __SSE2__ 1
+// CHECK_C864GM6_M32: #define __SSE3__ 1
+// CHECK_C864GM6_M32: #define __SSE4A__ 1
+// CHECK_C864GM6_M32: #define __SSE4_1__ 1
+// CHECK_C864GM6_M32: #define __SSE4_2__ 1
+// CHECK_C864GM6_M32: #define __SSE_MATH__ 1
+// CHECK_C864GM6_M32: #define __SSE__ 1
+// CHECK_C864GM6_M32: #define __SSSE3__ 1
+// CHECK_C864GM6_M32: #define __XSAVEC__ 1
+// CHECK_C864GM6_M32: #define __XSAVEOPT__ 1
+// CHECK_C864GM6_M32: #define __XSAVES__ 1
+// CHECK_C864GM6_M32: #define __XSAVE__ 1
+// CHECK_C864GM6_M32: #define __c86 -4g-m6__ 1
+// CHECK_C864GM6_M32: #define __i386 1
+// CHECK_C864GM6_M32: #define __i386__ 1
+// CHECK_C864GM6_M32: #define __tune_c86 -4g-m6__ 1
+
+// RUN: %clang -march=c86-4g-m6 -m64 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM6_M64
+// CHECK_C864GM6_M64: #define __ADX__ 1
+// CHECK_C864GM6_M64: #define __AES__ 1
+// CHECK_C864GM6_M64: #define __AVX2__ 1
+// CHECK_C864GM6_M64: #define __AVX__ 1
+// CHECK_C864GM6_M64: #define __BMI2__ 1
+// CHECK_C864GM6_M64: #define __BMI__ 1
+// CHECK_C864GM6_M64: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM6_M64: #define __CLZERO__ 1
+// CHECK_C864GM6_M64: #define __CRC32__ 1
+// CHECK_C864GM6_M64: #define __F16C__ 1
+// CHECK_C864GM6_M64: #define __FMA__ 1
+// CHECK_C864GM6_M64: #define __FSGSBASE__ 1
+// CHECK_C864GM6_M64: #define __FXSR__ 1
+// CHECK_C864GM6_M64: #define __LZCNT__ 1
+// CHECK_C864GM6_M64: #define __MMX__ 1
+// CHECK_C864GM6_M64: #define __MOVBE__ 1
+// CHECK_C864GM6_M64: #define __MWAITX__ 1
+// CHECK_C864GM6_M64: #define __PCLMUL__ 1
+// CHECK_C864GM6_M64: #define __POPCNT__ 1
+// CHECK_C864GM6_M64: #define __PRFCHW__ 1
+// CHECK_C864GM6_M64: #define __RDRND__ 1
+// CHECK_C864GM6_M64: #define __RDSEED__ 1
+// CHECK_C864GM6_M64: #define __SHA__ 1
+// CHECK_C864GM6_M64: #define __SSE2_MATH__ 1
+// CHECK_C864GM6_M64: #define __SSE2__ 1
+// CHECK_C864GM6_M64: #define __SSE3__ 1
+// CHECK_C864GM6_M64: #define __SSE4A__ 1
+// CHECK_C864GM6_M64: #define __SSE4_1__ 1
+// CHECK_C864GM6_M64: #define __SSE4_2__ 1
+// CHECK_C864GM6_M64: #define __SSE_MATH__ 1
+// CHECK_C864GM6_M64: #define __SSE__ 1
+// CHECK_C864GM6_M64: #define __SSSE3__ 1
+// CHECK_C864GM6_M64: #define __XSAVEC__ 1
+// CHECK_C864GM6_M64: #define __XSAVEOPT__ 1
+// CHECK_C864GM6_M64: #define __XSAVES__ 1
+// CHECK_C864GM6_M64: #define __XSAVE__ 1
+// CHECK_C864GM6_M64: #define __c86 -4g-m6__ 1
+// CHECK_C864GM6_M64: #define __tune_c86 -4g-m6__ 1
+// CHECK_C864GM6_M64: #define __x86_64 1
+// CHECK_C864GM6_M64: #define __x86_64__ 1
+
+// RUN: %clang -march=c86-4g-m7 -m32 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM7_M32
+// CHECK_C864GM7_M32: #define __ADX__ 1
+// CHECK_C864GM7_M32: #define __AES__ 1
+// CHECK_C864GM7_M32: #define __AVX2__ 1
+// CHECK_C864GM7_M32: #define __AVX512BF16__ 1
+// CHECK_C864GM7_M32: #define __AVX512BITALG__ 1
+// CHECK_C864GM7_M32: #define __AVX512BW__ 1
+// CHECK_C864GM7_M32: #define __AVX512CD__ 1
+// CHECK_C864GM7_M32: #define __AVX512DQ__ 1
+// CHECK_C864GM7_M32: #define __AVX512F__ 1
+// CHECK_C864GM7_M32: #define __AVX512IFMA__ 1
+// CHECK_C864GM7_M32: #define __AVX512VBMI2__ 1
+// CHECK_C864GM7_M32: #define __AVX512VBMI__ 1
+// CHECK_C864GM7_M32: #define __AVX512VL__ 1
+// CHECK_C864GM7_M32: #define __AVX512VNNI__ 1
+// CHECK_C864GM7_M32: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_C864GM7_M32: #define __AVX__ 1
+// CHECK_C864GM7_M32: #define __BMI2__ 1
+// CHECK_C864GM7_M32: #define __BMI__ 1
+// CHECK_C864GM7_M32: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM7_M32: #define __CLWB__ 1
+// CHECK_C864GM7_M32: #define __CLZERO__ 1
+// CHECK_C864GM7_M32: #define __CRC32__ 1
+// CHECK_C864GM7_M32: #define __F16C__ 1
+// CHECK_C864GM7_M32: #define __FMA__ 1
+// CHECK_C864GM7_M32: #define __FSGSBASE__ 1
+// CHECK_C864GM7_M32: #define __FXSR__ 1
+// CHECK_C864GM7_M32: #define __GFNI__ 1
+// CHECK_C864GM7_M32: #define __LZCNT__ 1
+// CHECK_C864GM7_M32: #define __MMX__ 1
+// CHECK_C864GM7_M32: #define __MOVBE__ 1
+// CHECK_C864GM7_M32: #define __MWAITX__ 1
+// CHECK_C864GM7_M32: #define __PCLMUL__ 1
+// CHECK_C864GM7_M32: #define __POPCNT__ 1
+// CHECK_C864GM7_M32: #define __PRFCHW__ 1
+// CHECK_C864GM7_M32: #define __RDRND__ 1
+// CHECK_C864GM7_M32: #define __RDSEED__ 1
+// CHECK_C864GM7_M32: #define __SHA__ 1
+// CHECK_C864GM7_M32: #define __SSE2_MATH__ 1
+// CHECK_C864GM7_M32: #define __SSE2__ 1
+// CHECK_C864GM7_M32: #define __SSE3__ 1
+// CHECK_C864GM7_M32: #define __SSE4A__ 1
+// CHECK_C864GM7_M32: #define __SSE4_1__ 1
+// CHECK_C864GM7_M32: #define __SSE4_2__ 1
+// CHECK_C864GM7_M32: #define __SSE_MATH__ 1
+// CHECK_C864GM7_M32: #define __SSE__ 1
+// CHECK_C864GM7_M32: #define __SSSE3__ 1
+// CHECK_C864GM7_M32: #define __VAES__ 1
+// CHECK_C864GM7_M32: #define __VPCLMULQDQ__ 1
+// CHECK_C864GM7_M32: #define __WBNOINVD__ 1
+// CHECK_C864GM7_M32: #define __XSAVEC__ 1
+// CHECK_C864GM7_M32: #define __XSAVEOPT__ 1
+// CHECK_C864GM7_M32: #define __XSAVES__ 1
+// CHECK_C864GM7_M32: #define __XSAVE__ 1
+// CHECK_C864GM7_M32: #define __c86 -4g-m7__ 1
+// CHECK_C864GM7_M32: #define __i386 1
+// CHECK_C864GM7_M32: #define __i386__ 1
+// CHECK_C864GM7_M32: #define __tune_c86 -4g-m7__ 1
+
+// RUN: %clang -march=c86-4g-m7 -m64 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM7_M64
+// CHECK_C864GM7_M64: #define __ADX__ 1
+// CHECK_C864GM7_M64: #define __AES__ 1
+// CHECK_C864GM7_M64: #define __AVX2__ 1
+// CHECK_C864GM7_M64: #define __AVX512BF16__ 1
+// CHECK_C864GM7_M64: #define __AVX512BITALG__ 1
+// CHECK_C864GM7_M64: #define __AVX512BW__ 1
+// CHECK_C864GM7_M64: #define __AVX512CD__ 1
+// CHECK_C864GM7_M64: #define __AVX512DQ__ 1
+// CHECK_C864GM7_M64: #define __AVX512F__ 1
+// CHECK_C864GM7_M64: #define __AVX512IFMA__ 1
+// CHECK_C864GM7_M64: #define __AVX512VBMI2__ 1
+// CHECK_C864GM7_M64: #define __AVX512VBMI__ 1
+// CHECK_C864GM7_M64: #define __AVX512VL__ 1
+// CHECK_C864GM7_M64: #define __AVX512VNNI__ 1
+// CHECK_C864GM7_M64: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_C864GM7_M64: #define __AVX__ 1
+// CHECK_C864GM7_M64: #define __BMI2__ 1
+// CHECK_C864GM7_M64: #define __BMI__ 1
+// CHECK_C864GM7_M64: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM7_M64: #define __CLWB__ 1
+// CHECK_C864GM7_M64: #define __CLZERO__ 1
+// CHECK_C864GM7_M64: #define __CRC32__ 1
+// CHECK_C864GM7_M64: #define __F16C__ 1
+// CHECK_C864GM7_M64: #define __FMA__ 1
+// CHECK_C864GM7_M64: #define __FSGSBASE__ 1
+// CHECK_C864GM7_M64: #define __FXSR__ 1
+// CHECK_C864GM7_M64: #define __GFNI__ 1
+// CHECK_C864GM7_M64: #define __LZCNT__ 1
+// CHECK_C864GM7_M64: #define __MMX__ 1
+// CHECK_C864GM7_M64: #define __MOVBE__ 1
+// CHECK_C864GM7_M64: #define __MWAITX__ 1
+// CHECK_C864GM7_M64: #define __PCLMUL__ 1
+// CHECK_C864GM7_M64: #define __POPCNT__ 1
+// CHECK_C864GM7_M64: #define __PRFCHW__ 1
+// CHECK_C864GM7_M64: #define __RDRND__ 1
+// CHECK_C864GM7_M64: #define __RDSEED__ 1
+// CHECK_C864GM7_M64: #define __SHA__ 1
+// CHECK_C864GM7_M64: #define __SSE2_MATH__ 1
+// CHECK_C864GM7_M64: #define __SSE2__ 1
+// CHECK_C864GM7_M64: #define __SSE3__ 1
+// CHECK_C864GM7_M64: #define __SSE4A__ 1
+// CHECK_C864GM7_M64: #define __SSE4_1__ 1
+// CHECK_C864GM7_M64: #define __SSE4_2__ 1
+// CHECK_C864GM7_M64: #define __SSE_MATH__ 1
+// CHECK_C864GM7_M64: #define __SSE__ 1
+// CHECK_C864GM7_M64: #define __SSSE3__ 1
+// CHECK_C864GM7_M64: #define __VAES__ 1
+// CHECK_C864GM7_M64: #define __VPCLMULQDQ__ 1
+// CHECK_C864GM7_M64: #define __WBNOINVD__ 1
+// CHECK_C864GM7_M64: #define __XSAVEC__ 1
+// CHECK_C864GM7_M64: #define __XSAVEOPT__ 1
+// CHECK_C864GM7_M64: #define __XSAVES__ 1
+// CHECK_C864GM7_M64: #define __XSAVE__ 1
+// CHECK_C864GM7_M64: #define __c86 -4g-m7__ 1
+// CHECK_C864GM7_M64: #define __tune_c86 -4g-m7__ 1
+// CHECK_C864GM7_M64: #define __x86_64 1
+// CHECK_C864GM7_M64: #define __x86_64__ 1
+
// End X86/GCC/Linux tests ------------------
diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c b/compiler-rt/lib/builtins/cpu_model/x86.c
index a71078e9064d5..44e0560391966 100644
--- a/compiler-rt/lib/builtins/cpu_model/x86.c
+++ b/compiler-rt/lib/builtins/cpu_model/x86.c
@@ -36,11 +36,13 @@
enum VendorSignatures {
SIG_INTEL = 0x756e6547, // Genu
SIG_AMD = 0x68747541, // Auth
+ SIG_HYGON = 0x6f677948, // Hygo
};
enum ProcessorVendors {
VENDOR_INTEL = 1,
VENDOR_AMD,
+ VENDOR_HYGON,
VENDOR_OTHER,
VENDOR_MAX
};
@@ -66,6 +68,7 @@ enum ProcessorTypes {
INTEL_GRANDRIDGE,
INTEL_CLEARWATERFOREST,
AMDFAM1AH,
+ HYGONFAM18H,
CPU_TYPE_MAX
};
@@ -108,6 +111,9 @@ enum ProcessorSubtypes {
AMDFAM1AH_ZNVER6,
INTEL_COREI7_DIAMONDRAPIDS,
INTEL_COREI7_NOVALAKE,
+ HYGONFAM18H_C86_4G_M4,
+ HYGONFAM18H_C86_4G_M6,
+ HYGONFAM18H_C86_4G_M7,
CPU_SUBTYPE_MAX
};
@@ -872,6 +878,47 @@ getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
return CPU;
}
+static const char *
+getHygonProcessorTypeAndSubtype(unsigned Family, unsigned Model,
+ const unsigned *Features,
+ struct __processor_model *CpuModel) {
+ const char *CPU = 0;
+
+ enum ProcessorTypes Type = CPU_TYPE_MAX;
+ enum ProcessorSubtypes Subtype = CPU_SUBTYPE_MAX;
+
+ switch (Family) {
+ case 24:
+ switch (Model) {
+ case 4:
+ CPU = "c86-4g-m4";
+ Type = HYGONFAM18H;
+ Subtype = HYGONFAM18H_C86_4G_M4;
+ break; // c86-4g-m4
+ case 6:
+ CPU = "c86-4g-m6";
+ Type = HYGONFAM18H;
+ Subtype = HYGONFAM18H_C86_4G_M6;
+ break; // c86-4g-m6
+ case 7:
+ CPU = "c86-4g-m7";
+ Type = HYGONFAM18H;
+ Subtype = HYGONFAM18H_C86_4G_M7;
+ break; // c86-4g-m7
+ }
+ break; // Hygon Family 18H
+ default:
+ break; // Unknown Hygon CPU.
+ }
+
+ if (Type != CPU_TYPE_MAX)
+ CpuModel->__cpu_type = Type;
+ if (Subtype != CPU_SUBTYPE_MAX)
+ CpuModel->__cpu_subtype = Subtype;
+
+ return CPU;
+}
+
#undef testFeature
static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
@@ -1235,6 +1282,9 @@ int CONSTRUCTOR_ATTRIBUTE __cpu_indicator_init(void) {
// Get CPU type.
getAMDProcessorTypeAndSubtype(Family, Model, &Features[0], &__cpu_model);
__cpu_model.__cpu_vendor = VENDOR_AMD;
+ } else if (Vendor == SIG_HYGON) {
+ getHygonProcessorTypeAndSubtype(Family, Model, &Features[0], &__cpu_model);
+ __cpu_model.__cpu_vendor = VENDOR_HYGON;
} else
__cpu_model.__cpu_vendor = VENDOR_OTHER;
diff --git a/llvm/include/llvm/TargetParser/Host.h b/llvm/include/llvm/TargetParser/Host.h
index b44b9b9a4d069..27749eef9cd41 100644
--- a/llvm/include/llvm/TargetParser/Host.h
+++ b/llvm/include/llvm/TargetParser/Host.h
@@ -77,6 +77,7 @@ enum class VendorSignatures {
UNKNOWN,
GENUINE_INTEL,
AUTHENTIC_AMD,
+ HYGON_GENUINE,
};
/// Returns the host CPU's vendor.
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def
index db03fc855df5a..0194941bb70e0 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.def
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -50,6 +50,7 @@ X86_CPU_TYPE(INTEL_SIERRAFOREST, "sierraforest")
X86_CPU_TYPE(INTEL_GRANDRIDGE, "grandridge")
X86_CPU_TYPE(INTEL_CLEARWATERFOREST, "clearwaterforest")
X86_CPU_TYPE(AMDFAM1AH, "amdfam1ah")
+X86_CPU_TYPE(HYGONFAM18H, "hygonfam18h")
// Alternate names supported by __builtin_cpu_is and target multiversioning.
X86_CPU_TYPE_ALIAS(INTEL_BONNELL, "atom")
@@ -110,6 +111,9 @@ X86_CPU_SUBTYPE(AMDFAM1AH_ZNVER5, "znver5")
X86_CPU_SUBTYPE(AMDFAM1AH_ZNVER6, "znver6")
X86_CPU_SUBTYPE(INTEL_COREI7_DIAMONDRAPIDS, "diamondrapids")
X86_CPU_SUBTYPE(INTEL_COREI7_NOVALAKE, "novalake")
+X86_CPU_SUBTYPE(HYGONFAM18H_C86_4G_M4, "c86-4g-m4")
+X86_CPU_SUBTYPE(HYGONFAM18H_C86_4G_M6, "c86-4g-m6")
+X86_CPU_SUBTYPE(HYGONFAM18H_C86_4G_M7, "c86-4g-m7")
// Alternate names supported by __builtin_cpu_is and target multiversioning.
X86_CPU_SUBTYPE_ALIAS(INTEL_COREI7_ALDERLAKE, "raptorlake")
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.h b/llvm/include/llvm/TargetParser/X86TargetParser.h
index 31d13ce29f7fc..85b10d500f0a4 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.h
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.h
@@ -147,6 +147,9 @@ enum CPUKind {
CK_ZNVER4,
CK_ZNVER5,
CK_ZNVER6,
+ CK_C86_4G_M4,
+ CK_C86_4G_M6,
+ CK_C86_4G_M7,
CK_x86_64,
CK_x86_64_v2,
CK_x86_64_v3,
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index c42d3453e0729..0080732ec198a 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1661,6 +1661,81 @@ def ProcessorFeatures {
];
list<SubtargetFeature> ZN6Features =
!listconcat(ZN5Features, ZN6AdditionalFeatures);
+
+ list<SubtargetFeature> C864GM4Features = [FeatureADX,
+ FeatureAES,
+ FeatureAVX2,
+ FeatureBMI,
+ FeatureBMI2,
+ FeatureCLFLUSHOPT,
+ FeatureCLZERO,
+ FeatureCMOV,
+ FeatureCRC32,
+ FeatureCX16,
+ FeatureF16C,
+ FeatureFMA,
+ FeatureFSGSBase,
+ FeatureFXSR,
+ FeatureLAHFSAHF64,
+ FeatureLZCNT,
+ FeatureMMX,
+ FeatureMOVBE,
+ FeatureMWAITX,
+ FeatureNOPL,
+ FeaturePCLMUL,
+ FeaturePOPCNT,
+ FeaturePRFCHW,
+ FeatureRDRAND,
+ FeatureRDSEED,
+ FeatureSHA,
+ FeatureSSE4A,
+ FeatureX86_64,
+ FeatureX87,
+ FeatureXSAVE,
+ FeatureXSAVEC,
+ FeatureXSAVEOPT,
+ FeatureXSAVES];
+ list<SubtargetFeature> C864GM4Tuning = [TuningFastLZCNT,
+ TuningFastBEXTR,
+ TuningFast15ByteNOP,
+ TuningFastScalarFSQRT,
+ TuningFastVectorFSQRT,
+ TuningFastScalarShiftMasks,
+ TuningFastVariablePerLaneShuffle,
+ TuningFastMOVBE,
+ TuningFastImm16,
+ TuningSlowDivide64,
+ TuningSlowSHLD,
+ TuningSBBDepBreaking,
+ TuningInsertVZEROUPPER,
+ TuningAllowLight256Bit];
+
+ list<SubtargetFeature> C864GM6Features = C864GM4Features;
+ list<SubtargetFeature> C864GM6Tuning = C864GM4Tuning;
+
+ list<SubtargetFeature> C864GM7AdditionalFeatures = [FeatureAVX512,
+ FeatureBF16,
+ FeatureBITALG,
+ FeatureBWI,
+ FeatureCDI,
+ FeatureCLWB,
+ FeatureDQI,
+ FeatureGFNI,
+ FeatureIFMA,
+ FeatureVAES,
+ FeatureVBMI,
+ FeatureVBMI2,
+ FeatureVLX,
+ FeatureVNNI,
+ FeatureVPCLMULQDQ,
+ FeatureVPOPCNTDQ,
+ FeatureWBNOINVD];
+ list<SubtargetFeature> C864GM7Features =
+ !listconcat(C864GM4Features, C864GM7AdditionalFeatures);
+
+ list<SubtargetFeature> C864GM7AdditionalTuning = [TuningBranchFusion];
+ list<SubtargetFeature> C864GM7Tuning =
+ !listconcat(C864GM4Tuning, C864GM7AdditionalTuning);
}
//===----------------------------------------------------------------------===//
@@ -2026,6 +2101,15 @@ def : ProcModel<"znver5", Znver4Model, ProcessorFeatures.ZN5Features,
def : ProcModel<"znver6", Znver4Model, ProcessorFeatures.ZN6Features,
ProcessorFeatures.ZN6Tuning>;
+// Hygon CPUs.
+
+def : Proc<"c86-4g-m4", ProcessorFeatures.C864GM4Features,
+ ProcessorFeatures.C864GM4Tuning>;
+def : Proc<"c86-4g-m6", ProcessorFeatures.C864GM6Features,
+ ProcessorFeatures.C864GM6Tuning>;
+def : Proc<"c86-4g-m7", ProcessorFeatures.C864GM7Features,
+ ProcessorFeatures.C864GM7Tuning>;
+
def : Proc<"geode", [FeatureX87, FeatureCX8, FeatureMMX, FeaturePRFCHW],
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index dfe97f178bd46..ef164bed8c5af 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -682,6 +682,10 @@ VendorSignatures getVendorSignature(unsigned *MaxLeaf) {
if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
return VendorSignatures::AUTHENTIC_AMD;
+ // "Hygo nGen uien"
+ if (EBX == 0x6f677948 && EDX == 0x6e65476e && ECX == 0x656e6975)
+ return VendorSignatures::HYGON_GENUINE;
+
return VendorSignatures::UNKNOWN;
}
@@ -1355,6 +1359,39 @@ static const char *getAMDProcessorTypeAndSubtype(unsigned Family,
return CPU;
}
+static StringRef
+getHygonProcessorTypeAndSubtype(unsigned Family, unsigned Model,
+ const unsigned *Features,
+ unsigned *Type, unsigned *Subtype) {
+ StringRef CPU;
+
+ switch (Family) {
+ case 24:
+ switch (Model) {
+ case 4:
+ CPU = "c86-4g-m4";
+ *Type = X86::HYGONFAM18H;
+ *Subtype = X86::HYGONFAM18H_C86_4G_M4;
+ break; // c86-4g-m4
+ case 6:
+ CPU = "c86-4g-m6";
+ *Type = X86::HYGONFAM18H;
+ *Subtype = X86::HYGONFAM18H_C86_4G_M6;
+ break; // c86-4g-m6
+ case 7:
+ CPU = "c86-4g-m7";
+ *Type = X86::HYGONFAM18H;
+ *Subtype = X86::HYGONFAM18H_C86_4G_M7;
+ break; // c86-4g-m7
+ }
+ break; // Hygon Family 18H
+ default:
+ break; // Unknown Hygon CPU.
+ }
+
+ return CPU;
+}
+
#undef testFeature
static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
@@ -1517,6 +1554,9 @@ StringRef sys::getHostCPUName() {
} else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type,
&Subtype);
+ } else if (Vendor == VendorSignatures::HYGON_GENUINE) {
+ CPU = getHygonProcessorTypeAndSubtype(Family, Model, Features, &Type,
+ &Subtype);
}
if (!CPU.empty())
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index b3859eb4ff2fd..f2e18b8b8d967 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -259,6 +259,27 @@ static constexpr FeatureBitset FeaturesZNVER6 =
FeaturesZNVER5 | FeatureAVXVNNIINT8 | FeatureAVX512FP16 | FeatureAVXIFMA |
FeatureAVXNECONVERT;
+// Hygon architecture processors.
+constexpr FeatureBitset FeaturesC86_4G_M4 =
+ FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
+ FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
+ FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT |
+ FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT |
+ FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
+ FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
+ FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
+ FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
+ FeatureXSAVEOPT | FeatureXSAVES;
+
+static constexpr FeatureBitset FeaturesC86_4G_M6 = FeaturesC86_4G_M4;
+
+static constexpr FeatureBitset FeaturesC86_4G_M7 = FeaturesC86_4G_M4 |
+ FeatureAVX512BF16 | FeatureAVX512BITALG | FeatureAVX512BW | FeatureAVX512CD |
+ FeatureAVX512DQ | FeatureAVX512F | FeatureAVX512IFMA | FeatureAVX512VBMI |
+ FeatureAVX512VBMI2 | FeatureAVX512VL | FeatureAVX512VNNI |
+ FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureCMOV | FeatureGFNI |
+ FeatureVAES | FeatureVPCLMULQDQ | FeatureWBNOINVD;
+
// D151696 tranplanted Mangling and OnlyForCPUDispatchSpecific from
// X86TargetParser.def to here. They are assigned by following ways:
// 1. Copy the mangling from the original CPU_SPEICIFC MACROs. If no, assign
@@ -445,6 +466,10 @@ constexpr ProcInfo Processors[] = {
{ {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4, '\0', false },
{ {"znver5"}, CK_ZNVER5, FEATURE_AVX512VP2INTERSECT, FeaturesZNVER5, '\0', false },
{ {"znver6"}, CK_ZNVER6, FEATURE_AVX512FP16, FeaturesZNVER6, '\0', false },
+ // Hygon precessors.
+ { {"c86-4g-m4"}, CK_C86_4G_M4, FEATURE_AVX2, FeaturesC86_4G_M4 , '\0', false },
+ { {"c86-4g-m6"}, CK_C86_4G_M6, FEATURE_AVX512VBMI2, FeaturesC86_4G_M6 , '\0', false },
+ { {"c86-4g-m7"}, CK_C86_4G_M7, FEATURE_AVX512VBMI2, FeaturesC86_4G_M7 , '\0', false },
// Generic 64-bit processor.
{ {"x86-64"}, CK_x86_64, FEATURE_SSE2 , FeaturesX86_64, '\0', false },
{ {"x86-64-v2"}, CK_x86_64_v2, FEATURE_SSE4_2 , FeaturesX86_64_V2, '\0', false },
diff --git a/llvm/test/CodeGen/X86/bypass-slow-division-64.ll b/llvm/test/CodeGen/X86/bypass-slow-division-64.ll
index 821b7b8e4144f..f60d7f011c7d5 100644
--- a/llvm/test/CodeGen/X86/bypass-slow-division-64.ll
+++ b/llvm/test/CodeGen/X86/bypass-slow-division-64.ll
@@ -25,6 +25,9 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m4 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m6 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m7 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
; Additional tests for 64-bit divide bypass
diff --git a/llvm/test/CodeGen/X86/cmp16.ll b/llvm/test/CodeGen/X86/cmp16.ll
index ff6ee68074088..8d441424dabec 100644
--- a/llvm/test/CodeGen/X86/cmp16.ll
+++ b/llvm/test/CodeGen/X86/cmp16.ll
@@ -15,6 +15,9 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=X64,X64-FAST
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=X64,X64-FAST
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 | FileCheck %s --check-prefixes=X64,X64-FAST
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m4 | FileCheck %s --check-prefixes=X64,X64-FAST
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m6 | FileCheck %s --check-prefixes=X64,X64-FAST
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m7 | FileCheck %s --check-prefixes=X64,X64-FAST
define i1 @cmp16_reg_eq_reg(i16 %a0, i16 %a1) {
; X86-GENERIC-LABEL: cmp16_reg_eq_reg:
diff --git a/llvm/test/CodeGen/X86/cpus-hygon.ll b/llvm/test/CodeGen/X86/cpus-hygon.ll
new file mode 100644
index 0000000000000..94895e32c4d72
--- /dev/null
+++ b/llvm/test/CodeGen/X86/cpus-hygon.ll
@@ -0,0 +1,10 @@
+; Test that the CPU names work.
+; CHECK-NO-ERROR-NOT: not a recognized processor for this target
+
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m6 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+
+define void @foo() {
+ ret void
+}
diff --git a/llvm/test/CodeGen/X86/rdpru.ll b/llvm/test/CodeGen/X86/rdpru.ll
index 067ae31142c39..b811bba23c329 100644
--- a/llvm/test/CodeGen/X86/rdpru.ll
+++ b/llvm/test/CodeGen/X86/rdpru.ll
@@ -8,6 +8,9 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 -fast-isel | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 -fast-isel | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 -fast-isel | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m4 -fast-isel | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m6 -fast-isel | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m7 -fast-isel | FileCheck %s --check-prefix=X64
define void @rdpru_asm() {
; X86-LABEL: rdpru_asm:
diff --git a/llvm/test/CodeGen/X86/slow-unaligned-mem.ll b/llvm/test/CodeGen/X86/slow-unaligned-mem.ll
index a215b60055dd5..ec2a61c548fd1 100644
--- a/llvm/test/CodeGen/X86/slow-unaligned-mem.ll
+++ b/llvm/test/CodeGen/X86/slow-unaligned-mem.ll
@@ -53,6 +53,12 @@
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver5 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX512
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver6 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX512
+; Hygon chips with fast unaligned memory accesses
+
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=c86-4g-m4 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=c86-4g-m6 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=c86-4g-m7 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX512
+
; Other chips with slow unaligned memory accesses
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=c3-2 2>&1 | FileCheck %s --check-prefixes=SLOW
diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll b/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
index 416ff1d41af72..ab527e3a0bc63 100644
--- a/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
+++ b/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
@@ -8,6 +8,9 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m4 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m6 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m7 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=X86-64
define float @f32_no_daz(float %f) #0 {
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll b/llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll
index 5bf936c6e5cec..eb0751d01182a 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll
@@ -10,6 +10,9 @@
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=znver4 | FileCheck %s --check-prefixes=FAST
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=znver5 | FileCheck %s --check-prefixes=FAST
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=znver6 | FileCheck %s --check-prefixes=FAST
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m4 | FileCheck %s --check-prefixes=FAST
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m6 | FileCheck %s --check-prefixes=FAST
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 | FileCheck %s --check-prefixes=FAST
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=haswell | FileCheck %s --check-prefixes=FAST
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=skx | FileCheck %s --check-prefixes=FAST
diff --git a/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll b/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
index bb1a4e5fcb75b..1d3feb0b7802d 100644
--- a/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
+++ b/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
@@ -19,6 +19,9 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=BMI2-FAST
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=BMI2-FAST
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 | FileCheck %s --check-prefixes=BMI2-FAST
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m4 | FileCheck %s --check-prefixes=BMI2-SLOW
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m6 | FileCheck %s --check-prefixes=BMI2-SLOW
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m7 | FileCheck %s --check-prefixes=BMI2-SLOW
; Verify that for the X86_64 processors that are known to have poor latency
; double precision shift instructions we do not generate 'shld' or 'shrd'
diff --git a/llvm/test/MC/X86/x86_long_nop.s b/llvm/test/MC/X86/x86_long_nop.s
index 2c5fe3acde26c..9a1826c8748ab 100644
--- a/llvm/test/MC/X86/x86_long_nop.s
+++ b/llvm/test/MC/X86/x86_long_nop.s
@@ -23,6 +23,12 @@
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=znver5 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=znver6 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=znver6 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=c86-4g-m4 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=c86-4g-m4 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=c86-4g-m6 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=c86-4g-m6 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=c86-4g-m7 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=c86-4g-m7 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=nehalem %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP10 %s
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=westmere %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP10 %s
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=sandybridge %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
>From 29588a49746a8e226ee8cd1e377750b3f258fd32 Mon Sep 17 00:00:00 2001
From: Xiaomeng Zhang <zhangxiaomeng at hygon.cn>
Date: Fri, 20 Mar 2026 14:21:04 +0800
Subject: [PATCH 2/7] Update Host.cpp
---
llvm/lib/TargetParser/Host.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index ef164bed8c5af..2124b0e3783ac 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -682,7 +682,7 @@ VendorSignatures getVendorSignature(unsigned *MaxLeaf) {
if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
return VendorSignatures::AUTHENTIC_AMD;
- // "Hygo nGen uien"
+ // "Hygo nGen uine"
if (EBX == 0x6f677948 && EDX == 0x6e65476e && ECX == 0x656e6975)
return VendorSignatures::HYGON_GENUINE;
>From 41c2607ef5114cc8c3ce45317b4957d88100648c Mon Sep 17 00:00:00 2001
From: zhangxiaomeng <zhangxiaomeng at hygon.cn>
Date: Fri, 20 Mar 2026 16:50:45 +0800
Subject: [PATCH 3/7] fix some clang-format errors
---
compiler-rt/lib/builtins/cpu_model/x86.c | 4 ++--
llvm/lib/TargetParser/Host.cpp | 11 ++++++-----
llvm/lib/TargetParser/X86TargetParser.cpp | 13 +++++++------
3 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c b/compiler-rt/lib/builtins/cpu_model/x86.c
index 44e0560391966..b0e1f0bdcc5c4 100644
--- a/compiler-rt/lib/builtins/cpu_model/x86.c
+++ b/compiler-rt/lib/builtins/cpu_model/x86.c
@@ -880,8 +880,8 @@ getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
static const char *
getHygonProcessorTypeAndSubtype(unsigned Family, unsigned Model,
- const unsigned *Features,
- struct __processor_model *CpuModel) {
+ const unsigned *Features,
+ struct __processor_model *CpuModel) {
const char *CPU = 0;
enum ProcessorTypes Type = CPU_TYPE_MAX;
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index 2124b0e3783ac..881c963585e75 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -1359,10 +1359,11 @@ static const char *getAMDProcessorTypeAndSubtype(unsigned Family,
return CPU;
}
-static StringRef
-getHygonProcessorTypeAndSubtype(unsigned Family, unsigned Model,
- const unsigned *Features,
- unsigned *Type, unsigned *Subtype) {
+static StringRef getHygonProcessorTypeAndSubtype(unsigned Family,
+ unsigned Model,
+ const unsigned *Features,
+ unsigned *Type,
+ unsigned *Subtype) {
StringRef CPU;
switch (Family) {
@@ -1556,7 +1557,7 @@ StringRef sys::getHostCPUName() {
&Subtype);
} else if (Vendor == VendorSignatures::HYGON_GENUINE) {
CPU = getHygonProcessorTypeAndSubtype(Family, Model, Features, &Type,
- &Subtype);
+ &Subtype);
}
if (!CPU.empty())
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index f2e18b8b8d967..676a989977f3a 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -273,12 +273,13 @@ constexpr FeatureBitset FeaturesC86_4G_M4 =
static constexpr FeatureBitset FeaturesC86_4G_M6 = FeaturesC86_4G_M4;
-static constexpr FeatureBitset FeaturesC86_4G_M7 = FeaturesC86_4G_M4 |
- FeatureAVX512BF16 | FeatureAVX512BITALG | FeatureAVX512BW | FeatureAVX512CD |
- FeatureAVX512DQ | FeatureAVX512F | FeatureAVX512IFMA | FeatureAVX512VBMI |
- FeatureAVX512VBMI2 | FeatureAVX512VL | FeatureAVX512VNNI |
- FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureCMOV | FeatureGFNI |
- FeatureVAES | FeatureVPCLMULQDQ | FeatureWBNOINVD;
+static constexpr FeatureBitset FeaturesC86_4G_M7 =
+ FeaturesC86_4G_M4 | FeatureAVX512BF16 | FeatureAVX512BITALG |
+ FeatureAVX512BW | FeatureAVX512CD | FeatureAVX512DQ | FeatureAVX512F |
+ FeatureAVX512IFMA | FeatureAVX512VBMI | FeatureAVX512VBMI2 |
+ FeatureAVX512VL | FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB |
+ FeatureCMOV | FeatureGFNI | FeatureVAES | FeatureVPCLMULQDQ |
+ FeatureWBNOINVD;
// D151696 tranplanted Mangling and OnlyForCPUDispatchSpecific from
// X86TargetParser.def to here. They are assigned by following ways:
>From 31d214f7ac165931f934edfae90a371251e0dbb5 Mon Sep 17 00:00:00 2001
From: zhangxiaomeng <zhangxiaomeng at hygon.cn>
Date: Sun, 22 Mar 2026 12:33:20 +0800
Subject: [PATCH 4/7] Change c86-4g-m6 KeyFeature to right.
---
llvm/lib/TargetParser/X86TargetParser.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index 676a989977f3a..012cdabfb85e6 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -469,7 +469,7 @@ constexpr ProcInfo Processors[] = {
{ {"znver6"}, CK_ZNVER6, FEATURE_AVX512FP16, FeaturesZNVER6, '\0', false },
// Hygon precessors.
{ {"c86-4g-m4"}, CK_C86_4G_M4, FEATURE_AVX2, FeaturesC86_4G_M4 , '\0', false },
- { {"c86-4g-m6"}, CK_C86_4G_M6, FEATURE_AVX512VBMI2, FeaturesC86_4G_M6 , '\0', false },
+ { {"c86-4g-m6"}, CK_C86_4G_M6, FEATURE_AVX2, FeaturesC86_4G_M6 , '\0', false },
{ {"c86-4g-m7"}, CK_C86_4G_M7, FEATURE_AVX512VBMI2, FeaturesC86_4G_M7 , '\0', false },
// Generic 64-bit processor.
{ {"x86-64"}, CK_x86_64, FEATURE_SSE2 , FeaturesX86_64, '\0', false },
>From 21da8f14665c0c4d6b2abfa64470cdf75f003412 Mon Sep 17 00:00:00 2001
From: zhangxiaomeng <zhangxiaomeng at hygon.cn>
Date: Sun, 22 Mar 2026 14:16:57 +0800
Subject: [PATCH 5/7] Add and update some comments.
---
llvm/lib/Target/X86/X86.td | 5 ++++-
llvm/lib/TargetParser/X86TargetParser.cpp | 2 +-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 0080732ec198a..61e863bf46431 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1662,6 +1662,7 @@ def ProcessorFeatures {
list<SubtargetFeature> ZN6Features =
!listconcat(ZN5Features, ZN6AdditionalFeatures);
+ // Hygon Processors common ISAs
list<SubtargetFeature> C864GM4Features = [FeatureADX,
FeatureAES,
FeatureAVX2,
@@ -1710,9 +1711,11 @@ def ProcessorFeatures {
TuningInsertVZEROUPPER,
TuningAllowLight256Bit];
+ // C86-4G-M6
list<SubtargetFeature> C864GM6Features = C864GM4Features;
list<SubtargetFeature> C864GM6Tuning = C864GM4Tuning;
-
+
+ // C86-4G-M7
list<SubtargetFeature> C864GM7AdditionalFeatures = [FeatureAVX512,
FeatureBF16,
FeatureBITALG,
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index 012cdabfb85e6..b924851cd0c53 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -467,7 +467,7 @@ constexpr ProcInfo Processors[] = {
{ {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4, '\0', false },
{ {"znver5"}, CK_ZNVER5, FEATURE_AVX512VP2INTERSECT, FeaturesZNVER5, '\0', false },
{ {"znver6"}, CK_ZNVER6, FEATURE_AVX512FP16, FeaturesZNVER6, '\0', false },
- // Hygon precessors.
+ // Hygon processors.
{ {"c86-4g-m4"}, CK_C86_4G_M4, FEATURE_AVX2, FeaturesC86_4G_M4 , '\0', false },
{ {"c86-4g-m6"}, CK_C86_4G_M6, FEATURE_AVX2, FeaturesC86_4G_M6 , '\0', false },
{ {"c86-4g-m7"}, CK_C86_4G_M7, FEATURE_AVX512VBMI2, FeaturesC86_4G_M7 , '\0', false },
>From e7c93df8ab25f329fe8d0d9f3722867762514669 Mon Sep 17 00:00:00 2001
From: zhangxiaomeng <zhangxiaomeng at hygon.cn>
Date: Thu, 26 Mar 2026 14:31:05 +0800
Subject: [PATCH 6/7] Change the macro names from hyphens to underscores.
---
clang/lib/Basic/Targets/X86.cpp | 6 ++---
.../Preprocessor/predefined-arch-macros.c | 24 +++++++++----------
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index fd30c7f8d61b9..becae6e9526a6 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -730,13 +730,13 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
defineCPUMacros(Builder, "geode");
break;
case CK_C86_4G_M4:
- defineCPUMacros(Builder, "c86-4g-m4");
+ defineCPUMacros(Builder, "c86_4g_m4");
break;
case CK_C86_4G_M6:
- defineCPUMacros(Builder, "c86-4g-m6");
+ defineCPUMacros(Builder, "c86_4g_m6");
break;
case CK_C86_4G_M7:
- defineCPUMacros(Builder, "c86-4g-m7");
+ defineCPUMacros(Builder, "c86_4g_m7");
break;
}
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c
index bc950f5ecee9c..79e3b282c7058 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -4326,10 +4326,10 @@
// CHECK_C864GM4_M32: #define __XSAVEOPT__ 1
// CHECK_C864GM4_M32: #define __XSAVES__ 1
// CHECK_C864GM4_M32: #define __XSAVE__ 1
-// CHECK_C864GM4_M32: #define __c86 -4g-m4__ 1
+// CHECK_C864GM4_M32: #define __c86_4g_m4__ 1
// CHECK_C864GM4_M32: #define __i386 1
// CHECK_C864GM4_M32: #define __i386__ 1
-// CHECK_C864GM4_M32: #define __tune_c86 -4g-m4__ 1
+// CHECK_C864GM4_M32: #define __tune_c86_4g_m4__ 1
// RUN: %clang -march=c86-4g-m4 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
@@ -4370,8 +4370,8 @@
// CHECK_C864GM4_M64: #define __XSAVEOPT__ 1
// CHECK_C864GM4_M64: #define __XSAVES__ 1
// CHECK_C864GM4_M64: #define __XSAVE__ 1
-// CHECK_C864GM4_M64: #define __c86 -4g-m4__ 1
-// CHECK_C864GM4_M64: #define __tune_c86 -4g-m4__ 1
+// CHECK_C864GM4_M64: #define __c86_4g_m4__ 1
+// CHECK_C864GM4_M64: #define __tune_c86_4g_m4__ 1
// CHECK_C864GM4_M64: #define __x86_64 1
// CHECK_C864GM4_M64: #define __x86_64__ 1
@@ -4414,10 +4414,10 @@
// CHECK_C864GM6_M32: #define __XSAVEOPT__ 1
// CHECK_C864GM6_M32: #define __XSAVES__ 1
// CHECK_C864GM6_M32: #define __XSAVE__ 1
-// CHECK_C864GM6_M32: #define __c86 -4g-m6__ 1
+// CHECK_C864GM6_M32: #define __c86_4g_m6__ 1
// CHECK_C864GM6_M32: #define __i386 1
// CHECK_C864GM6_M32: #define __i386__ 1
-// CHECK_C864GM6_M32: #define __tune_c86 -4g-m6__ 1
+// CHECK_C864GM6_M32: #define __tune_c86_4g_m6__ 1
// RUN: %clang -march=c86-4g-m6 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
@@ -4458,8 +4458,8 @@
// CHECK_C864GM6_M64: #define __XSAVEOPT__ 1
// CHECK_C864GM6_M64: #define __XSAVES__ 1
// CHECK_C864GM6_M64: #define __XSAVE__ 1
-// CHECK_C864GM6_M64: #define __c86 -4g-m6__ 1
-// CHECK_C864GM6_M64: #define __tune_c86 -4g-m6__ 1
+// CHECK_C864GM6_M64: #define __c86_4g_m6__ 1
+// CHECK_C864GM6_M64: #define __tune_c86_4g_m6__ 1
// CHECK_C864GM6_M64: #define __x86_64 1
// CHECK_C864GM6_M64: #define __x86_64__ 1
@@ -4519,10 +4519,10 @@
// CHECK_C864GM7_M32: #define __XSAVEOPT__ 1
// CHECK_C864GM7_M32: #define __XSAVES__ 1
// CHECK_C864GM7_M32: #define __XSAVE__ 1
-// CHECK_C864GM7_M32: #define __c86 -4g-m7__ 1
+// CHECK_C864GM7_M32: #define __c86_4g_m7__ 1
// CHECK_C864GM7_M32: #define __i386 1
// CHECK_C864GM7_M32: #define __i386__ 1
-// CHECK_C864GM7_M32: #define __tune_c86 -4g-m7__ 1
+// CHECK_C864GM7_M32: #define __tune_c86_4g_m7__ 1
// RUN: %clang -march=c86-4g-m7 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
@@ -4580,8 +4580,8 @@
// CHECK_C864GM7_M64: #define __XSAVEOPT__ 1
// CHECK_C864GM7_M64: #define __XSAVES__ 1
// CHECK_C864GM7_M64: #define __XSAVE__ 1
-// CHECK_C864GM7_M64: #define __c86 -4g-m7__ 1
-// CHECK_C864GM7_M64: #define __tune_c86 -4g-m7__ 1
+// CHECK_C864GM7_M64: #define __c86_4g_m7__ 1
+// CHECK_C864GM7_M64: #define __tune_c86_4g_m7__ 1
// CHECK_C864GM7_M64: #define __x86_64 1
// CHECK_C864GM7_M64: #define __x86_64__ 1
>From 196317d28e2c53f38928e738f7b0548d15137086 Mon Sep 17 00:00:00 2001
From: Xiaomeng Zhang <zhangxiaomeng at hygon.cn>
Date: Thu, 26 Mar 2026 14:49:10 +0800
Subject: [PATCH 7/7] Update llvm/lib/Target/X86/X86.td
Co-authored-by: Carlo Cabrera <github at carlo.cab>
---
llvm/lib/Target/X86/X86.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 61e863bf46431..0adab58f9eff7 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1711,7 +1711,7 @@ def ProcessorFeatures {
TuningInsertVZEROUPPER,
TuningAllowLight256Bit];
- // C86-4G-M6
+ // C86-4G-M6: same features as M4; kept separate for future differentiation
list<SubtargetFeature> C864GM6Features = C864GM4Features;
list<SubtargetFeature> C864GM6Tuning = C864GM4Tuning;
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