[llvm] [test] Precommit test (PR #188667)

[via llvm-commits]

https://github.com/wangleiat created https://github.com/llvm/llvm-project/pull/188667

None

>From 976a107ad34ab1764def212bad21683a7a6dcc83 Mon Sep 17 00:00:00 2001
From: wanglei <wanglei at loongson.cn>
Date: Thu, 26 Mar 2026 11:18:40 +0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
 =?UTF-8?q?l=20version?=
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Created using spr 1.3.7
---
 .../VectorCombine/LoongArch/lit.local.cfg     |  4 +++
 .../LoongArch/shuffle-identity-miscompile.ll  | 26 +++++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 llvm/test/Transforms/VectorCombine/LoongArch/lit.local.cfg
 create mode 100644 llvm/test/Transforms/VectorCombine/LoongArch/shuffle-identity-miscompile.ll

diff --git a/llvm/test/Transforms/VectorCombine/LoongArch/lit.local.cfg b/llvm/test/Transforms/VectorCombine/LoongArch/lit.local.cfg
new file mode 100644
index 0000000000000..9570af17fe5f1
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/LoongArch/lit.local.cfg
@@ -0,0 +1,4 @@
+config.suffixes = [".ll"]
+
+if not "LoongArch" in config.root.targets:
+    config.unsupported = True
diff --git a/llvm/test/Transforms/VectorCombine/LoongArch/shuffle-identity-miscompile.ll b/llvm/test/Transforms/VectorCombine/LoongArch/shuffle-identity-miscompile.ll
new file mode 100644
index 0000000000000..94815d8a604bc
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/LoongArch/shuffle-identity-miscompile.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt < %s -S -p vector-combine -mtriple=loongarch64 -mattr=+lsx | FileCheck %s
+
+define i32 @shuffle_different_lanes() local_unnamed_addr {
+; CHECK-LABEL: define i32 @shuffle_different_lanes(
+; CHECK-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    [[TMP0:%.*]] = call <2 x i64> @llvm.loongarch.lsx.vadd.d(<2 x i64> <i64 8067293510808050, i64 0>, <2 x i64> zeroinitializer)
+; CHECK-NEXT:    [[TMP1:%.*]] = trunc <2 x i64> [[TMP0]] to <2 x i16>
+; CHECK-NEXT:    [[TMP2:%.*]] = trunc <2 x i64> [[TMP0]] to <2 x i16>
+; CHECK-NEXT:    [[TMP3:%.*]] = bitcast <2 x i16> zeroinitializer to i32
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+entry:
+  %0 = call <2 x i64> @llvm.loongarch.lsx.vadd.d(<2 x i64> <i64 8067293510808050, i64 0>, <2 x i64> zeroinitializer)
+  %shuffle = shufflevector <2 x i64> %0, <2 x i64> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
+  %conv = trunc <4 x i64> %shuffle to <4 x i16>
+  %vecinit4.i = shufflevector <4 x i16> %conv, <4 x i16> poison, <4 x i32> <i32 2, i32 poison, i32 2, i32 poison>
+  %sub.i = sub <4 x i16> %conv, %vecinit4.i
+  %shuffle.i = shufflevector <4 x i16> %sub.i, <4 x i16> poison, <2 x i32> <i32 0, i32 2>
+  %1 = bitcast <2 x i16> %shuffle.i to i32
+  ret i32 %1
+
+}
+
+declare <2 x i64> @llvm.loongarch.lsx.vadd.d(<2 x i64>, <2 x i64>)