[llvm] [PowerPC] Use add_like pattern for ADDI/ADDIS add-immediate matching (PR #187326)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 25 04:59:36 PDT 2026
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/187326
>From 4afc61564edc9838bd393bd8e874b85864d31523 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Wed, 18 Mar 2026 17:03:23 +0000
Subject: [PATCH] [PowerPC] Add add_like pattern and use for ADDI/ADDIS
add-immediate matching
Allow or_disjoint nodes with sext-immediates to make use of the ADD instructions instead or OR (which use zext-immediates) to potentially allow further folding
Prep work to help with regressions identified on #186461
---
llvm/lib/Target/PowerPC/PPCInstrInfo.td | 6 ++--
.../CodeGen/PowerPC/aix-vec_insert_elt.ll | 4 +--
.../aix32-p8-scalar_vector_conversions.ll | 4 +--
.../PowerPC/fp128-bitcast-after-operation.ll | 2 +-
llvm/test/CodeGen/PowerPC/signbit-shift.ll | 2 +-
llvm/test/CodeGen/PowerPC/vec_insert_elt.ll | 2 +-
...lar-shift-by-byte-multiple-legalization.ll | 29 +++++++++----------
7 files changed, 24 insertions(+), 25 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 3271e4d279f56..e4eb55ae8d0cc 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2551,7 +2551,7 @@ def : Pat<(int_ppc_iospace_eieio), (PseudoEIEIO)>;
let PPC970_Unit = 1 in { // FXU Operations.
def ADDI : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D),
"addi $RST, $RA, $D", IIC_IntSimple,
- [(set i32:$RST, (add i32:$RA, imm32SExt16:$D))]>;
+ [(set i32:$RST, (add_like i32:$RA, imm32SExt16:$D))]>;
let BaseName = "addic" in {
let Defs = [CARRY] in
def ADDIC : DForm_2<12, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),
@@ -2565,7 +2565,7 @@ def ADDIC_rec : DForm_2<13, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),
}
def ADDIS : DForm_2<15, (outs gprc:$RST), (ins gprc_nor0:$RA, s17imm:$D),
"addis $RST, $RA, $D", IIC_IntSimple,
- [(set i32:$RST, (add i32:$RA, imm16ShiftedSExt:$D))]>;
+ [(set i32:$RST, (add_like i32:$RA, imm16ShiftedSExt:$D))]>;
let isCodeGenOnly = 1 in
def LA : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D),
"la $RST, $D($RA)", IIC_IntGeneral,
@@ -3400,7 +3400,7 @@ def : Pat<(not i32:$in),
(i32not $in)>;
// ADD an arbitrary immediate.
-def : Pat<(add i32:$in, imm:$imm),
+def : Pat<(add_like i32:$in, imm:$imm),
(ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
// OR an arbitrary immediate.
def : Pat<(or i32:$in, imm:$imm),
diff --git a/llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll b/llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
index 3c1646f8eb19e..01df6f02bf6e9 100644
--- a/llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
@@ -170,7 +170,7 @@ define <2 x i64> @testDoubleword(<2 x i64> %a, i64 %b, i64 %idx) {
; CHECK-32-NEXT: stxv 34, -32(1)
; CHECK-32-NEXT: rlwinm 6, 5, 2, 28, 28
; CHECK-32-NEXT: stwx 3, 7, 6
-; CHECK-32-NEXT: ori 3, 5, 1
+; CHECK-32-NEXT: addi 3, 5, 1
; CHECK-32-NEXT: addi 5, 1, -16
; CHECK-32-NEXT: lxv 0, -32(1)
; CHECK-32-NEXT: rlwinm 3, 3, 2, 28, 29
@@ -190,7 +190,7 @@ define <2 x i64> @testDoubleword(<2 x i64> %a, i64 %b, i64 %idx) {
; CHECK-32-P10-NEXT: add 5, 6, 6
; CHECK-32-P10-NEXT: slwi 6, 5, 2
; CHECK-32-P10-NEXT: vinswlx 2, 6, 3
-; CHECK-32-P10-NEXT: ori 3, 5, 1
+; CHECK-32-P10-NEXT: addi 3, 5, 1
; CHECK-32-P10-NEXT: slwi 3, 3, 2
; CHECK-32-P10-NEXT: vinswlx 2, 3, 4
; CHECK-32-P10-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/aix32-p8-scalar_vector_conversions.ll b/llvm/test/CodeGen/PowerPC/aix32-p8-scalar_vector_conversions.ll
index 7aaf753d29133..b05cb1843482e 100644
--- a/llvm/test/CodeGen/PowerPC/aix32-p8-scalar_vector_conversions.ll
+++ b/llvm/test/CodeGen/PowerPC/aix32-p8-scalar_vector_conversions.ll
@@ -993,7 +993,7 @@ define i64 @getvelsl(<2 x i64> %vsl, i32 signext %i) {
; CHECK-NEXT: add 5, 3, 3
; CHECK-NEXT: addi 4, 1, -16
; CHECK-NEXT: rlwinm 3, 5, 2, 28, 28
-; CHECK-NEXT: ori 5, 5, 1
+; CHECK-NEXT: addi 5, 5, 1
; CHECK-NEXT: stxvw4x 34, 0, 4
; CHECK-NEXT: rlwinm 5, 5, 2, 28, 29
; CHECK-NEXT: lwzx 3, 4, 3
@@ -1011,7 +1011,7 @@ define i64 @getvelul(<2 x i64> %vul, i32 signext %i) {
; CHECK-NEXT: add 5, 3, 3
; CHECK-NEXT: addi 4, 1, -16
; CHECK-NEXT: rlwinm 3, 5, 2, 28, 28
-; CHECK-NEXT: ori 5, 5, 1
+; CHECK-NEXT: addi 5, 5, 1
; CHECK-NEXT: stxvw4x 34, 0, 4
; CHECK-NEXT: rlwinm 5, 5, 2, 28, 29
; CHECK-NEXT: lwzx 3, 4, 3
diff --git a/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll b/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
index ebec8c1c4d654..4608b19bfe954 100644
--- a/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
+++ b/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
@@ -223,7 +223,7 @@ define i128 @test_copysign_const(ppc_fp128 %x) nounwind {
; PPC32-NEXT: li 6, 0
; PPC32-NEXT: lwz 3, 24(1)
; PPC32-NEXT: rlwinm 4, 3, 0, 0, 0
-; PPC32-NEXT: oris 3, 4, 16399
+; PPC32-NEXT: addis 3, 4, 16399
; PPC32-NEXT: xoris 5, 4, 48304
; PPC32-NEXT: li 4, 0
; PPC32-NEXT: addi 1, 1, 32
diff --git a/llvm/test/CodeGen/PowerPC/signbit-shift.ll b/llvm/test/CodeGen/PowerPC/signbit-shift.ll
index f8838b50816e1..9af6f97b1c879 100644
--- a/llvm/test/CodeGen/PowerPC/signbit-shift.ll
+++ b/llvm/test/CodeGen/PowerPC/signbit-shift.ll
@@ -205,7 +205,7 @@ define i32 @sub_lshr_not(i32 %x) {
; CHECK-LABEL: sub_lshr_not:
; CHECK: # %bb.0:
; CHECK-NEXT: srwi 3, 3, 31
-; CHECK-NEXT: ori 3, 3, 42
+; CHECK-NEXT: addi 3, 3, 42
; CHECK-NEXT: blr
%not = xor i32 %x, -1
%sh = lshr i32 %not, 31
diff --git a/llvm/test/CodeGen/PowerPC/vec_insert_elt.ll b/llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
index 242884940023c..835ce40d8d0a0 100644
--- a/llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
@@ -246,7 +246,7 @@ define <2 x i64> @testDoubleword(<2 x i64> %a, i64 %b, i64 %idx) {
; AIX-P8-32-NEXT: rlwinm r7, r6, 2, 28, 28
; AIX-P8-32-NEXT: stxvd2x v2, 0, r5
; AIX-P8-32-NEXT: stwx r3, r5, r7
-; AIX-P8-32-NEXT: ori r3, r6, 1
+; AIX-P8-32-NEXT: addi r3, r6, 1
; AIX-P8-32-NEXT: rlwinm r3, r3, 2, 28, 29
; AIX-P8-32-NEXT: stwx r4, r5, r3
; AIX-P8-32-NEXT: lxvd2x v2, 0, r5
diff --git a/llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll b/llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll
index 12976e838f3ca..6e66f44663295 100644
--- a/llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll
+++ b/llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll
@@ -1504,22 +1504,21 @@ define void @shl_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) nou
; LE-32BIT-NEXT: stw 8, 20(1)
; LE-32BIT-NEXT: stw 7, 16(1)
; LE-32BIT-NEXT: lwzux 3, 4, 3
-; LE-32BIT-NEXT: lwz 6, 12(4)
-; LE-32BIT-NEXT: lwz 7, 8(4)
-; LE-32BIT-NEXT: lwz 8, 20(4)
-; LE-32BIT-NEXT: lwz 9, 16(4)
-; LE-32BIT-NEXT: lwz 10, 28(4)
-; LE-32BIT-NEXT: lwz 11, 24(4)
-; LE-32BIT-NEXT: ori 4, 4, 4
-; LE-32BIT-NEXT: lwz 4, 0(4)
+; LE-32BIT-NEXT: lwz 6, 4(4)
+; LE-32BIT-NEXT: lwz 7, 12(4)
+; LE-32BIT-NEXT: lwz 8, 8(4)
+; LE-32BIT-NEXT: lwz 9, 20(4)
+; LE-32BIT-NEXT: lwz 10, 16(4)
+; LE-32BIT-NEXT: lwz 11, 28(4)
+; LE-32BIT-NEXT: lwz 4, 24(4)
; LE-32BIT-NEXT: stw 3, 0(5)
-; LE-32BIT-NEXT: stw 11, 24(5)
-; LE-32BIT-NEXT: stw 10, 28(5)
-; LE-32BIT-NEXT: stw 9, 16(5)
-; LE-32BIT-NEXT: stw 8, 20(5)
-; LE-32BIT-NEXT: stw 7, 8(5)
-; LE-32BIT-NEXT: stw 6, 12(5)
-; LE-32BIT-NEXT: stw 4, 4(5)
+; LE-32BIT-NEXT: stw 4, 24(5)
+; LE-32BIT-NEXT: stw 11, 28(5)
+; LE-32BIT-NEXT: stw 10, 16(5)
+; LE-32BIT-NEXT: stw 9, 20(5)
+; LE-32BIT-NEXT: stw 8, 8(5)
+; LE-32BIT-NEXT: stw 7, 12(5)
+; LE-32BIT-NEXT: stw 6, 4(5)
; LE-32BIT-NEXT: addi 1, 1, 80
; LE-32BIT-NEXT: blr
%src = load i256, ptr %src.ptr, align 1
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