[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for div_fmas/fixup/scale (PR #188305)

[Petar Avramovic via llvm-commits]

petar-avramovic wrote:

## RegBankLegalize coverage check

| Opcode | Rule | Test file | Function | Status |
|--------|------|-----------|----------|--------|
| amdgcn_div_fmas | .Div(S32) | GlobalISel/llvm.amdgcn.div.fmas.ll | `v_div_fmas_f32` | ✅ |
| amdgcn_div_fmas | .Uni(S32) | GlobalISel/llvm.amdgcn.div.fmas.ll | `s_div_fmas_f32` | ✅ |
| amdgcn_div_fmas | .Div(S64) | GlobalISel/llvm.amdgcn.div.fmas.ll | `v_div_fmas_f64` | ✅ |
| amdgcn_div_fmas | .Uni(S64) | GlobalISel/llvm.amdgcn.div.fmas.ll | `s_div_fmas_f64` | ✅ |
| amdgcn_div_fixup | .Div(S16) | 💡 llvm.amdgcn.div.fixup.f16.ll | 💡 `div_fixup_f16_vgpr` | ❌ MISSING |
| amdgcn_div_fixup | .Uni(S16) | llvm.amdgcn.div.fixup.f16.ll | `div_fixup_f16` | ✅ |
| amdgcn_div_fixup | .Div(S32) | 💡 llvm.amdgcn.div.fixup.ll | 💡 `test_div_fixup_f32_vgpr` | ❌ MISSING |
| amdgcn_div_fixup | .Uni(S32) | llvm.amdgcn.div.fixup.ll | `test_div_fixup_f32` | ✅ |
| amdgcn_div_fixup | .Div(S64) | 💡 llvm.amdgcn.div.fixup.ll | 💡 `test_div_fixup_f64_vgpr` | ❌ MISSING |
| amdgcn_div_fixup | .Uni(S64) | llvm.amdgcn.div.fixup.ll | `test_div_fixup_f64` | ✅ |
| amdgcn_div_scale | .Div(S32) | GlobalISel/llvm.amdgcn.div.scale.ll | `test_div_scale_f32_1` | ✅ |
| amdgcn_div_scale | .Uni(S32) | GlobalISel/llvm.amdgcn.div.scale.ll | `test_div_scale_f32_all_scalar_1` | ✅ |
| amdgcn_div_scale | .Div(S64) | GlobalISel/llvm.amdgcn.div.scale.ll | `test_div_scale_f64_1` | ✅ |
| amdgcn_div_scale | .Uni(S64) | GlobalISel/llvm.amdgcn.div.scale.ll | `test_div_scale_f64_all_scalar_1` | ✅ |

### Suggested fix

Three `.Div` rules for `amdgcn_div_fixup` are not covered — all existing tests use `amdgpu_kernel` functions, so arguments are in SGPRs (hitting `.Uni`). Non-kernel `void` device functions are needed so arguments arrive in VGPRs.

**For `llvm.amdgcn.div.fixup.f16.ll`** (covers `.Div(S16)`):
```llvm
define void @div_fixup_f16_vgpr(ptr addrspace(1) %out, half %a, half %b, half %c) nounwind {
  %result = call half @llvm.amdgcn.div.fixup.f16(half %a, half %b, half %c) nounwind readnone
  store half %result, ptr addrspace(1) %out, align 2
  ret void
}
```

**For `llvm.amdgcn.div.fixup.ll`** (covers `.Div(S32)` and `.Div(S64)`):
```llvm
define void @test_div_fixup_f32_vgpr(ptr addrspace(1) %out, float %a, float %b, float %c) nounwind {
  %result = call float @llvm.amdgcn.div.fixup.f32(float %a, float %b, float %c) nounwind readnone
  store float %result, ptr addrspace(1) %out, align 4
  ret void
}

define void @test_div_fixup_f64_vgpr(ptr addrspace(1) %out, double %a, double %b, double %c) nounwind {
  %result = call double @llvm.amdgcn.div.fixup.f64(double %a, double %b, double %c) nounwind readnone
  store double %result, ptr addrspace(1) %out, align 8
  ret void
}
```

Non-kernel `void` functions so arguments arrive in VGPRs, exercising the `.Div` rules. Run `update_llc_test_checks.py` to fill in the check lines after adding these functions.

> ⚙️ *Automated check — not a human review. Posted by [`/check-regbank-coverage-pr`](https://github.com/llvm/llvm-project/blob/main/.claude/commands/check-regbank-coverage-pr.md) running in [Claude Code](https://claude.ai/code).*

https://github.com/llvm/llvm-project/pull/188305