[compiler-rt] [compiler-rt] Implement __clear_cache for Hexagon (PR #188411)

[Brian Cain via llvm-commits]

https://github.com/androm3da created https://github.com/llvm/llvm-project/pull/188411

Add Hexagon support to compiler-rt's __clear_cache implementation. The sequence follows the Hexagon PRM (§ 5.10.3-5.10.4):

* dccleaninva per cache line
* icinva per cache line
* isync

>From d16391da823af1e7a3495f569718d60de0204472 Mon Sep 17 00:00:00 2001
From: Brian Cain <brian.cain at oss.qualcomm.com>
Date: Tue, 24 Mar 2026 20:51:03 -0700
Subject: [PATCH] [compiler-rt] Implement __clear_cache for Hexagon

Add Hexagon support to compiler-rt's __clear_cache implementation.
The sequence follows the Hexagon PRM (Sections 5.10.3-5.10.4):

* dccleaninva per cache line
* icinva per cache line
* isync
---
 compiler-rt/lib/builtins/clear_cache.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/compiler-rt/lib/builtins/clear_cache.c b/compiler-rt/lib/builtins/clear_cache.c
index eb58452d624ee..a1eceff1951c5 100644
--- a/compiler-rt/lib/builtins/clear_cache.c
+++ b/compiler-rt/lib/builtins/clear_cache.c
@@ -204,6 +204,24 @@ void __clear_cache(void *start, void *end) {
   sysarch(RISCV_SYNC_ICACHE, &arg);
 #elif defined(__ve__)
   __asm__ volatile("fencec 2");
+#elif defined(__hexagon__)
+  // Hexagon has separate instruction and data caches.
+  const size_t line_size = __GCC_DESTRUCTIVE_SIZE;
+  const uintptr_t mask = ~(line_size - 1);
+  const uintptr_t start_line = (uintptr_t)start & mask;
+  const uintptr_t end_addr = (uintptr_t)end;
+
+  // Clean and invalidate data cache to push new code to memory and
+  // invalidate stale lines in the L2 cache.
+  for (uintptr_t addr = start_line; addr < end_addr; addr += line_size)
+    __builtin_HEXAGON_Y2_dccleaninva((void *)addr);
+
+  // Invalidate instruction cache so it re-fetches from memory.
+  for (uintptr_t addr = start_line; addr < end_addr; addr += line_size)
+    __builtin_HEXAGON_Y2_icinva((void *)addr);
+
+  // Instruction sync barrier ensures subsequent fetches see the new code.
+  __builtin_HEXAGON_Y2_isync();
 #else
 #if __APPLE__
   // On Darwin, sys_icache_invalidate() provides this functionality