[llvm] [AArch64] Fix definition of system register move instructions (PR #185709)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 24 06:44:57 PDT 2026
https://github.com/Lukacma updated https://github.com/llvm/llvm-project/pull/185709
>From 0fb3f038615073ce3f9f84c87accf251cd731b1e Mon Sep 17 00:00:00 2001
From: Marian Lukac <Marian.Lukac at arm.com>
Date: Tue, 10 Mar 2026 17:47:48 +0000
Subject: [PATCH 01/12] [NFC] Make bit20 fixed for Sys Register move
instructions
---
.../lib/Target/AArch64/AArch64InstrFormats.td | 10 +-
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 22 +-
.../lib/Target/AArch64/AArch64SMEInstrInfo.td | 4 +-
.../Target/AArch64/AArch64SystemOperands.td | 2098 ++++++++---------
.../AArch64/aarch64-sme-za-call-lowering.ll | 12 +-
.../CodeGen/AArch64/expand-sme-pseudos.mir | 8 +-
.../machine-sme-abi-find-insert-pt.mir | 26 +-
.../CodeGen/AArch64/sme-abi-eh-liveins.mir | 10 +-
.../AArch64/sme-lazy-sve-nzcv-live.mir | 6 +-
9 files changed, 1100 insertions(+), 1096 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 5fdb9814cc2e8..5aa661ae4d8b5 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -2015,8 +2015,9 @@ def TIndexhint_op : Operand<i32> {
class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
"mrs", "\t$Rt, $systemreg"> {
- bits<16> systemreg;
- let Inst{20-5} = systemreg;
+ bits<15> systemreg;
+ let Inst{20}= 0b1;
+ let Inst{19-5} = systemreg;
let DecoderNamespace = "Fallback";
// The MRS is set as a NZCV setting instruction. Not all MRS instructions
// require doing this. The alternative was to explicitly model each one, but
@@ -2030,8 +2031,9 @@ class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
// would do it, but feels like overkill at this point.
class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
"msr", "\t$systemreg, $Rt"> {
- bits<16> systemreg;
- let Inst{20-5} = systemreg;
+ bits<15> systemreg;
+ let Inst{20} = 0b1;
+ let Inst{19-5} = systemreg;
let DecoderNamespace = "Fallback";
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 2900cf073b5aa..0bb9a85eb87cb 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -2528,35 +2528,35 @@ def HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW : Pseudo<
}
// The virtual cycle counter register is CNTVCT_EL0.
-def : Pat<(readcyclecounter), (MRS 0xdf02)>;
+def : Pat<(readcyclecounter), (MRS 0x5f02)>;
// FPCR and FPSR registers.
let Uses = [FPCR] in
def MRS_FPCR : Pseudo<(outs GPR64:$dst), (ins),
[(set GPR64:$dst, (int_aarch64_get_fpcr))]>,
- PseudoInstExpansion<(MRS GPR64:$dst, 0xda20)>,
+ PseudoInstExpansion<(MRS GPR64:$dst, 0x5a20)>,
Sched<[WriteSys]>;
let Defs = [FPCR] in
def MSR_FPCR : Pseudo<(outs), (ins GPR64:$val),
[(int_aarch64_set_fpcr i64:$val)]>,
- PseudoInstExpansion<(MSR 0xda20, GPR64:$val)>,
+ PseudoInstExpansion<(MSR 0x5a20, GPR64:$val)>,
Sched<[WriteSys]>;
let Uses = [FPSR] in
def MRS_FPSR : Pseudo<(outs GPR64:$dst), (ins),
[(set GPR64:$dst, (int_aarch64_get_fpsr))]>,
- PseudoInstExpansion<(MRS GPR64:$dst, 0xda21)>,
+ PseudoInstExpansion<(MRS GPR64:$dst, 0x5a21)>,
Sched<[WriteSys]>;
let Defs = [FPSR] in
def MSR_FPSR : Pseudo<(outs), (ins GPR64:$val),
[(int_aarch64_set_fpsr i64:$val)]>,
- PseudoInstExpansion<(MSR 0xda21, GPR64:$val)>,
+ PseudoInstExpansion<(MSR 0x5a21, GPR64:$val)>,
Sched<[WriteSys]>;
let Defs = [FPMR] in
def MSR_FPMR : Pseudo<(outs), (ins GPR64:$val),
[(int_aarch64_set_fpmr i64:$val)]>,
- PseudoInstExpansion<(MSR 0xda22, GPR64:$val)>,
+ PseudoInstExpansion<(MSR 0x5a22, GPR64:$val)>,
Sched<[WriteSys]>;
// Generic system instructions
@@ -11534,16 +11534,18 @@ def MRRS : RtSystemI128<1,
(outs MrrsMssrPairClassOperand:$Rt), (ins mrs_sysreg_op:$systemreg),
"mrrs", "\t$Rt, $systemreg">
{
- bits<16> systemreg;
- let Inst{20-5} = systemreg;
+ bits<15> systemreg;
+ let Inst{20}= 0b1;
+ let Inst{19-5} = systemreg;
}
def MSRR : RtSystemI128<0,
(outs), (ins msr_sysreg_op:$systemreg, MrrsMssrPairClassOperand:$Rt),
"msrr", "\t$systemreg, $Rt">
{
- bits<16> systemreg;
- let Inst{20-5} = systemreg;
+ bits<15> systemreg;
+ let Inst{20} = 0b1;
+ let Inst{19-5} = systemreg;
}
//===----------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index 905eed50dee9a..9bb0273449cb2 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -326,9 +326,9 @@ def : Pat<(AArch64_restore_za
// Read and write TPIDR2_EL0
def : Pat<(int_aarch64_sme_set_tpidr2 i64:$val),
- (MSR 0xde85, GPR64:$val)>;
+ (MSR 0x5e85, GPR64:$val)>;
def : Pat<(i64 (int_aarch64_sme_get_tpidr2)),
- (MRS 0xde85)>;
+ (MRS 0x5e85)>;
} // End let Predicates = [HasSMEandIsNonStreamingSafe]
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 004bff92c082d..923e040686965 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -1024,11 +1024,11 @@ defm : TLBI<"VMALLWS2E1OS", 0, 0b100, 0b1000, 0b0101, 0b010, 0, 1>;
// MRS/MSR (system register read/write) instruction options.
//===----------------------------------------------------------------------===//
-class SysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
+class SysReg<string name, bit op0, bits<3> op1, bits<4> crn, bits<4> crm,
bits<3> op2> {
string Name = name;
- bits<16> Encoding;
- let Encoding{15-14} = op0;
+ bits<15> Encoding;
+ let Encoding{14} = op0;
let Encoding{13-11} = op1;
let Encoding{10-7} = crn;
let Encoding{6-3} = crm;
@@ -1058,21 +1058,21 @@ def lookupSysRegByName : SearchIndex {
let Key = ["Name"];
}
-class RWSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
+class RWSysReg<string name, bit op0, bits<3> op1, bits<4> crn, bits<4> crm,
bits<3> op2>
: SysReg<name, op0, op1, crn, crm, op2> {
let Readable = 1;
let Writeable = 1;
}
-class ROSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
+class ROSysReg<string name, bit op0, bits<3> op1, bits<4> crn, bits<4> crm,
bits<3> op2>
: SysReg<name, op0, op1, crn, crm, op2> {
let Readable = 1;
let Writeable = 0;
}
-class WOSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
+class WOSysReg<string name, bit op0, bits<3> op1, bits<4> crn, bits<4> crm,
bits<3> op2>
: SysReg<name, op0, op1, crn, crm, op2> {
let Readable = 0;
@@ -1084,186 +1084,186 @@ class WOSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
//===----------------------
// Op0 Op1 CRn CRm Op2
-def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>;
-def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>;
-def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>;
-def : ROSysReg<"OSLSR_EL1", 0b10, 0b000, 0b0001, 0b0001, 0b100>;
-def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>;
-def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;
-def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
-def : ROSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>;
-def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>;
-def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>;
+def : ROSysReg<"MDCCSR_EL0", 0b0, 0b011, 0b0000, 0b0001, 0b000>;
+def : ROSysReg<"DBGDTRRX_EL0", 0b0, 0b011, 0b0000, 0b0101, 0b000>;
+def : ROSysReg<"MDRAR_EL1", 0b0, 0b000, 0b0001, 0b0000, 0b000>;
+def : ROSysReg<"OSLSR_EL1", 0b0, 0b000, 0b0001, 0b0001, 0b100>;
+def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b0, 0b000, 0b0111, 0b1110, 0b110>;
+def : ROSysReg<"PMCEID0_EL0", 0b1, 0b011, 0b1001, 0b1100, 0b110>;
+def : ROSysReg<"PMCEID1_EL0", 0b1, 0b011, 0b1001, 0b1100, 0b111>;
+def : ROSysReg<"PMMIR_EL1", 0b1, 0b000, 0b1001, 0b1110, 0b110>;
+def : ROSysReg<"MIDR_EL1", 0b1, 0b000, 0b0000, 0b0000, 0b000>;
+def : ROSysReg<"CCSIDR_EL1", 0b1, 0b001, 0b0000, 0b0000, 0b000>;
//v8.3 CCIDX - extending the CCsIDr number of sets
-def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> {
+def : ROSysReg<"CCSIDR2_EL1", 0b1, 0b001, 0b0000, 0b0000, 0b010> {
let Requires = [{ {AArch64::FeatureCCIDX} }];
}
-def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>;
-def : ROSysReg<"CTR_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b001>;
-def : ROSysReg<"MPIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b101>;
-def : ROSysReg<"REVIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b110>;
-def : ROSysReg<"AIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b111>;
-def : ROSysReg<"DCZID_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b111>;
-def : ROSysReg<"ID_PFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b000>;
-def : ROSysReg<"ID_PFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b001>;
-def : ROSysReg<"ID_PFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b100> {
+def : ROSysReg<"CLIDR_EL1", 0b1, 0b001, 0b0000, 0b0000, 0b001>;
+def : ROSysReg<"CTR_EL0", 0b1, 0b011, 0b0000, 0b0000, 0b001>;
+def : ROSysReg<"MPIDR_EL1", 0b1, 0b000, 0b0000, 0b0000, 0b101>;
+def : ROSysReg<"REVIDR_EL1", 0b1, 0b000, 0b0000, 0b0000, 0b110>;
+def : ROSysReg<"AIDR_EL1", 0b1, 0b001, 0b0000, 0b0000, 0b111>;
+def : ROSysReg<"DCZID_EL0", 0b1, 0b011, 0b0000, 0b0000, 0b111>;
+def : ROSysReg<"ID_PFR0_EL1", 0b1, 0b000, 0b0000, 0b0001, 0b000>;
+def : ROSysReg<"ID_PFR1_EL1", 0b1, 0b000, 0b0000, 0b0001, 0b001>;
+def : ROSysReg<"ID_PFR2_EL1", 0b1, 0b000, 0b0000, 0b0011, 0b100> {
let Requires = [{ {AArch64::FeatureSpecRestrict} }];
}
-def : ROSysReg<"ID_DFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b010>;
-def : ROSysReg<"ID_DFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b101>;
-def : ROSysReg<"ID_AFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b011>;
-def : ROSysReg<"ID_MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b100>;
-def : ROSysReg<"ID_MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b101>;
-def : ROSysReg<"ID_MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b110>;
-def : ROSysReg<"ID_MMFR3_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b111>;
-def : ROSysReg<"ID_ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b000>;
-def : ROSysReg<"ID_ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b001>;
-def : ROSysReg<"ID_ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b010>;
-def : ROSysReg<"ID_ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b011>;
-def : ROSysReg<"ID_ISAR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b100>;
-def : ROSysReg<"ID_ISAR5_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b101>;
-def : ROSysReg<"ID_ISAR6_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b111> {
+def : ROSysReg<"ID_DFR0_EL1", 0b1, 0b000, 0b0000, 0b0001, 0b010>;
+def : ROSysReg<"ID_DFR1_EL1", 0b1, 0b000, 0b0000, 0b0011, 0b101>;
+def : ROSysReg<"ID_AFR0_EL1", 0b1, 0b000, 0b0000, 0b0001, 0b011>;
+def : ROSysReg<"ID_MMFR0_EL1", 0b1, 0b000, 0b0000, 0b0001, 0b100>;
+def : ROSysReg<"ID_MMFR1_EL1", 0b1, 0b000, 0b0000, 0b0001, 0b101>;
+def : ROSysReg<"ID_MMFR2_EL1", 0b1, 0b000, 0b0000, 0b0001, 0b110>;
+def : ROSysReg<"ID_MMFR3_EL1", 0b1, 0b000, 0b0000, 0b0001, 0b111>;
+def : ROSysReg<"ID_ISAR0_EL1", 0b1, 0b000, 0b0000, 0b0010, 0b000>;
+def : ROSysReg<"ID_ISAR1_EL1", 0b1, 0b000, 0b0000, 0b0010, 0b001>;
+def : ROSysReg<"ID_ISAR2_EL1", 0b1, 0b000, 0b0000, 0b0010, 0b010>;
+def : ROSysReg<"ID_ISAR3_EL1", 0b1, 0b000, 0b0000, 0b0010, 0b011>;
+def : ROSysReg<"ID_ISAR4_EL1", 0b1, 0b000, 0b0000, 0b0010, 0b100>;
+def : ROSysReg<"ID_ISAR5_EL1", 0b1, 0b000, 0b0000, 0b0010, 0b101>;
+def : ROSysReg<"ID_ISAR6_EL1", 0b1, 0b000, 0b0000, 0b0010, 0b111> {
let Requires = [{ {AArch64::HasV8_2aOps} }];
}
-def : ROSysReg<"ID_AA64PFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b000>;
-def : ROSysReg<"ID_AA64PFR1_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b001>;
-def : ROSysReg<"ID_AA64PFR2_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b010>;
-def : ROSysReg<"ID_AA64DFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b000>;
-def : ROSysReg<"ID_AA64DFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b001>;
-def : ROSysReg<"ID_AA64DFR2_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b010>;
-def : ROSysReg<"ID_AA64AFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b100>;
-def : ROSysReg<"ID_AA64AFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b101>;
-def : ROSysReg<"ID_AA64ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b000>;
-def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>;
-def : ROSysReg<"ID_AA64ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b010>;
-def : ROSysReg<"ID_AA64ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b011>;
-def : ROSysReg<"ID_AA64MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b000>;
-def : ROSysReg<"ID_AA64MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b001>;
-def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010>;
-def : ROSysReg<"ID_AA64MMFR3_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b011>;
-def : ROSysReg<"ID_AA64MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b100>;
-def : ROSysReg<"MVFR0_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b000>;
-def : ROSysReg<"MVFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b001>;
-def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>;
-def : ROSysReg<"RVBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b001>;
-def : ROSysReg<"RVBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b001>;
-def : ROSysReg<"RVBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b001>;
-def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>;
-def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>;
-def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>;
-def : ROSysReg<"ID_MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b110>;
-def : ROSysReg<"ID_MMFR5_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b110>;
+def : ROSysReg<"ID_AA64PFR0_EL1", 0b1, 0b000, 0b0000, 0b0100, 0b000>;
+def : ROSysReg<"ID_AA64PFR1_EL1", 0b1, 0b000, 0b0000, 0b0100, 0b001>;
+def : ROSysReg<"ID_AA64PFR2_EL1", 0b1, 0b000, 0b0000, 0b0100, 0b010>;
+def : ROSysReg<"ID_AA64DFR0_EL1", 0b1, 0b000, 0b0000, 0b0101, 0b000>;
+def : ROSysReg<"ID_AA64DFR1_EL1", 0b1, 0b000, 0b0000, 0b0101, 0b001>;
+def : ROSysReg<"ID_AA64DFR2_EL1", 0b1, 0b000, 0b0000, 0b0101, 0b010>;
+def : ROSysReg<"ID_AA64AFR0_EL1", 0b1, 0b000, 0b0000, 0b0101, 0b100>;
+def : ROSysReg<"ID_AA64AFR1_EL1", 0b1, 0b000, 0b0000, 0b0101, 0b101>;
+def : ROSysReg<"ID_AA64ISAR0_EL1", 0b1, 0b000, 0b0000, 0b0110, 0b000>;
+def : ROSysReg<"ID_AA64ISAR1_EL1", 0b1, 0b000, 0b0000, 0b0110, 0b001>;
+def : ROSysReg<"ID_AA64ISAR2_EL1", 0b1, 0b000, 0b0000, 0b0110, 0b010>;
+def : ROSysReg<"ID_AA64ISAR3_EL1", 0b1, 0b000, 0b0000, 0b0110, 0b011>;
+def : ROSysReg<"ID_AA64MMFR0_EL1", 0b1, 0b000, 0b0000, 0b0111, 0b000>;
+def : ROSysReg<"ID_AA64MMFR1_EL1", 0b1, 0b000, 0b0000, 0b0111, 0b001>;
+def : ROSysReg<"ID_AA64MMFR2_EL1", 0b1, 0b000, 0b0000, 0b0111, 0b010>;
+def : ROSysReg<"ID_AA64MMFR3_EL1", 0b1, 0b000, 0b0000, 0b0111, 0b011>;
+def : ROSysReg<"ID_AA64MMFR4_EL1", 0b1, 0b000, 0b0000, 0b0111, 0b100>;
+def : ROSysReg<"MVFR0_EL1", 0b1, 0b000, 0b0000, 0b0011, 0b000>;
+def : ROSysReg<"MVFR1_EL1", 0b1, 0b000, 0b0000, 0b0011, 0b001>;
+def : ROSysReg<"MVFR2_EL1", 0b1, 0b000, 0b0000, 0b0011, 0b010>;
+def : ROSysReg<"RVBAR_EL1", 0b1, 0b000, 0b1100, 0b0000, 0b001>;
+def : ROSysReg<"RVBAR_EL2", 0b1, 0b100, 0b1100, 0b0000, 0b001>;
+def : ROSysReg<"RVBAR_EL3", 0b1, 0b110, 0b1100, 0b0000, 0b001>;
+def : ROSysReg<"ISR_EL1", 0b1, 0b000, 0b1100, 0b0001, 0b000>;
+def : ROSysReg<"CNTPCT_EL0", 0b1, 0b011, 0b1110, 0b0000, 0b001>;
+def : ROSysReg<"CNTVCT_EL0", 0b1, 0b011, 0b1110, 0b0000, 0b010>;
+def : ROSysReg<"ID_MMFR4_EL1", 0b1, 0b000, 0b0000, 0b0010, 0b110>;
+def : ROSysReg<"ID_MMFR5_EL1", 0b1, 0b000, 0b0000, 0b0011, 0b110>;
// Trace registers
// Op0 Op1 CRn CRm Op2
-def : ROSysReg<"TRCSTATR", 0b10, 0b001, 0b0000, 0b0011, 0b000>;
-def : ROSysReg<"TRCIDR8", 0b10, 0b001, 0b0000, 0b0000, 0b110>;
-def : ROSysReg<"TRCIDR9", 0b10, 0b001, 0b0000, 0b0001, 0b110>;
-def : ROSysReg<"TRCIDR10", 0b10, 0b001, 0b0000, 0b0010, 0b110>;
-def : ROSysReg<"TRCIDR11", 0b10, 0b001, 0b0000, 0b0011, 0b110>;
-def : ROSysReg<"TRCIDR12", 0b10, 0b001, 0b0000, 0b0100, 0b110>;
-def : ROSysReg<"TRCIDR13", 0b10, 0b001, 0b0000, 0b0101, 0b110>;
-def : ROSysReg<"TRCIDR0", 0b10, 0b001, 0b0000, 0b1000, 0b111>;
-def : ROSysReg<"TRCIDR1", 0b10, 0b001, 0b0000, 0b1001, 0b111>;
-def : ROSysReg<"TRCIDR2", 0b10, 0b001, 0b0000, 0b1010, 0b111>;
-def : ROSysReg<"TRCIDR3", 0b10, 0b001, 0b0000, 0b1011, 0b111>;
-def : ROSysReg<"TRCIDR4", 0b10, 0b001, 0b0000, 0b1100, 0b111>;
-def : ROSysReg<"TRCIDR5", 0b10, 0b001, 0b0000, 0b1101, 0b111>;
-def : ROSysReg<"TRCIDR6", 0b10, 0b001, 0b0000, 0b1110, 0b111>;
-def : ROSysReg<"TRCIDR7", 0b10, 0b001, 0b0000, 0b1111, 0b111>;
-def : ROSysReg<"TRCOSLSR", 0b10, 0b001, 0b0001, 0b0001, 0b100>;
-def : ROSysReg<"TRCPDSR", 0b10, 0b001, 0b0001, 0b0101, 0b100>;
-def : ROSysReg<"TRCDEVAFF0", 0b10, 0b001, 0b0111, 0b1010, 0b110>;
-def : ROSysReg<"TRCDEVAFF1", 0b10, 0b001, 0b0111, 0b1011, 0b110>;
-def : ROSysReg<"TRCLSR", 0b10, 0b001, 0b0111, 0b1101, 0b110>;
-def : ROSysReg<"TRCAUTHSTATUS", 0b10, 0b001, 0b0111, 0b1110, 0b110>;
-def : ROSysReg<"TRCDEVARCH", 0b10, 0b001, 0b0111, 0b1111, 0b110>;
-def : ROSysReg<"TRCDEVID", 0b10, 0b001, 0b0111, 0b0010, 0b111>;
-def : ROSysReg<"TRCDEVTYPE", 0b10, 0b001, 0b0111, 0b0011, 0b111>;
-def : ROSysReg<"TRCPIDR4", 0b10, 0b001, 0b0111, 0b0100, 0b111>;
-def : ROSysReg<"TRCPIDR5", 0b10, 0b001, 0b0111, 0b0101, 0b111>;
-def : ROSysReg<"TRCPIDR6", 0b10, 0b001, 0b0111, 0b0110, 0b111>;
-def : ROSysReg<"TRCPIDR7", 0b10, 0b001, 0b0111, 0b0111, 0b111>;
-def : ROSysReg<"TRCPIDR0", 0b10, 0b001, 0b0111, 0b1000, 0b111>;
-def : ROSysReg<"TRCPIDR1", 0b10, 0b001, 0b0111, 0b1001, 0b111>;
-def : ROSysReg<"TRCPIDR2", 0b10, 0b001, 0b0111, 0b1010, 0b111>;
-def : ROSysReg<"TRCPIDR3", 0b10, 0b001, 0b0111, 0b1011, 0b111>;
-def : ROSysReg<"TRCCIDR0", 0b10, 0b001, 0b0111, 0b1100, 0b111>;
-def : ROSysReg<"TRCCIDR1", 0b10, 0b001, 0b0111, 0b1101, 0b111>;
-def : ROSysReg<"TRCCIDR2", 0b10, 0b001, 0b0111, 0b1110, 0b111>;
-def : ROSysReg<"TRCCIDR3", 0b10, 0b001, 0b0111, 0b1111, 0b111>;
+def : ROSysReg<"TRCSTATR", 0b0, 0b001, 0b0000, 0b0011, 0b000>;
+def : ROSysReg<"TRCIDR8", 0b0, 0b001, 0b0000, 0b0000, 0b110>;
+def : ROSysReg<"TRCIDR9", 0b0, 0b001, 0b0000, 0b0001, 0b110>;
+def : ROSysReg<"TRCIDR10", 0b0, 0b001, 0b0000, 0b0010, 0b110>;
+def : ROSysReg<"TRCIDR11", 0b0, 0b001, 0b0000, 0b0011, 0b110>;
+def : ROSysReg<"TRCIDR12", 0b0, 0b001, 0b0000, 0b0100, 0b110>;
+def : ROSysReg<"TRCIDR13", 0b0, 0b001, 0b0000, 0b0101, 0b110>;
+def : ROSysReg<"TRCIDR0", 0b0, 0b001, 0b0000, 0b1000, 0b111>;
+def : ROSysReg<"TRCIDR1", 0b0, 0b001, 0b0000, 0b1001, 0b111>;
+def : ROSysReg<"TRCIDR2", 0b0, 0b001, 0b0000, 0b1010, 0b111>;
+def : ROSysReg<"TRCIDR3", 0b0, 0b001, 0b0000, 0b1011, 0b111>;
+def : ROSysReg<"TRCIDR4", 0b0, 0b001, 0b0000, 0b1100, 0b111>;
+def : ROSysReg<"TRCIDR5", 0b0, 0b001, 0b0000, 0b1101, 0b111>;
+def : ROSysReg<"TRCIDR6", 0b0, 0b001, 0b0000, 0b1110, 0b111>;
+def : ROSysReg<"TRCIDR7", 0b0, 0b001, 0b0000, 0b1111, 0b111>;
+def : ROSysReg<"TRCOSLSR", 0b0, 0b001, 0b0001, 0b0001, 0b100>;
+def : ROSysReg<"TRCPDSR", 0b0, 0b001, 0b0001, 0b0101, 0b100>;
+def : ROSysReg<"TRCDEVAFF0", 0b0, 0b001, 0b0111, 0b1010, 0b110>;
+def : ROSysReg<"TRCDEVAFF1", 0b0, 0b001, 0b0111, 0b1011, 0b110>;
+def : ROSysReg<"TRCLSR", 0b0, 0b001, 0b0111, 0b1101, 0b110>;
+def : ROSysReg<"TRCAUTHSTATUS", 0b0, 0b001, 0b0111, 0b1110, 0b110>;
+def : ROSysReg<"TRCDEVARCH", 0b0, 0b001, 0b0111, 0b1111, 0b110>;
+def : ROSysReg<"TRCDEVID", 0b0, 0b001, 0b0111, 0b0010, 0b111>;
+def : ROSysReg<"TRCDEVTYPE", 0b0, 0b001, 0b0111, 0b0011, 0b111>;
+def : ROSysReg<"TRCPIDR4", 0b0, 0b001, 0b0111, 0b0100, 0b111>;
+def : ROSysReg<"TRCPIDR5", 0b0, 0b001, 0b0111, 0b0101, 0b111>;
+def : ROSysReg<"TRCPIDR6", 0b0, 0b001, 0b0111, 0b0110, 0b111>;
+def : ROSysReg<"TRCPIDR7", 0b0, 0b001, 0b0111, 0b0111, 0b111>;
+def : ROSysReg<"TRCPIDR0", 0b0, 0b001, 0b0111, 0b1000, 0b111>;
+def : ROSysReg<"TRCPIDR1", 0b0, 0b001, 0b0111, 0b1001, 0b111>;
+def : ROSysReg<"TRCPIDR2", 0b0, 0b001, 0b0111, 0b1010, 0b111>;
+def : ROSysReg<"TRCPIDR3", 0b0, 0b001, 0b0111, 0b1011, 0b111>;
+def : ROSysReg<"TRCCIDR0", 0b0, 0b001, 0b0111, 0b1100, 0b111>;
+def : ROSysReg<"TRCCIDR1", 0b0, 0b001, 0b0111, 0b1101, 0b111>;
+def : ROSysReg<"TRCCIDR2", 0b0, 0b001, 0b0111, 0b1110, 0b111>;
+def : ROSysReg<"TRCCIDR3", 0b0, 0b001, 0b0111, 0b1111, 0b111>;
// GICv3 registers
// Op0 Op1 CRn CRm Op2
-def : ROSysReg<"ICC_IAR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b000>;
-def : ROSysReg<"ICC_IAR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b000>;
-def : ROSysReg<"ICC_HPPIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b010>;
-def : ROSysReg<"ICC_HPPIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b010>;
-def : ROSysReg<"ICC_RPR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b011>;
-def : ROSysReg<"ICH_VTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b001>;
-def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>;
-def : ROSysReg<"ICH_ELRSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>;
+def : ROSysReg<"ICC_IAR1_EL1", 0b1, 0b000, 0b1100, 0b1100, 0b000>;
+def : ROSysReg<"ICC_IAR0_EL1", 0b1, 0b000, 0b1100, 0b1000, 0b000>;
+def : ROSysReg<"ICC_HPPIR1_EL1", 0b1, 0b000, 0b1100, 0b1100, 0b010>;
+def : ROSysReg<"ICC_HPPIR0_EL1", 0b1, 0b000, 0b1100, 0b1000, 0b010>;
+def : ROSysReg<"ICC_RPR_EL1", 0b1, 0b000, 0b1100, 0b1011, 0b011>;
+def : ROSysReg<"ICH_VTR_EL2", 0b1, 0b100, 0b1100, 0b1011, 0b001>;
+def : ROSysReg<"ICH_EISR_EL2", 0b1, 0b100, 0b1100, 0b1011, 0b011>;
+def : ROSysReg<"ICH_ELRSR_EL2", 0b1, 0b100, 0b1100, 0b1011, 0b101>;
// SVE control registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureSVE} }] in {
-def : ROSysReg<"ID_AA64ZFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b100>;
+def : ROSysReg<"ID_AA64ZFR0_EL1", 0b1, 0b000, 0b0000, 0b0100, 0b100>;
}
// v8.1a "Limited Ordering Regions" extension-specific system register
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureLOR} }] in
-def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>;
+def : ROSysReg<"LORID_EL1", 0b1, 0b000, 0b1010, 0b0100, 0b111>;
// v8.2a "RAS extension" registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureRAS} }] in {
-def : ROSysReg<"ERRIDR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b000>;
-def : ROSysReg<"ERXFR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b000>;
+def : ROSysReg<"ERRIDR_EL1", 0b1, 0b000, 0b0101, 0b0011, 0b000>;
+def : ROSysReg<"ERXFR_EL1", 0b1, 0b000, 0b0101, 0b0100, 0b000>;
}
// v8.5a "random number" registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureRandGen} }] in {
-def : ROSysReg<"RNDR", 0b11, 0b011, 0b0010, 0b0100, 0b000>;
-def : ROSysReg<"RNDRRS", 0b11, 0b011, 0b0010, 0b0100, 0b001>;
+def : ROSysReg<"RNDR", 0b1, 0b011, 0b0010, 0b0100, 0b000>;
+def : ROSysReg<"RNDRRS", 0b1, 0b011, 0b0010, 0b0100, 0b001>;
}
// v8.5a Software Context Number registers
let Requires = [{ {AArch64::FeatureSpecRestrict} }] in {
-def : RWSysReg<"SCXTNUM_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b111>;
-def : RWSysReg<"SCXTNUM_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b111>;
-def : RWSysReg<"SCXTNUM_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b111>;
-def : RWSysReg<"SCXTNUM_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b111>;
-def : RWSysReg<"SCXTNUM_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b111>;
+def : RWSysReg<"SCXTNUM_EL0", 0b1, 0b011, 0b1101, 0b0000, 0b111>;
+def : RWSysReg<"SCXTNUM_EL1", 0b1, 0b000, 0b1101, 0b0000, 0b111>;
+def : RWSysReg<"SCXTNUM_EL2", 0b1, 0b100, 0b1101, 0b0000, 0b111>;
+def : RWSysReg<"SCXTNUM_EL3", 0b1, 0b110, 0b1101, 0b0000, 0b111>;
+def : RWSysReg<"SCXTNUM_EL12", 0b1, 0b101, 0b1101, 0b0000, 0b111>;
}
// v9a Realm Management Extension registers
let Requires = [{ {AArch64::FeatureRME} }] in {
-def : RWSysReg<"GPCCR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b110>;
-def : RWSysReg<"GPTBR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b100>;
+def : RWSysReg<"GPCCR_EL3", 0b1, 0b110, 0b0010, 0b0001, 0b110>;
+def : RWSysReg<"GPTBR_EL3", 0b1, 0b110, 0b0010, 0b0001, 0b100>;
}
// MFAR_EL3 is part of both FEAT_RME and FEAT_PFAR (further below). The latter
// is unconditional so this register has to be too.
-def : RWSysReg<"MFAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b101>;
+def : RWSysReg<"MFAR_EL3", 0b1, 0b110, 0b0110, 0b0000, 0b101>;
// v9a Memory Encryption Contexts Extension registers
let Requires = [{ {AArch64::FeatureMEC} }] in {
-def : ROSysReg<"MECIDR_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b111>;
-def : RWSysReg<"MECID_P0_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b000>;
-def : RWSysReg<"MECID_A0_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b001>;
-def : RWSysReg<"MECID_P1_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b010>;
-def : RWSysReg<"MECID_A1_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b011>;
-def : RWSysReg<"VMECID_P_EL2", 0b11, 0b100, 0b1010, 0b1001, 0b000>;
-def : RWSysReg<"VMECID_A_EL2", 0b11, 0b100, 0b1010, 0b1001, 0b001>;
-def : RWSysReg<"MECID_RL_A_EL3", 0b11, 0b110, 0b1010, 0b1010, 0b001>;
+def : ROSysReg<"MECIDR_EL2", 0b1, 0b100, 0b1010, 0b1000, 0b111>;
+def : RWSysReg<"MECID_P0_EL2", 0b1, 0b100, 0b1010, 0b1000, 0b000>;
+def : RWSysReg<"MECID_A0_EL2", 0b1, 0b100, 0b1010, 0b1000, 0b001>;
+def : RWSysReg<"MECID_P1_EL2", 0b1, 0b100, 0b1010, 0b1000, 0b010>;
+def : RWSysReg<"MECID_A1_EL2", 0b1, 0b100, 0b1010, 0b1000, 0b011>;
+def : RWSysReg<"VMECID_P_EL2", 0b1, 0b100, 0b1010, 0b1001, 0b000>;
+def : RWSysReg<"VMECID_A_EL2", 0b1, 0b100, 0b1010, 0b1001, 0b001>;
+def : RWSysReg<"MECID_RL_A_EL3", 0b1, 0b110, 0b1010, 0b1010, 0b001>;
}
// v9-a Scalable Matrix Extension (SME) registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureSME} }] in {
-def : ROSysReg<"ID_AA64SMFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b101>;
+def : ROSysReg<"ID_AA64SMFR0_EL1", 0b1, 0b000, 0b0000, 0b0100, 0b101>;
}
//===----------------------
@@ -1271,503 +1271,503 @@ def : ROSysReg<"ID_AA64SMFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b101>;
//===----------------------
// Op0 Op1 CRn CRm Op2
-def : WOSysReg<"DBGDTRTX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>;
-def : WOSysReg<"OSLAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b100>;
-def : WOSysReg<"PMSWINC_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b100>;
+def : WOSysReg<"DBGDTRTX_EL0", 0b0, 0b011, 0b0000, 0b0101, 0b000>;
+def : WOSysReg<"OSLAR_EL1", 0b0, 0b000, 0b0001, 0b0000, 0b100>;
+def : WOSysReg<"PMSWINC_EL0", 0b1, 0b011, 0b1001, 0b1100, 0b100>;
// Trace Registers
// Op0 Op1 CRn CRm Op2
-def : WOSysReg<"TRCOSLAR", 0b10, 0b001, 0b0001, 0b0000, 0b100>;
-def : WOSysReg<"TRCLAR", 0b10, 0b001, 0b0111, 0b1100, 0b110>;
+def : WOSysReg<"TRCOSLAR", 0b0, 0b001, 0b0001, 0b0000, 0b100>;
+def : WOSysReg<"TRCLAR", 0b0, 0b001, 0b0111, 0b1100, 0b110>;
// GICv3 registers
// Op0 Op1 CRn CRm Op2
-def : WOSysReg<"ICC_EOIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b001>;
-def : WOSysReg<"ICC_EOIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b001>;
-def : WOSysReg<"ICC_DIR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b001>;
-def : WOSysReg<"ICC_SGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b101>;
-def : WOSysReg<"ICC_ASGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b110>;
-def : WOSysReg<"ICC_SGI0R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b111>;
+def : WOSysReg<"ICC_EOIR1_EL1", 0b1, 0b000, 0b1100, 0b1100, 0b001>;
+def : WOSysReg<"ICC_EOIR0_EL1", 0b1, 0b000, 0b1100, 0b1000, 0b001>;
+def : WOSysReg<"ICC_DIR_EL1", 0b1, 0b000, 0b1100, 0b1011, 0b001>;
+def : WOSysReg<"ICC_SGI1R_EL1", 0b1, 0b000, 0b1100, 0b1011, 0b101>;
+def : WOSysReg<"ICC_ASGI1R_EL1", 0b1, 0b000, 0b1100, 0b1011, 0b110>;
+def : WOSysReg<"ICC_SGI0R_EL1", 0b1, 0b000, 0b1100, 0b1011, 0b111>;
//===----------------------
// Read-write regs
//===----------------------
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"OSDTRRX_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b010>;
-def : RWSysReg<"OSDTRTX_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b010>;
-def : RWSysReg<"TEECR32_EL1", 0b10, 0b010, 0b0000, 0b0000, 0b000>;
-def : RWSysReg<"MDCCINT_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b000>;
-def : RWSysReg<"MDSCR_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b010>;
-def : RWSysReg<"DBGDTR_EL0", 0b10, 0b011, 0b0000, 0b0100, 0b000>;
-def : RWSysReg<"OSECCR_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b010>;
-def : RWSysReg<"DBGVCR32_EL2", 0b10, 0b100, 0b0000, 0b0111, 0b000>;
+def : RWSysReg<"OSDTRRX_EL1", 0b0, 0b000, 0b0000, 0b0000, 0b010>;
+def : RWSysReg<"OSDTRTX_EL1", 0b0, 0b000, 0b0000, 0b0011, 0b010>;
+def : RWSysReg<"TEECR32_EL1", 0b0, 0b010, 0b0000, 0b0000, 0b000>;
+def : RWSysReg<"MDCCINT_EL1", 0b0, 0b000, 0b0000, 0b0010, 0b000>;
+def : RWSysReg<"MDSCR_EL1", 0b0, 0b000, 0b0000, 0b0010, 0b010>;
+def : RWSysReg<"DBGDTR_EL0", 0b0, 0b011, 0b0000, 0b0100, 0b000>;
+def : RWSysReg<"OSECCR_EL1", 0b0, 0b000, 0b0000, 0b0110, 0b010>;
+def : RWSysReg<"DBGVCR32_EL2", 0b0, 0b100, 0b0000, 0b0111, 0b000>;
foreach n = 0-15 in {
defvar nb = !cast<bits<4>>(n);
// Op0 Op1 CRn CRm Op2
- def : RWSysReg<"DBGBVR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b100>;
- def : RWSysReg<"DBGBCR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b101>;
- def : RWSysReg<"DBGWVR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b110>;
- def : RWSysReg<"DBGWCR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b111>;
+ def : RWSysReg<"DBGBVR"#n#"_EL1", 0b0, 0b000, 0b0000, nb, 0b100>;
+ def : RWSysReg<"DBGBCR"#n#"_EL1", 0b0, 0b000, 0b0000, nb, 0b101>;
+ def : RWSysReg<"DBGWVR"#n#"_EL1", 0b0, 0b000, 0b0000, nb, 0b110>;
+ def : RWSysReg<"DBGWCR"#n#"_EL1", 0b0, 0b000, 0b0000, nb, 0b111>;
}
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"TEEHBR32_EL1", 0b10, 0b010, 0b0001, 0b0000, 0b000>;
-def : RWSysReg<"OSDLR_EL1", 0b10, 0b000, 0b0001, 0b0011, 0b100>;
-def : RWSysReg<"DBGPRCR_EL1", 0b10, 0b000, 0b0001, 0b0100, 0b100>;
-def : RWSysReg<"DBGCLAIMSET_EL1", 0b10, 0b000, 0b0111, 0b1000, 0b110>;
-def : RWSysReg<"DBGCLAIMCLR_EL1", 0b10, 0b000, 0b0111, 0b1001, 0b110>;
-def : RWSysReg<"CSSELR_EL1", 0b11, 0b010, 0b0000, 0b0000, 0b000>;
-def : RWSysReg<"VPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b000>;
-def : RWSysReg<"VMPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b101>;
-def : RWSysReg<"CPACR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b010>;
-def : RWSysReg<"SCTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b000>;
-def : RWSysReg<"SCTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b000>;
-def : RWSysReg<"SCTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b000>;
-def : RWSysReg<"ACTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b001>;
-def : RWSysReg<"ACTLR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b001>;
-def : RWSysReg<"ACTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b001>;
-def : RWSysReg<"ACTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b001>;
-def : RWSysReg<"HCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b000>;
-def : RWSysReg<"HCRX_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b010> {
+def : RWSysReg<"TEEHBR32_EL1", 0b0, 0b010, 0b0001, 0b0000, 0b000>;
+def : RWSysReg<"OSDLR_EL1", 0b0, 0b000, 0b0001, 0b0011, 0b100>;
+def : RWSysReg<"DBGPRCR_EL1", 0b0, 0b000, 0b0001, 0b0100, 0b100>;
+def : RWSysReg<"DBGCLAIMSET_EL1", 0b0, 0b000, 0b0111, 0b1000, 0b110>;
+def : RWSysReg<"DBGCLAIMCLR_EL1", 0b0, 0b000, 0b0111, 0b1001, 0b110>;
+def : RWSysReg<"CSSELR_EL1", 0b1, 0b010, 0b0000, 0b0000, 0b000>;
+def : RWSysReg<"VPIDR_EL2", 0b1, 0b100, 0b0000, 0b0000, 0b000>;
+def : RWSysReg<"VMPIDR_EL2", 0b1, 0b100, 0b0000, 0b0000, 0b101>;
+def : RWSysReg<"CPACR_EL1", 0b1, 0b000, 0b0001, 0b0000, 0b010>;
+def : RWSysReg<"SCTLR_EL1", 0b1, 0b000, 0b0001, 0b0000, 0b000>;
+def : RWSysReg<"SCTLR_EL2", 0b1, 0b100, 0b0001, 0b0000, 0b000>;
+def : RWSysReg<"SCTLR_EL3", 0b1, 0b110, 0b0001, 0b0000, 0b000>;
+def : RWSysReg<"ACTLR_EL1", 0b1, 0b000, 0b0001, 0b0000, 0b001>;
+def : RWSysReg<"ACTLR_EL12", 0b1, 0b101, 0b0001, 0b0000, 0b001>;
+def : RWSysReg<"ACTLR_EL2", 0b1, 0b100, 0b0001, 0b0000, 0b001>;
+def : RWSysReg<"ACTLR_EL3", 0b1, 0b110, 0b0001, 0b0000, 0b001>;
+def : RWSysReg<"HCR_EL2", 0b1, 0b100, 0b0001, 0b0001, 0b000>;
+def : RWSysReg<"HCRX_EL2", 0b1, 0b100, 0b0001, 0b0010, 0b010> {
let Requires = [{ {AArch64::FeatureHCX} }];
}
-def : RWSysReg<"SCR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b000>;
-def : RWSysReg<"MDCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b001>;
-def : RWSysReg<"SDER32_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b001>;
-def : RWSysReg<"CPTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b010>;
-def : RWSysReg<"CPTR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b010>;
-def : RWSysReg<"HSTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b011>;
-def : RWSysReg<"HACR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b111>;
-def : RWSysReg<"MDCR_EL3", 0b11, 0b110, 0b0001, 0b0011, 0b001>;
-def : RWSysReg<"TTBR0_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b000>;
-def : RWSysReg<"TTBR0_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b000>;
+def : RWSysReg<"SCR_EL3", 0b1, 0b110, 0b0001, 0b0001, 0b000>;
+def : RWSysReg<"MDCR_EL2", 0b1, 0b100, 0b0001, 0b0001, 0b001>;
+def : RWSysReg<"SDER32_EL3", 0b1, 0b110, 0b0001, 0b0001, 0b001>;
+def : RWSysReg<"CPTR_EL2", 0b1, 0b100, 0b0001, 0b0001, 0b010>;
+def : RWSysReg<"CPTR_EL3", 0b1, 0b110, 0b0001, 0b0001, 0b010>;
+def : RWSysReg<"HSTR_EL2", 0b1, 0b100, 0b0001, 0b0001, 0b011>;
+def : RWSysReg<"HACR_EL2", 0b1, 0b100, 0b0001, 0b0001, 0b111>;
+def : RWSysReg<"MDCR_EL3", 0b1, 0b110, 0b0001, 0b0011, 0b001>;
+def : RWSysReg<"TTBR0_EL1", 0b1, 0b000, 0b0010, 0b0000, 0b000>;
+def : RWSysReg<"TTBR0_EL3", 0b1, 0b110, 0b0010, 0b0000, 0b000>;
let Requires = [{ {AArch64::FeatureEL2VMSA} }] in {
-def : RWSysReg<"TTBR0_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000>;
-def : RWSysReg<"VTTBR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b000>;
-}
-
-def : RWSysReg<"TTBR1_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b001>;
-def : RWSysReg<"TCR_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b010>;
-def : RWSysReg<"TCR_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b010>;
-def : RWSysReg<"TCR_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b010>;
-def : RWSysReg<"VTCR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b010>;
-def : RWSysReg<"DACR32_EL2", 0b11, 0b100, 0b0011, 0b0000, 0b000>;
-def : RWSysReg<"SPSR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b000>;
-def : RWSysReg<"SPSR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b000>;
-def : RWSysReg<"SPSR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b000>;
-def : RWSysReg<"ELR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b001>;
-def : RWSysReg<"ELR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b001>;
-def : RWSysReg<"ELR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b001>;
-def : RWSysReg<"SP_EL0", 0b11, 0b000, 0b0100, 0b0001, 0b000>;
-def : RWSysReg<"SP_EL1", 0b11, 0b100, 0b0100, 0b0001, 0b000>;
-def : RWSysReg<"SP_EL2", 0b11, 0b110, 0b0100, 0b0001, 0b000>;
-def : RWSysReg<"SPSel", 0b11, 0b000, 0b0100, 0b0010, 0b000>;
-def : RWSysReg<"NZCV", 0b11, 0b011, 0b0100, 0b0010, 0b000>;
-def : RWSysReg<"DAIF", 0b11, 0b011, 0b0100, 0b0010, 0b001>;
-def : ROSysReg<"CurrentEL", 0b11, 0b000, 0b0100, 0b0010, 0b010>;
-def : RWSysReg<"SPSR_irq", 0b11, 0b100, 0b0100, 0b0011, 0b000>;
-def : RWSysReg<"SPSR_abt", 0b11, 0b100, 0b0100, 0b0011, 0b001>;
-def : RWSysReg<"SPSR_und", 0b11, 0b100, 0b0100, 0b0011, 0b010>;
-def : RWSysReg<"SPSR_fiq", 0b11, 0b100, 0b0100, 0b0011, 0b011>;
+def : RWSysReg<"TTBR0_EL2", 0b1, 0b100, 0b0010, 0b0000, 0b000>;
+def : RWSysReg<"VTTBR_EL2", 0b1, 0b100, 0b0010, 0b0001, 0b000>;
+}
+
+def : RWSysReg<"TTBR1_EL1", 0b1, 0b000, 0b0010, 0b0000, 0b001>;
+def : RWSysReg<"TCR_EL1", 0b1, 0b000, 0b0010, 0b0000, 0b010>;
+def : RWSysReg<"TCR_EL2", 0b1, 0b100, 0b0010, 0b0000, 0b010>;
+def : RWSysReg<"TCR_EL3", 0b1, 0b110, 0b0010, 0b0000, 0b010>;
+def : RWSysReg<"VTCR_EL2", 0b1, 0b100, 0b0010, 0b0001, 0b010>;
+def : RWSysReg<"DACR32_EL2", 0b1, 0b100, 0b0011, 0b0000, 0b000>;
+def : RWSysReg<"SPSR_EL1", 0b1, 0b000, 0b0100, 0b0000, 0b000>;
+def : RWSysReg<"SPSR_EL2", 0b1, 0b100, 0b0100, 0b0000, 0b000>;
+def : RWSysReg<"SPSR_EL3", 0b1, 0b110, 0b0100, 0b0000, 0b000>;
+def : RWSysReg<"ELR_EL1", 0b1, 0b000, 0b0100, 0b0000, 0b001>;
+def : RWSysReg<"ELR_EL2", 0b1, 0b100, 0b0100, 0b0000, 0b001>;
+def : RWSysReg<"ELR_EL3", 0b1, 0b110, 0b0100, 0b0000, 0b001>;
+def : RWSysReg<"SP_EL0", 0b1, 0b000, 0b0100, 0b0001, 0b000>;
+def : RWSysReg<"SP_EL1", 0b1, 0b100, 0b0100, 0b0001, 0b000>;
+def : RWSysReg<"SP_EL2", 0b1, 0b110, 0b0100, 0b0001, 0b000>;
+def : RWSysReg<"SPSel", 0b1, 0b000, 0b0100, 0b0010, 0b000>;
+def : RWSysReg<"NZCV", 0b1, 0b011, 0b0100, 0b0010, 0b000>;
+def : RWSysReg<"DAIF", 0b1, 0b011, 0b0100, 0b0010, 0b001>;
+def : ROSysReg<"CurrentEL", 0b1, 0b000, 0b0100, 0b0010, 0b010>;
+def : RWSysReg<"SPSR_irq", 0b1, 0b100, 0b0100, 0b0011, 0b000>;
+def : RWSysReg<"SPSR_abt", 0b1, 0b100, 0b0100, 0b0011, 0b001>;
+def : RWSysReg<"SPSR_und", 0b1, 0b100, 0b0100, 0b0011, 0b010>;
+def : RWSysReg<"SPSR_fiq", 0b1, 0b100, 0b0100, 0b0011, 0b011>;
let Requires = [{ {AArch64::FeatureFPARMv8} }] in {
-def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>;
-def : RWSysReg<"FPSR", 0b11, 0b011, 0b0100, 0b0100, 0b001>;
-}
-def : RWSysReg<"DSPSR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b000>;
-def : RWSysReg<"DLR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b001>;
-def : RWSysReg<"IFSR32_EL2", 0b11, 0b100, 0b0101, 0b0000, 0b001>;
-def : RWSysReg<"AFSR0_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b000>;
-def : RWSysReg<"AFSR0_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b000>;
-def : RWSysReg<"AFSR0_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b000>;
-def : RWSysReg<"AFSR1_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b001>;
-def : RWSysReg<"AFSR1_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b001>;
-def : RWSysReg<"AFSR1_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b001>;
-def : RWSysReg<"ESR_EL1", 0b11, 0b000, 0b0101, 0b0010, 0b000>;
-def : RWSysReg<"ESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b000>;
-def : RWSysReg<"ESR_EL3", 0b11, 0b110, 0b0101, 0b0010, 0b000>;
-def : RWSysReg<"FPEXC32_EL2", 0b11, 0b100, 0b0101, 0b0011, 0b000>;
-def : RWSysReg<"FAR_EL1", 0b11, 0b000, 0b0110, 0b0000, 0b000>;
-def : RWSysReg<"FAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b000>;
-def : RWSysReg<"FAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b000>;
-def : RWSysReg<"HPFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b100>;
-def : RWSysReg<"PAR_EL1", 0b11, 0b000, 0b0111, 0b0100, 0b000>;
-def : RWSysReg<"PMCR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b000>;
-def : RWSysReg<"PMCNTENSET_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b001>;
-def : RWSysReg<"PMCNTENCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b010>;
-def : RWSysReg<"PMOVSCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b011>;
-def : RWSysReg<"PMSELR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b101>;
-def : RWSysReg<"PMCCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b000>;
-def : RWSysReg<"PMXEVTYPER_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b001>;
-def : RWSysReg<"PMXEVCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b010>;
-def : RWSysReg<"PMUSERENR_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b000>;
-def : RWSysReg<"PMINTENSET_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b001>;
-def : RWSysReg<"PMINTENCLR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b010>;
-def : RWSysReg<"PMOVSSET_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b011>;
-def : RWSysReg<"MAIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b000>;
-def : RWSysReg<"MAIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b000>;
-def : RWSysReg<"MAIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b000>;
-def : RWSysReg<"AMAIR_EL1", 0b11, 0b000, 0b1010, 0b0011, 0b000>;
-def : RWSysReg<"AMAIR_EL2", 0b11, 0b100, 0b1010, 0b0011, 0b000>;
-def : RWSysReg<"AMAIR_EL3", 0b11, 0b110, 0b1010, 0b0011, 0b000>;
-def : RWSysReg<"VBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b000>;
-def : RWSysReg<"VBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b000>;
-def : RWSysReg<"VBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b000>;
-def : RWSysReg<"RMR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b010>;
-def : RWSysReg<"RMR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b010>;
-def : RWSysReg<"RMR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b010>;
-def : RWSysReg<"CONTEXTIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b001>;
-def : RWSysReg<"TPIDR_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b010>;
-def : RWSysReg<"TPIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b010>;
-def : RWSysReg<"TPIDR_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b010>;
-def : RWSysReg<"TPIDRRO_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b011>;
-def : RWSysReg<"TPIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b100>;
-def : RWSysReg<"CNTFRQ_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b000>;
-def : RWSysReg<"CNTVOFF_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b011>;
-def : RWSysReg<"CNTKCTL_EL1", 0b11, 0b000, 0b1110, 0b0001, 0b000>;
-def : RWSysReg<"CNTHCTL_EL2", 0b11, 0b100, 0b1110, 0b0001, 0b000>;
-def : RWSysReg<"CNTP_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b000>;
-def : RWSysReg<"CNTHP_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b000>;
-def : RWSysReg<"CNTPS_TVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b000>;
-def : RWSysReg<"CNTP_CTL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b001>;
-def : RWSysReg<"CNTHP_CTL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b001>;
-def : RWSysReg<"CNTPS_CTL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b001>;
-def : RWSysReg<"CNTP_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b010>;
-def : RWSysReg<"CNTHP_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b010>;
-def : RWSysReg<"CNTPS_CVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b010>;
-def : RWSysReg<"CNTV_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b000>;
-def : RWSysReg<"CNTV_CTL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b001>;
-def : RWSysReg<"CNTV_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b010>;
-def : RWSysReg<"PMEVCNTR0_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b000>;
-def : RWSysReg<"PMEVCNTR1_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b001>;
-def : RWSysReg<"PMEVCNTR2_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b010>;
-def : RWSysReg<"PMEVCNTR3_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b011>;
-def : RWSysReg<"PMEVCNTR4_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b100>;
-def : RWSysReg<"PMEVCNTR5_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b101>;
-def : RWSysReg<"PMEVCNTR6_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b110>;
-def : RWSysReg<"PMEVCNTR7_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b111>;
-def : RWSysReg<"PMEVCNTR8_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b000>;
-def : RWSysReg<"PMEVCNTR9_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b001>;
-def : RWSysReg<"PMEVCNTR10_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b010>;
-def : RWSysReg<"PMEVCNTR11_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b011>;
-def : RWSysReg<"PMEVCNTR12_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b100>;
-def : RWSysReg<"PMEVCNTR13_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b101>;
-def : RWSysReg<"PMEVCNTR14_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b110>;
-def : RWSysReg<"PMEVCNTR15_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b111>;
-def : RWSysReg<"PMEVCNTR16_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b000>;
-def : RWSysReg<"PMEVCNTR17_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b001>;
-def : RWSysReg<"PMEVCNTR18_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b010>;
-def : RWSysReg<"PMEVCNTR19_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b011>;
-def : RWSysReg<"PMEVCNTR20_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b100>;
-def : RWSysReg<"PMEVCNTR21_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b101>;
-def : RWSysReg<"PMEVCNTR22_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b110>;
-def : RWSysReg<"PMEVCNTR23_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b111>;
-def : RWSysReg<"PMEVCNTR24_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b000>;
-def : RWSysReg<"PMEVCNTR25_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b001>;
-def : RWSysReg<"PMEVCNTR26_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b010>;
-def : RWSysReg<"PMEVCNTR27_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b011>;
-def : RWSysReg<"PMEVCNTR28_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b100>;
-def : RWSysReg<"PMEVCNTR29_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b101>;
-def : RWSysReg<"PMEVCNTR30_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b110>;
-def : RWSysReg<"PMCCFILTR_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b111>;
-def : RWSysReg<"PMEVTYPER0_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b000>;
-def : RWSysReg<"PMEVTYPER1_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b001>;
-def : RWSysReg<"PMEVTYPER2_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b010>;
-def : RWSysReg<"PMEVTYPER3_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b011>;
-def : RWSysReg<"PMEVTYPER4_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b100>;
-def : RWSysReg<"PMEVTYPER5_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b101>;
-def : RWSysReg<"PMEVTYPER6_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b110>;
-def : RWSysReg<"PMEVTYPER7_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b111>;
-def : RWSysReg<"PMEVTYPER8_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b000>;
-def : RWSysReg<"PMEVTYPER9_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b001>;
-def : RWSysReg<"PMEVTYPER10_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b010>;
-def : RWSysReg<"PMEVTYPER11_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b011>;
-def : RWSysReg<"PMEVTYPER12_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b100>;
-def : RWSysReg<"PMEVTYPER13_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b101>;
-def : RWSysReg<"PMEVTYPER14_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b110>;
-def : RWSysReg<"PMEVTYPER15_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b111>;
-def : RWSysReg<"PMEVTYPER16_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b000>;
-def : RWSysReg<"PMEVTYPER17_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b001>;
-def : RWSysReg<"PMEVTYPER18_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b010>;
-def : RWSysReg<"PMEVTYPER19_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b011>;
-def : RWSysReg<"PMEVTYPER20_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b100>;
-def : RWSysReg<"PMEVTYPER21_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b101>;
-def : RWSysReg<"PMEVTYPER22_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b110>;
-def : RWSysReg<"PMEVTYPER23_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b111>;
-def : RWSysReg<"PMEVTYPER24_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b000>;
-def : RWSysReg<"PMEVTYPER25_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b001>;
-def : RWSysReg<"PMEVTYPER26_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b010>;
-def : RWSysReg<"PMEVTYPER27_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b011>;
-def : RWSysReg<"PMEVTYPER28_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b100>;
-def : RWSysReg<"PMEVTYPER29_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b101>;
-def : RWSysReg<"PMEVTYPER30_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b110>;
+def : RWSysReg<"FPCR", 0b1, 0b011, 0b0100, 0b0100, 0b000>;
+def : RWSysReg<"FPSR", 0b1, 0b011, 0b0100, 0b0100, 0b001>;
+}
+def : RWSysReg<"DSPSR_EL0", 0b1, 0b011, 0b0100, 0b0101, 0b000>;
+def : RWSysReg<"DLR_EL0", 0b1, 0b011, 0b0100, 0b0101, 0b001>;
+def : RWSysReg<"IFSR32_EL2", 0b1, 0b100, 0b0101, 0b0000, 0b001>;
+def : RWSysReg<"AFSR0_EL1", 0b1, 0b000, 0b0101, 0b0001, 0b000>;
+def : RWSysReg<"AFSR0_EL2", 0b1, 0b100, 0b0101, 0b0001, 0b000>;
+def : RWSysReg<"AFSR0_EL3", 0b1, 0b110, 0b0101, 0b0001, 0b000>;
+def : RWSysReg<"AFSR1_EL1", 0b1, 0b000, 0b0101, 0b0001, 0b001>;
+def : RWSysReg<"AFSR1_EL2", 0b1, 0b100, 0b0101, 0b0001, 0b001>;
+def : RWSysReg<"AFSR1_EL3", 0b1, 0b110, 0b0101, 0b0001, 0b001>;
+def : RWSysReg<"ESR_EL1", 0b1, 0b000, 0b0101, 0b0010, 0b000>;
+def : RWSysReg<"ESR_EL2", 0b1, 0b100, 0b0101, 0b0010, 0b000>;
+def : RWSysReg<"ESR_EL3", 0b1, 0b110, 0b0101, 0b0010, 0b000>;
+def : RWSysReg<"FPEXC32_EL2", 0b1, 0b100, 0b0101, 0b0011, 0b000>;
+def : RWSysReg<"FAR_EL1", 0b1, 0b000, 0b0110, 0b0000, 0b000>;
+def : RWSysReg<"FAR_EL2", 0b1, 0b100, 0b0110, 0b0000, 0b000>;
+def : RWSysReg<"FAR_EL3", 0b1, 0b110, 0b0110, 0b0000, 0b000>;
+def : RWSysReg<"HPFAR_EL2", 0b1, 0b100, 0b0110, 0b0000, 0b100>;
+def : RWSysReg<"PAR_EL1", 0b1, 0b000, 0b0111, 0b0100, 0b000>;
+def : RWSysReg<"PMCR_EL0", 0b1, 0b011, 0b1001, 0b1100, 0b000>;
+def : RWSysReg<"PMCNTENSET_EL0", 0b1, 0b011, 0b1001, 0b1100, 0b001>;
+def : RWSysReg<"PMCNTENCLR_EL0", 0b1, 0b011, 0b1001, 0b1100, 0b010>;
+def : RWSysReg<"PMOVSCLR_EL0", 0b1, 0b011, 0b1001, 0b1100, 0b011>;
+def : RWSysReg<"PMSELR_EL0", 0b1, 0b011, 0b1001, 0b1100, 0b101>;
+def : RWSysReg<"PMCCNTR_EL0", 0b1, 0b011, 0b1001, 0b1101, 0b000>;
+def : RWSysReg<"PMXEVTYPER_EL0", 0b1, 0b011, 0b1001, 0b1101, 0b001>;
+def : RWSysReg<"PMXEVCNTR_EL0", 0b1, 0b011, 0b1001, 0b1101, 0b010>;
+def : RWSysReg<"PMUSERENR_EL0", 0b1, 0b011, 0b1001, 0b1110, 0b000>;
+def : RWSysReg<"PMINTENSET_EL1", 0b1, 0b000, 0b1001, 0b1110, 0b001>;
+def : RWSysReg<"PMINTENCLR_EL1", 0b1, 0b000, 0b1001, 0b1110, 0b010>;
+def : RWSysReg<"PMOVSSET_EL0", 0b1, 0b011, 0b1001, 0b1110, 0b011>;
+def : RWSysReg<"MAIR_EL1", 0b1, 0b000, 0b1010, 0b0010, 0b000>;
+def : RWSysReg<"MAIR_EL2", 0b1, 0b100, 0b1010, 0b0010, 0b000>;
+def : RWSysReg<"MAIR_EL3", 0b1, 0b110, 0b1010, 0b0010, 0b000>;
+def : RWSysReg<"AMAIR_EL1", 0b1, 0b000, 0b1010, 0b0011, 0b000>;
+def : RWSysReg<"AMAIR_EL2", 0b1, 0b100, 0b1010, 0b0011, 0b000>;
+def : RWSysReg<"AMAIR_EL3", 0b1, 0b110, 0b1010, 0b0011, 0b000>;
+def : RWSysReg<"VBAR_EL1", 0b1, 0b000, 0b1100, 0b0000, 0b000>;
+def : RWSysReg<"VBAR_EL2", 0b1, 0b100, 0b1100, 0b0000, 0b000>;
+def : RWSysReg<"VBAR_EL3", 0b1, 0b110, 0b1100, 0b0000, 0b000>;
+def : RWSysReg<"RMR_EL1", 0b1, 0b000, 0b1100, 0b0000, 0b010>;
+def : RWSysReg<"RMR_EL2", 0b1, 0b100, 0b1100, 0b0000, 0b010>;
+def : RWSysReg<"RMR_EL3", 0b1, 0b110, 0b1100, 0b0000, 0b010>;
+def : RWSysReg<"CONTEXTIDR_EL1", 0b1, 0b000, 0b1101, 0b0000, 0b001>;
+def : RWSysReg<"TPIDR_EL0", 0b1, 0b011, 0b1101, 0b0000, 0b010>;
+def : RWSysReg<"TPIDR_EL2", 0b1, 0b100, 0b1101, 0b0000, 0b010>;
+def : RWSysReg<"TPIDR_EL3", 0b1, 0b110, 0b1101, 0b0000, 0b010>;
+def : RWSysReg<"TPIDRRO_EL0", 0b1, 0b011, 0b1101, 0b0000, 0b011>;
+def : RWSysReg<"TPIDR_EL1", 0b1, 0b000, 0b1101, 0b0000, 0b100>;
+def : RWSysReg<"CNTFRQ_EL0", 0b1, 0b011, 0b1110, 0b0000, 0b000>;
+def : RWSysReg<"CNTVOFF_EL2", 0b1, 0b100, 0b1110, 0b0000, 0b011>;
+def : RWSysReg<"CNTKCTL_EL1", 0b1, 0b000, 0b1110, 0b0001, 0b000>;
+def : RWSysReg<"CNTHCTL_EL2", 0b1, 0b100, 0b1110, 0b0001, 0b000>;
+def : RWSysReg<"CNTP_TVAL_EL0", 0b1, 0b011, 0b1110, 0b0010, 0b000>;
+def : RWSysReg<"CNTHP_TVAL_EL2", 0b1, 0b100, 0b1110, 0b0010, 0b000>;
+def : RWSysReg<"CNTPS_TVAL_EL1", 0b1, 0b111, 0b1110, 0b0010, 0b000>;
+def : RWSysReg<"CNTP_CTL_EL0", 0b1, 0b011, 0b1110, 0b0010, 0b001>;
+def : RWSysReg<"CNTHP_CTL_EL2", 0b1, 0b100, 0b1110, 0b0010, 0b001>;
+def : RWSysReg<"CNTPS_CTL_EL1", 0b1, 0b111, 0b1110, 0b0010, 0b001>;
+def : RWSysReg<"CNTP_CVAL_EL0", 0b1, 0b011, 0b1110, 0b0010, 0b010>;
+def : RWSysReg<"CNTHP_CVAL_EL2", 0b1, 0b100, 0b1110, 0b0010, 0b010>;
+def : RWSysReg<"CNTPS_CVAL_EL1", 0b1, 0b111, 0b1110, 0b0010, 0b010>;
+def : RWSysReg<"CNTV_TVAL_EL0", 0b1, 0b011, 0b1110, 0b0011, 0b000>;
+def : RWSysReg<"CNTV_CTL_EL0", 0b1, 0b011, 0b1110, 0b0011, 0b001>;
+def : RWSysReg<"CNTV_CVAL_EL0", 0b1, 0b011, 0b1110, 0b0011, 0b010>;
+def : RWSysReg<"PMEVCNTR0_EL0", 0b1, 0b011, 0b1110, 0b1000, 0b000>;
+def : RWSysReg<"PMEVCNTR1_EL0", 0b1, 0b011, 0b1110, 0b1000, 0b001>;
+def : RWSysReg<"PMEVCNTR2_EL0", 0b1, 0b011, 0b1110, 0b1000, 0b010>;
+def : RWSysReg<"PMEVCNTR3_EL0", 0b1, 0b011, 0b1110, 0b1000, 0b011>;
+def : RWSysReg<"PMEVCNTR4_EL0", 0b1, 0b011, 0b1110, 0b1000, 0b100>;
+def : RWSysReg<"PMEVCNTR5_EL0", 0b1, 0b011, 0b1110, 0b1000, 0b101>;
+def : RWSysReg<"PMEVCNTR6_EL0", 0b1, 0b011, 0b1110, 0b1000, 0b110>;
+def : RWSysReg<"PMEVCNTR7_EL0", 0b1, 0b011, 0b1110, 0b1000, 0b111>;
+def : RWSysReg<"PMEVCNTR8_EL0", 0b1, 0b011, 0b1110, 0b1001, 0b000>;
+def : RWSysReg<"PMEVCNTR9_EL0", 0b1, 0b011, 0b1110, 0b1001, 0b001>;
+def : RWSysReg<"PMEVCNTR10_EL0", 0b1, 0b011, 0b1110, 0b1001, 0b010>;
+def : RWSysReg<"PMEVCNTR11_EL0", 0b1, 0b011, 0b1110, 0b1001, 0b011>;
+def : RWSysReg<"PMEVCNTR12_EL0", 0b1, 0b011, 0b1110, 0b1001, 0b100>;
+def : RWSysReg<"PMEVCNTR13_EL0", 0b1, 0b011, 0b1110, 0b1001, 0b101>;
+def : RWSysReg<"PMEVCNTR14_EL0", 0b1, 0b011, 0b1110, 0b1001, 0b110>;
+def : RWSysReg<"PMEVCNTR15_EL0", 0b1, 0b011, 0b1110, 0b1001, 0b111>;
+def : RWSysReg<"PMEVCNTR16_EL0", 0b1, 0b011, 0b1110, 0b1010, 0b000>;
+def : RWSysReg<"PMEVCNTR17_EL0", 0b1, 0b011, 0b1110, 0b1010, 0b001>;
+def : RWSysReg<"PMEVCNTR18_EL0", 0b1, 0b011, 0b1110, 0b1010, 0b010>;
+def : RWSysReg<"PMEVCNTR19_EL0", 0b1, 0b011, 0b1110, 0b1010, 0b011>;
+def : RWSysReg<"PMEVCNTR20_EL0", 0b1, 0b011, 0b1110, 0b1010, 0b100>;
+def : RWSysReg<"PMEVCNTR21_EL0", 0b1, 0b011, 0b1110, 0b1010, 0b101>;
+def : RWSysReg<"PMEVCNTR22_EL0", 0b1, 0b011, 0b1110, 0b1010, 0b110>;
+def : RWSysReg<"PMEVCNTR23_EL0", 0b1, 0b011, 0b1110, 0b1010, 0b111>;
+def : RWSysReg<"PMEVCNTR24_EL0", 0b1, 0b011, 0b1110, 0b1011, 0b000>;
+def : RWSysReg<"PMEVCNTR25_EL0", 0b1, 0b011, 0b1110, 0b1011, 0b001>;
+def : RWSysReg<"PMEVCNTR26_EL0", 0b1, 0b011, 0b1110, 0b1011, 0b010>;
+def : RWSysReg<"PMEVCNTR27_EL0", 0b1, 0b011, 0b1110, 0b1011, 0b011>;
+def : RWSysReg<"PMEVCNTR28_EL0", 0b1, 0b011, 0b1110, 0b1011, 0b100>;
+def : RWSysReg<"PMEVCNTR29_EL0", 0b1, 0b011, 0b1110, 0b1011, 0b101>;
+def : RWSysReg<"PMEVCNTR30_EL0", 0b1, 0b011, 0b1110, 0b1011, 0b110>;
+def : RWSysReg<"PMCCFILTR_EL0", 0b1, 0b011, 0b1110, 0b1111, 0b111>;
+def : RWSysReg<"PMEVTYPER0_EL0", 0b1, 0b011, 0b1110, 0b1100, 0b000>;
+def : RWSysReg<"PMEVTYPER1_EL0", 0b1, 0b011, 0b1110, 0b1100, 0b001>;
+def : RWSysReg<"PMEVTYPER2_EL0", 0b1, 0b011, 0b1110, 0b1100, 0b010>;
+def : RWSysReg<"PMEVTYPER3_EL0", 0b1, 0b011, 0b1110, 0b1100, 0b011>;
+def : RWSysReg<"PMEVTYPER4_EL0", 0b1, 0b011, 0b1110, 0b1100, 0b100>;
+def : RWSysReg<"PMEVTYPER5_EL0", 0b1, 0b011, 0b1110, 0b1100, 0b101>;
+def : RWSysReg<"PMEVTYPER6_EL0", 0b1, 0b011, 0b1110, 0b1100, 0b110>;
+def : RWSysReg<"PMEVTYPER7_EL0", 0b1, 0b011, 0b1110, 0b1100, 0b111>;
+def : RWSysReg<"PMEVTYPER8_EL0", 0b1, 0b011, 0b1110, 0b1101, 0b000>;
+def : RWSysReg<"PMEVTYPER9_EL0", 0b1, 0b011, 0b1110, 0b1101, 0b001>;
+def : RWSysReg<"PMEVTYPER10_EL0", 0b1, 0b011, 0b1110, 0b1101, 0b010>;
+def : RWSysReg<"PMEVTYPER11_EL0", 0b1, 0b011, 0b1110, 0b1101, 0b011>;
+def : RWSysReg<"PMEVTYPER12_EL0", 0b1, 0b011, 0b1110, 0b1101, 0b100>;
+def : RWSysReg<"PMEVTYPER13_EL0", 0b1, 0b011, 0b1110, 0b1101, 0b101>;
+def : RWSysReg<"PMEVTYPER14_EL0", 0b1, 0b011, 0b1110, 0b1101, 0b110>;
+def : RWSysReg<"PMEVTYPER15_EL0", 0b1, 0b011, 0b1110, 0b1101, 0b111>;
+def : RWSysReg<"PMEVTYPER16_EL0", 0b1, 0b011, 0b1110, 0b1110, 0b000>;
+def : RWSysReg<"PMEVTYPER17_EL0", 0b1, 0b011, 0b1110, 0b1110, 0b001>;
+def : RWSysReg<"PMEVTYPER18_EL0", 0b1, 0b011, 0b1110, 0b1110, 0b010>;
+def : RWSysReg<"PMEVTYPER19_EL0", 0b1, 0b011, 0b1110, 0b1110, 0b011>;
+def : RWSysReg<"PMEVTYPER20_EL0", 0b1, 0b011, 0b1110, 0b1110, 0b100>;
+def : RWSysReg<"PMEVTYPER21_EL0", 0b1, 0b011, 0b1110, 0b1110, 0b101>;
+def : RWSysReg<"PMEVTYPER22_EL0", 0b1, 0b011, 0b1110, 0b1110, 0b110>;
+def : RWSysReg<"PMEVTYPER23_EL0", 0b1, 0b011, 0b1110, 0b1110, 0b111>;
+def : RWSysReg<"PMEVTYPER24_EL0", 0b1, 0b011, 0b1110, 0b1111, 0b000>;
+def : RWSysReg<"PMEVTYPER25_EL0", 0b1, 0b011, 0b1110, 0b1111, 0b001>;
+def : RWSysReg<"PMEVTYPER26_EL0", 0b1, 0b011, 0b1110, 0b1111, 0b010>;
+def : RWSysReg<"PMEVTYPER27_EL0", 0b1, 0b011, 0b1110, 0b1111, 0b011>;
+def : RWSysReg<"PMEVTYPER28_EL0", 0b1, 0b011, 0b1110, 0b1111, 0b100>;
+def : RWSysReg<"PMEVTYPER29_EL0", 0b1, 0b011, 0b1110, 0b1111, 0b101>;
+def : RWSysReg<"PMEVTYPER30_EL0", 0b1, 0b011, 0b1110, 0b1111, 0b110>;
// Trace registers
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"TRCPRGCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b000>;
-def : RWSysReg<"TRCPROCSELR", 0b10, 0b001, 0b0000, 0b0010, 0b000>;
-def : RWSysReg<"TRCCONFIGR", 0b10, 0b001, 0b0000, 0b0100, 0b000>;
-def : RWSysReg<"TRCAUXCTLR", 0b10, 0b001, 0b0000, 0b0110, 0b000>;
-def : RWSysReg<"TRCEVENTCTL0R", 0b10, 0b001, 0b0000, 0b1000, 0b000>;
-def : RWSysReg<"TRCEVENTCTL1R", 0b10, 0b001, 0b0000, 0b1001, 0b000>;
-def : RWSysReg<"TRCSTALLCTLR", 0b10, 0b001, 0b0000, 0b1011, 0b000>;
-def : RWSysReg<"TRCTSCTLR", 0b10, 0b001, 0b0000, 0b1100, 0b000>;
-def : RWSysReg<"TRCSYNCPR", 0b10, 0b001, 0b0000, 0b1101, 0b000>;
-def : RWSysReg<"TRCCCCTLR", 0b10, 0b001, 0b0000, 0b1110, 0b000>;
-def : RWSysReg<"TRCBBCTLR", 0b10, 0b001, 0b0000, 0b1111, 0b000>;
-def : RWSysReg<"TRCTRACEIDR", 0b10, 0b001, 0b0000, 0b0000, 0b001>;
-def : RWSysReg<"TRCQCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b001>;
-def : RWSysReg<"TRCVICTLR", 0b10, 0b001, 0b0000, 0b0000, 0b010>;
-def : RWSysReg<"TRCVIIECTLR", 0b10, 0b001, 0b0000, 0b0001, 0b010>;
-def : RWSysReg<"TRCVISSCTLR", 0b10, 0b001, 0b0000, 0b0010, 0b010>;
-def : RWSysReg<"TRCVIPCSSCTLR", 0b10, 0b001, 0b0000, 0b0011, 0b010>;
-def : RWSysReg<"TRCVDCTLR", 0b10, 0b001, 0b0000, 0b1000, 0b010>;
-def : RWSysReg<"TRCVDSACCTLR", 0b10, 0b001, 0b0000, 0b1001, 0b010>;
-def : RWSysReg<"TRCVDARCCTLR", 0b10, 0b001, 0b0000, 0b1010, 0b010>;
-def : RWSysReg<"TRCSEQEVR0", 0b10, 0b001, 0b0000, 0b0000, 0b100>;
-def : RWSysReg<"TRCSEQEVR1", 0b10, 0b001, 0b0000, 0b0001, 0b100>;
-def : RWSysReg<"TRCSEQEVR2", 0b10, 0b001, 0b0000, 0b0010, 0b100>;
-def : RWSysReg<"TRCSEQRSTEVR", 0b10, 0b001, 0b0000, 0b0110, 0b100>;
-def : RWSysReg<"TRCSEQSTR", 0b10, 0b001, 0b0000, 0b0111, 0b100>;
-def : RWSysReg<"TRCEXTINSELR", 0b10, 0b001, 0b0000, 0b1000, 0b100>;
-def : RWSysReg<"TRCCNTRLDVR0", 0b10, 0b001, 0b0000, 0b0000, 0b101>;
-def : RWSysReg<"TRCCNTRLDVR1", 0b10, 0b001, 0b0000, 0b0001, 0b101>;
-def : RWSysReg<"TRCCNTRLDVR2", 0b10, 0b001, 0b0000, 0b0010, 0b101>;
-def : RWSysReg<"TRCCNTRLDVR3", 0b10, 0b001, 0b0000, 0b0011, 0b101>;
-def : RWSysReg<"TRCCNTCTLR0", 0b10, 0b001, 0b0000, 0b0100, 0b101>;
-def : RWSysReg<"TRCCNTCTLR1", 0b10, 0b001, 0b0000, 0b0101, 0b101>;
-def : RWSysReg<"TRCCNTCTLR2", 0b10, 0b001, 0b0000, 0b0110, 0b101>;
-def : RWSysReg<"TRCCNTCTLR3", 0b10, 0b001, 0b0000, 0b0111, 0b101>;
-def : RWSysReg<"TRCCNTVR0", 0b10, 0b001, 0b0000, 0b1000, 0b101>;
-def : RWSysReg<"TRCCNTVR1", 0b10, 0b001, 0b0000, 0b1001, 0b101>;
-def : RWSysReg<"TRCCNTVR2", 0b10, 0b001, 0b0000, 0b1010, 0b101>;
-def : RWSysReg<"TRCCNTVR3", 0b10, 0b001, 0b0000, 0b1011, 0b101>;
-def : RWSysReg<"TRCIMSPEC0", 0b10, 0b001, 0b0000, 0b0000, 0b111>;
-def : RWSysReg<"TRCIMSPEC1", 0b10, 0b001, 0b0000, 0b0001, 0b111>;
-def : RWSysReg<"TRCIMSPEC2", 0b10, 0b001, 0b0000, 0b0010, 0b111>;
-def : RWSysReg<"TRCIMSPEC3", 0b10, 0b001, 0b0000, 0b0011, 0b111>;
-def : RWSysReg<"TRCIMSPEC4", 0b10, 0b001, 0b0000, 0b0100, 0b111>;
-def : RWSysReg<"TRCIMSPEC5", 0b10, 0b001, 0b0000, 0b0101, 0b111>;
-def : RWSysReg<"TRCIMSPEC6", 0b10, 0b001, 0b0000, 0b0110, 0b111>;
-def : RWSysReg<"TRCIMSPEC7", 0b10, 0b001, 0b0000, 0b0111, 0b111>;
-def : RWSysReg<"TRCRSCTLR2", 0b10, 0b001, 0b0001, 0b0010, 0b000>;
-def : RWSysReg<"TRCRSCTLR3", 0b10, 0b001, 0b0001, 0b0011, 0b000>;
-def : RWSysReg<"TRCRSCTLR4", 0b10, 0b001, 0b0001, 0b0100, 0b000>;
-def : RWSysReg<"TRCRSCTLR5", 0b10, 0b001, 0b0001, 0b0101, 0b000>;
-def : RWSysReg<"TRCRSCTLR6", 0b10, 0b001, 0b0001, 0b0110, 0b000>;
-def : RWSysReg<"TRCRSCTLR7", 0b10, 0b001, 0b0001, 0b0111, 0b000>;
-def : RWSysReg<"TRCRSCTLR8", 0b10, 0b001, 0b0001, 0b1000, 0b000>;
-def : RWSysReg<"TRCRSCTLR9", 0b10, 0b001, 0b0001, 0b1001, 0b000>;
-def : RWSysReg<"TRCRSCTLR10", 0b10, 0b001, 0b0001, 0b1010, 0b000>;
-def : RWSysReg<"TRCRSCTLR11", 0b10, 0b001, 0b0001, 0b1011, 0b000>;
-def : RWSysReg<"TRCRSCTLR12", 0b10, 0b001, 0b0001, 0b1100, 0b000>;
-def : RWSysReg<"TRCRSCTLR13", 0b10, 0b001, 0b0001, 0b1101, 0b000>;
-def : RWSysReg<"TRCRSCTLR14", 0b10, 0b001, 0b0001, 0b1110, 0b000>;
-def : RWSysReg<"TRCRSCTLR15", 0b10, 0b001, 0b0001, 0b1111, 0b000>;
-def : RWSysReg<"TRCRSCTLR16", 0b10, 0b001, 0b0001, 0b0000, 0b001>;
-def : RWSysReg<"TRCRSCTLR17", 0b10, 0b001, 0b0001, 0b0001, 0b001>;
-def : RWSysReg<"TRCRSCTLR18", 0b10, 0b001, 0b0001, 0b0010, 0b001>;
-def : RWSysReg<"TRCRSCTLR19", 0b10, 0b001, 0b0001, 0b0011, 0b001>;
-def : RWSysReg<"TRCRSCTLR20", 0b10, 0b001, 0b0001, 0b0100, 0b001>;
-def : RWSysReg<"TRCRSCTLR21", 0b10, 0b001, 0b0001, 0b0101, 0b001>;
-def : RWSysReg<"TRCRSCTLR22", 0b10, 0b001, 0b0001, 0b0110, 0b001>;
-def : RWSysReg<"TRCRSCTLR23", 0b10, 0b001, 0b0001, 0b0111, 0b001>;
-def : RWSysReg<"TRCRSCTLR24", 0b10, 0b001, 0b0001, 0b1000, 0b001>;
-def : RWSysReg<"TRCRSCTLR25", 0b10, 0b001, 0b0001, 0b1001, 0b001>;
-def : RWSysReg<"TRCRSCTLR26", 0b10, 0b001, 0b0001, 0b1010, 0b001>;
-def : RWSysReg<"TRCRSCTLR27", 0b10, 0b001, 0b0001, 0b1011, 0b001>;
-def : RWSysReg<"TRCRSCTLR28", 0b10, 0b001, 0b0001, 0b1100, 0b001>;
-def : RWSysReg<"TRCRSCTLR29", 0b10, 0b001, 0b0001, 0b1101, 0b001>;
-def : RWSysReg<"TRCRSCTLR30", 0b10, 0b001, 0b0001, 0b1110, 0b001>;
-def : RWSysReg<"TRCRSCTLR31", 0b10, 0b001, 0b0001, 0b1111, 0b001>;
-def : RWSysReg<"TRCSSCCR0", 0b10, 0b001, 0b0001, 0b0000, 0b010>;
-def : RWSysReg<"TRCSSCCR1", 0b10, 0b001, 0b0001, 0b0001, 0b010>;
-def : RWSysReg<"TRCSSCCR2", 0b10, 0b001, 0b0001, 0b0010, 0b010>;
-def : RWSysReg<"TRCSSCCR3", 0b10, 0b001, 0b0001, 0b0011, 0b010>;
-def : RWSysReg<"TRCSSCCR4", 0b10, 0b001, 0b0001, 0b0100, 0b010>;
-def : RWSysReg<"TRCSSCCR5", 0b10, 0b001, 0b0001, 0b0101, 0b010>;
-def : RWSysReg<"TRCSSCCR6", 0b10, 0b001, 0b0001, 0b0110, 0b010>;
-def : RWSysReg<"TRCSSCCR7", 0b10, 0b001, 0b0001, 0b0111, 0b010>;
-def : RWSysReg<"TRCSSCSR0", 0b10, 0b001, 0b0001, 0b1000, 0b010>;
-def : RWSysReg<"TRCSSCSR1", 0b10, 0b001, 0b0001, 0b1001, 0b010>;
-def : RWSysReg<"TRCSSCSR2", 0b10, 0b001, 0b0001, 0b1010, 0b010>;
-def : RWSysReg<"TRCSSCSR3", 0b10, 0b001, 0b0001, 0b1011, 0b010>;
-def : RWSysReg<"TRCSSCSR4", 0b10, 0b001, 0b0001, 0b1100, 0b010>;
-def : RWSysReg<"TRCSSCSR5", 0b10, 0b001, 0b0001, 0b1101, 0b010>;
-def : RWSysReg<"TRCSSCSR6", 0b10, 0b001, 0b0001, 0b1110, 0b010>;
-def : RWSysReg<"TRCSSCSR7", 0b10, 0b001, 0b0001, 0b1111, 0b010>;
-def : RWSysReg<"TRCSSPCICR0", 0b10, 0b001, 0b0001, 0b0000, 0b011>;
-def : RWSysReg<"TRCSSPCICR1", 0b10, 0b001, 0b0001, 0b0001, 0b011>;
-def : RWSysReg<"TRCSSPCICR2", 0b10, 0b001, 0b0001, 0b0010, 0b011>;
-def : RWSysReg<"TRCSSPCICR3", 0b10, 0b001, 0b0001, 0b0011, 0b011>;
-def : RWSysReg<"TRCSSPCICR4", 0b10, 0b001, 0b0001, 0b0100, 0b011>;
-def : RWSysReg<"TRCSSPCICR5", 0b10, 0b001, 0b0001, 0b0101, 0b011>;
-def : RWSysReg<"TRCSSPCICR6", 0b10, 0b001, 0b0001, 0b0110, 0b011>;
-def : RWSysReg<"TRCSSPCICR7", 0b10, 0b001, 0b0001, 0b0111, 0b011>;
-def : RWSysReg<"TRCPDCR", 0b10, 0b001, 0b0001, 0b0100, 0b100>;
-def : RWSysReg<"TRCACVR0", 0b10, 0b001, 0b0010, 0b0000, 0b000>;
-def : RWSysReg<"TRCACVR1", 0b10, 0b001, 0b0010, 0b0010, 0b000>;
-def : RWSysReg<"TRCACVR2", 0b10, 0b001, 0b0010, 0b0100, 0b000>;
-def : RWSysReg<"TRCACVR3", 0b10, 0b001, 0b0010, 0b0110, 0b000>;
-def : RWSysReg<"TRCACVR4", 0b10, 0b001, 0b0010, 0b1000, 0b000>;
-def : RWSysReg<"TRCACVR5", 0b10, 0b001, 0b0010, 0b1010, 0b000>;
-def : RWSysReg<"TRCACVR6", 0b10, 0b001, 0b0010, 0b1100, 0b000>;
-def : RWSysReg<"TRCACVR7", 0b10, 0b001, 0b0010, 0b1110, 0b000>;
-def : RWSysReg<"TRCACVR8", 0b10, 0b001, 0b0010, 0b0000, 0b001>;
-def : RWSysReg<"TRCACVR9", 0b10, 0b001, 0b0010, 0b0010, 0b001>;
-def : RWSysReg<"TRCACVR10", 0b10, 0b001, 0b0010, 0b0100, 0b001>;
-def : RWSysReg<"TRCACVR11", 0b10, 0b001, 0b0010, 0b0110, 0b001>;
-def : RWSysReg<"TRCACVR12", 0b10, 0b001, 0b0010, 0b1000, 0b001>;
-def : RWSysReg<"TRCACVR13", 0b10, 0b001, 0b0010, 0b1010, 0b001>;
-def : RWSysReg<"TRCACVR14", 0b10, 0b001, 0b0010, 0b1100, 0b001>;
-def : RWSysReg<"TRCACVR15", 0b10, 0b001, 0b0010, 0b1110, 0b001>;
-def : RWSysReg<"TRCACATR0", 0b10, 0b001, 0b0010, 0b0000, 0b010>;
-def : RWSysReg<"TRCACATR1", 0b10, 0b001, 0b0010, 0b0010, 0b010>;
-def : RWSysReg<"TRCACATR2", 0b10, 0b001, 0b0010, 0b0100, 0b010>;
-def : RWSysReg<"TRCACATR3", 0b10, 0b001, 0b0010, 0b0110, 0b010>;
-def : RWSysReg<"TRCACATR4", 0b10, 0b001, 0b0010, 0b1000, 0b010>;
-def : RWSysReg<"TRCACATR5", 0b10, 0b001, 0b0010, 0b1010, 0b010>;
-def : RWSysReg<"TRCACATR6", 0b10, 0b001, 0b0010, 0b1100, 0b010>;
-def : RWSysReg<"TRCACATR7", 0b10, 0b001, 0b0010, 0b1110, 0b010>;
-def : RWSysReg<"TRCACATR8", 0b10, 0b001, 0b0010, 0b0000, 0b011>;
-def : RWSysReg<"TRCACATR9", 0b10, 0b001, 0b0010, 0b0010, 0b011>;
-def : RWSysReg<"TRCACATR10", 0b10, 0b001, 0b0010, 0b0100, 0b011>;
-def : RWSysReg<"TRCACATR11", 0b10, 0b001, 0b0010, 0b0110, 0b011>;
-def : RWSysReg<"TRCACATR12", 0b10, 0b001, 0b0010, 0b1000, 0b011>;
-def : RWSysReg<"TRCACATR13", 0b10, 0b001, 0b0010, 0b1010, 0b011>;
-def : RWSysReg<"TRCACATR14", 0b10, 0b001, 0b0010, 0b1100, 0b011>;
-def : RWSysReg<"TRCACATR15", 0b10, 0b001, 0b0010, 0b1110, 0b011>;
-def : RWSysReg<"TRCDVCVR0", 0b10, 0b001, 0b0010, 0b0000, 0b100>;
-def : RWSysReg<"TRCDVCVR1", 0b10, 0b001, 0b0010, 0b0100, 0b100>;
-def : RWSysReg<"TRCDVCVR2", 0b10, 0b001, 0b0010, 0b1000, 0b100>;
-def : RWSysReg<"TRCDVCVR3", 0b10, 0b001, 0b0010, 0b1100, 0b100>;
-def : RWSysReg<"TRCDVCVR4", 0b10, 0b001, 0b0010, 0b0000, 0b101>;
-def : RWSysReg<"TRCDVCVR5", 0b10, 0b001, 0b0010, 0b0100, 0b101>;
-def : RWSysReg<"TRCDVCVR6", 0b10, 0b001, 0b0010, 0b1000, 0b101>;
-def : RWSysReg<"TRCDVCVR7", 0b10, 0b001, 0b0010, 0b1100, 0b101>;
-def : RWSysReg<"TRCDVCMR0", 0b10, 0b001, 0b0010, 0b0000, 0b110>;
-def : RWSysReg<"TRCDVCMR1", 0b10, 0b001, 0b0010, 0b0100, 0b110>;
-def : RWSysReg<"TRCDVCMR2", 0b10, 0b001, 0b0010, 0b1000, 0b110>;
-def : RWSysReg<"TRCDVCMR3", 0b10, 0b001, 0b0010, 0b1100, 0b110>;
-def : RWSysReg<"TRCDVCMR4", 0b10, 0b001, 0b0010, 0b0000, 0b111>;
-def : RWSysReg<"TRCDVCMR5", 0b10, 0b001, 0b0010, 0b0100, 0b111>;
-def : RWSysReg<"TRCDVCMR6", 0b10, 0b001, 0b0010, 0b1000, 0b111>;
-def : RWSysReg<"TRCDVCMR7", 0b10, 0b001, 0b0010, 0b1100, 0b111>;
-def : RWSysReg<"TRCCIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b000>;
-def : RWSysReg<"TRCCIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b000>;
-def : RWSysReg<"TRCCIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b000>;
-def : RWSysReg<"TRCCIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b000>;
-def : RWSysReg<"TRCCIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b000>;
-def : RWSysReg<"TRCCIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b000>;
-def : RWSysReg<"TRCCIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b000>;
-def : RWSysReg<"TRCCIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b000>;
-def : RWSysReg<"TRCVMIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b001>;
-def : RWSysReg<"TRCVMIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b001>;
-def : RWSysReg<"TRCVMIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b001>;
-def : RWSysReg<"TRCVMIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b001>;
-def : RWSysReg<"TRCVMIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b001>;
-def : RWSysReg<"TRCVMIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b001>;
-def : RWSysReg<"TRCVMIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b001>;
-def : RWSysReg<"TRCVMIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b001>;
-def : RWSysReg<"TRCCIDCCTLR0", 0b10, 0b001, 0b0011, 0b0000, 0b010>;
-def : RWSysReg<"TRCCIDCCTLR1", 0b10, 0b001, 0b0011, 0b0001, 0b010>;
-def : RWSysReg<"TRCVMIDCCTLR0", 0b10, 0b001, 0b0011, 0b0010, 0b010>;
-def : RWSysReg<"TRCVMIDCCTLR1", 0b10, 0b001, 0b0011, 0b0011, 0b010>;
-def : RWSysReg<"TRCITCTRL", 0b10, 0b001, 0b0111, 0b0000, 0b100>;
-def : RWSysReg<"TRCCLAIMSET", 0b10, 0b001, 0b0111, 0b1000, 0b110>;
-def : RWSysReg<"TRCCLAIMCLR", 0b10, 0b001, 0b0111, 0b1001, 0b110>;
+def : RWSysReg<"TRCPRGCTLR", 0b0, 0b001, 0b0000, 0b0001, 0b000>;
+def : RWSysReg<"TRCPROCSELR", 0b0, 0b001, 0b0000, 0b0010, 0b000>;
+def : RWSysReg<"TRCCONFIGR", 0b0, 0b001, 0b0000, 0b0100, 0b000>;
+def : RWSysReg<"TRCAUXCTLR", 0b0, 0b001, 0b0000, 0b0110, 0b000>;
+def : RWSysReg<"TRCEVENTCTL0R", 0b0, 0b001, 0b0000, 0b1000, 0b000>;
+def : RWSysReg<"TRCEVENTCTL1R", 0b0, 0b001, 0b0000, 0b1001, 0b000>;
+def : RWSysReg<"TRCSTALLCTLR", 0b0, 0b001, 0b0000, 0b1011, 0b000>;
+def : RWSysReg<"TRCTSCTLR", 0b0, 0b001, 0b0000, 0b1100, 0b000>;
+def : RWSysReg<"TRCSYNCPR", 0b0, 0b001, 0b0000, 0b1101, 0b000>;
+def : RWSysReg<"TRCCCCTLR", 0b0, 0b001, 0b0000, 0b1110, 0b000>;
+def : RWSysReg<"TRCBBCTLR", 0b0, 0b001, 0b0000, 0b1111, 0b000>;
+def : RWSysReg<"TRCTRACEIDR", 0b0, 0b001, 0b0000, 0b0000, 0b001>;
+def : RWSysReg<"TRCQCTLR", 0b0, 0b001, 0b0000, 0b0001, 0b001>;
+def : RWSysReg<"TRCVICTLR", 0b0, 0b001, 0b0000, 0b0000, 0b010>;
+def : RWSysReg<"TRCVIIECTLR", 0b0, 0b001, 0b0000, 0b0001, 0b010>;
+def : RWSysReg<"TRCVISSCTLR", 0b0, 0b001, 0b0000, 0b0010, 0b010>;
+def : RWSysReg<"TRCVIPCSSCTLR", 0b0, 0b001, 0b0000, 0b0011, 0b010>;
+def : RWSysReg<"TRCVDCTLR", 0b0, 0b001, 0b0000, 0b1000, 0b010>;
+def : RWSysReg<"TRCVDSACCTLR", 0b0, 0b001, 0b0000, 0b1001, 0b010>;
+def : RWSysReg<"TRCVDARCCTLR", 0b0, 0b001, 0b0000, 0b1010, 0b010>;
+def : RWSysReg<"TRCSEQEVR0", 0b0, 0b001, 0b0000, 0b0000, 0b100>;
+def : RWSysReg<"TRCSEQEVR1", 0b0, 0b001, 0b0000, 0b0001, 0b100>;
+def : RWSysReg<"TRCSEQEVR2", 0b0, 0b001, 0b0000, 0b0010, 0b100>;
+def : RWSysReg<"TRCSEQRSTEVR", 0b0, 0b001, 0b0000, 0b0110, 0b100>;
+def : RWSysReg<"TRCSEQSTR", 0b0, 0b001, 0b0000, 0b0111, 0b100>;
+def : RWSysReg<"TRCEXTINSELR", 0b0, 0b001, 0b0000, 0b1000, 0b100>;
+def : RWSysReg<"TRCCNTRLDVR0", 0b0, 0b001, 0b0000, 0b0000, 0b101>;
+def : RWSysReg<"TRCCNTRLDVR1", 0b0, 0b001, 0b0000, 0b0001, 0b101>;
+def : RWSysReg<"TRCCNTRLDVR2", 0b0, 0b001, 0b0000, 0b0010, 0b101>;
+def : RWSysReg<"TRCCNTRLDVR3", 0b0, 0b001, 0b0000, 0b0011, 0b101>;
+def : RWSysReg<"TRCCNTCTLR0", 0b0, 0b001, 0b0000, 0b0100, 0b101>;
+def : RWSysReg<"TRCCNTCTLR1", 0b0, 0b001, 0b0000, 0b0101, 0b101>;
+def : RWSysReg<"TRCCNTCTLR2", 0b0, 0b001, 0b0000, 0b0110, 0b101>;
+def : RWSysReg<"TRCCNTCTLR3", 0b0, 0b001, 0b0000, 0b0111, 0b101>;
+def : RWSysReg<"TRCCNTVR0", 0b0, 0b001, 0b0000, 0b1000, 0b101>;
+def : RWSysReg<"TRCCNTVR1", 0b0, 0b001, 0b0000, 0b1001, 0b101>;
+def : RWSysReg<"TRCCNTVR2", 0b0, 0b001, 0b0000, 0b1010, 0b101>;
+def : RWSysReg<"TRCCNTVR3", 0b0, 0b001, 0b0000, 0b1011, 0b101>;
+def : RWSysReg<"TRCIMSPEC0", 0b0, 0b001, 0b0000, 0b0000, 0b111>;
+def : RWSysReg<"TRCIMSPEC1", 0b0, 0b001, 0b0000, 0b0001, 0b111>;
+def : RWSysReg<"TRCIMSPEC2", 0b0, 0b001, 0b0000, 0b0010, 0b111>;
+def : RWSysReg<"TRCIMSPEC3", 0b0, 0b001, 0b0000, 0b0011, 0b111>;
+def : RWSysReg<"TRCIMSPEC4", 0b0, 0b001, 0b0000, 0b0100, 0b111>;
+def : RWSysReg<"TRCIMSPEC5", 0b0, 0b001, 0b0000, 0b0101, 0b111>;
+def : RWSysReg<"TRCIMSPEC6", 0b0, 0b001, 0b0000, 0b0110, 0b111>;
+def : RWSysReg<"TRCIMSPEC7", 0b0, 0b001, 0b0000, 0b0111, 0b111>;
+def : RWSysReg<"TRCRSCTLR2", 0b0, 0b001, 0b0001, 0b0010, 0b000>;
+def : RWSysReg<"TRCRSCTLR3", 0b0, 0b001, 0b0001, 0b0011, 0b000>;
+def : RWSysReg<"TRCRSCTLR4", 0b0, 0b001, 0b0001, 0b0100, 0b000>;
+def : RWSysReg<"TRCRSCTLR5", 0b0, 0b001, 0b0001, 0b0101, 0b000>;
+def : RWSysReg<"TRCRSCTLR6", 0b0, 0b001, 0b0001, 0b0110, 0b000>;
+def : RWSysReg<"TRCRSCTLR7", 0b0, 0b001, 0b0001, 0b0111, 0b000>;
+def : RWSysReg<"TRCRSCTLR8", 0b0, 0b001, 0b0001, 0b1000, 0b000>;
+def : RWSysReg<"TRCRSCTLR9", 0b0, 0b001, 0b0001, 0b1001, 0b000>;
+def : RWSysReg<"TRCRSCTLR10", 0b0, 0b001, 0b0001, 0b1010, 0b000>;
+def : RWSysReg<"TRCRSCTLR11", 0b0, 0b001, 0b0001, 0b1011, 0b000>;
+def : RWSysReg<"TRCRSCTLR12", 0b0, 0b001, 0b0001, 0b1100, 0b000>;
+def : RWSysReg<"TRCRSCTLR13", 0b0, 0b001, 0b0001, 0b1101, 0b000>;
+def : RWSysReg<"TRCRSCTLR14", 0b0, 0b001, 0b0001, 0b1110, 0b000>;
+def : RWSysReg<"TRCRSCTLR15", 0b0, 0b001, 0b0001, 0b1111, 0b000>;
+def : RWSysReg<"TRCRSCTLR16", 0b0, 0b001, 0b0001, 0b0000, 0b001>;
+def : RWSysReg<"TRCRSCTLR17", 0b0, 0b001, 0b0001, 0b0001, 0b001>;
+def : RWSysReg<"TRCRSCTLR18", 0b0, 0b001, 0b0001, 0b0010, 0b001>;
+def : RWSysReg<"TRCRSCTLR19", 0b0, 0b001, 0b0001, 0b0011, 0b001>;
+def : RWSysReg<"TRCRSCTLR20", 0b0, 0b001, 0b0001, 0b0100, 0b001>;
+def : RWSysReg<"TRCRSCTLR21", 0b0, 0b001, 0b0001, 0b0101, 0b001>;
+def : RWSysReg<"TRCRSCTLR22", 0b0, 0b001, 0b0001, 0b0110, 0b001>;
+def : RWSysReg<"TRCRSCTLR23", 0b0, 0b001, 0b0001, 0b0111, 0b001>;
+def : RWSysReg<"TRCRSCTLR24", 0b0, 0b001, 0b0001, 0b1000, 0b001>;
+def : RWSysReg<"TRCRSCTLR25", 0b0, 0b001, 0b0001, 0b1001, 0b001>;
+def : RWSysReg<"TRCRSCTLR26", 0b0, 0b001, 0b0001, 0b1010, 0b001>;
+def : RWSysReg<"TRCRSCTLR27", 0b0, 0b001, 0b0001, 0b1011, 0b001>;
+def : RWSysReg<"TRCRSCTLR28", 0b0, 0b001, 0b0001, 0b1100, 0b001>;
+def : RWSysReg<"TRCRSCTLR29", 0b0, 0b001, 0b0001, 0b1101, 0b001>;
+def : RWSysReg<"TRCRSCTLR30", 0b0, 0b001, 0b0001, 0b1110, 0b001>;
+def : RWSysReg<"TRCRSCTLR31", 0b0, 0b001, 0b0001, 0b1111, 0b001>;
+def : RWSysReg<"TRCSSCCR0", 0b0, 0b001, 0b0001, 0b0000, 0b010>;
+def : RWSysReg<"TRCSSCCR1", 0b0, 0b001, 0b0001, 0b0001, 0b010>;
+def : RWSysReg<"TRCSSCCR2", 0b0, 0b001, 0b0001, 0b0010, 0b010>;
+def : RWSysReg<"TRCSSCCR3", 0b0, 0b001, 0b0001, 0b0011, 0b010>;
+def : RWSysReg<"TRCSSCCR4", 0b0, 0b001, 0b0001, 0b0100, 0b010>;
+def : RWSysReg<"TRCSSCCR5", 0b0, 0b001, 0b0001, 0b0101, 0b010>;
+def : RWSysReg<"TRCSSCCR6", 0b0, 0b001, 0b0001, 0b0110, 0b010>;
+def : RWSysReg<"TRCSSCCR7", 0b0, 0b001, 0b0001, 0b0111, 0b010>;
+def : RWSysReg<"TRCSSCSR0", 0b0, 0b001, 0b0001, 0b1000, 0b010>;
+def : RWSysReg<"TRCSSCSR1", 0b0, 0b001, 0b0001, 0b1001, 0b010>;
+def : RWSysReg<"TRCSSCSR2", 0b0, 0b001, 0b0001, 0b1010, 0b010>;
+def : RWSysReg<"TRCSSCSR3", 0b0, 0b001, 0b0001, 0b1011, 0b010>;
+def : RWSysReg<"TRCSSCSR4", 0b0, 0b001, 0b0001, 0b1100, 0b010>;
+def : RWSysReg<"TRCSSCSR5", 0b0, 0b001, 0b0001, 0b1101, 0b010>;
+def : RWSysReg<"TRCSSCSR6", 0b0, 0b001, 0b0001, 0b1110, 0b010>;
+def : RWSysReg<"TRCSSCSR7", 0b0, 0b001, 0b0001, 0b1111, 0b010>;
+def : RWSysReg<"TRCSSPCICR0", 0b0, 0b001, 0b0001, 0b0000, 0b011>;
+def : RWSysReg<"TRCSSPCICR1", 0b0, 0b001, 0b0001, 0b0001, 0b011>;
+def : RWSysReg<"TRCSSPCICR2", 0b0, 0b001, 0b0001, 0b0010, 0b011>;
+def : RWSysReg<"TRCSSPCICR3", 0b0, 0b001, 0b0001, 0b0011, 0b011>;
+def : RWSysReg<"TRCSSPCICR4", 0b0, 0b001, 0b0001, 0b0100, 0b011>;
+def : RWSysReg<"TRCSSPCICR5", 0b0, 0b001, 0b0001, 0b0101, 0b011>;
+def : RWSysReg<"TRCSSPCICR6", 0b0, 0b001, 0b0001, 0b0110, 0b011>;
+def : RWSysReg<"TRCSSPCICR7", 0b0, 0b001, 0b0001, 0b0111, 0b011>;
+def : RWSysReg<"TRCPDCR", 0b0, 0b001, 0b0001, 0b0100, 0b100>;
+def : RWSysReg<"TRCACVR0", 0b0, 0b001, 0b0010, 0b0000, 0b000>;
+def : RWSysReg<"TRCACVR1", 0b0, 0b001, 0b0010, 0b0010, 0b000>;
+def : RWSysReg<"TRCACVR2", 0b0, 0b001, 0b0010, 0b0100, 0b000>;
+def : RWSysReg<"TRCACVR3", 0b0, 0b001, 0b0010, 0b0110, 0b000>;
+def : RWSysReg<"TRCACVR4", 0b0, 0b001, 0b0010, 0b1000, 0b000>;
+def : RWSysReg<"TRCACVR5", 0b0, 0b001, 0b0010, 0b1010, 0b000>;
+def : RWSysReg<"TRCACVR6", 0b0, 0b001, 0b0010, 0b1100, 0b000>;
+def : RWSysReg<"TRCACVR7", 0b0, 0b001, 0b0010, 0b1110, 0b000>;
+def : RWSysReg<"TRCACVR8", 0b0, 0b001, 0b0010, 0b0000, 0b001>;
+def : RWSysReg<"TRCACVR9", 0b0, 0b001, 0b0010, 0b0010, 0b001>;
+def : RWSysReg<"TRCACVR10", 0b0, 0b001, 0b0010, 0b0100, 0b001>;
+def : RWSysReg<"TRCACVR11", 0b0, 0b001, 0b0010, 0b0110, 0b001>;
+def : RWSysReg<"TRCACVR12", 0b0, 0b001, 0b0010, 0b1000, 0b001>;
+def : RWSysReg<"TRCACVR13", 0b0, 0b001, 0b0010, 0b1010, 0b001>;
+def : RWSysReg<"TRCACVR14", 0b0, 0b001, 0b0010, 0b1100, 0b001>;
+def : RWSysReg<"TRCACVR15", 0b0, 0b001, 0b0010, 0b1110, 0b001>;
+def : RWSysReg<"TRCACATR0", 0b0, 0b001, 0b0010, 0b0000, 0b010>;
+def : RWSysReg<"TRCACATR1", 0b0, 0b001, 0b0010, 0b0010, 0b010>;
+def : RWSysReg<"TRCACATR2", 0b0, 0b001, 0b0010, 0b0100, 0b010>;
+def : RWSysReg<"TRCACATR3", 0b0, 0b001, 0b0010, 0b0110, 0b010>;
+def : RWSysReg<"TRCACATR4", 0b0, 0b001, 0b0010, 0b1000, 0b010>;
+def : RWSysReg<"TRCACATR5", 0b0, 0b001, 0b0010, 0b1010, 0b010>;
+def : RWSysReg<"TRCACATR6", 0b0, 0b001, 0b0010, 0b1100, 0b010>;
+def : RWSysReg<"TRCACATR7", 0b0, 0b001, 0b0010, 0b1110, 0b010>;
+def : RWSysReg<"TRCACATR8", 0b0, 0b001, 0b0010, 0b0000, 0b011>;
+def : RWSysReg<"TRCACATR9", 0b0, 0b001, 0b0010, 0b0010, 0b011>;
+def : RWSysReg<"TRCACATR10", 0b0, 0b001, 0b0010, 0b0100, 0b011>;
+def : RWSysReg<"TRCACATR11", 0b0, 0b001, 0b0010, 0b0110, 0b011>;
+def : RWSysReg<"TRCACATR12", 0b0, 0b001, 0b0010, 0b1000, 0b011>;
+def : RWSysReg<"TRCACATR13", 0b0, 0b001, 0b0010, 0b1010, 0b011>;
+def : RWSysReg<"TRCACATR14", 0b0, 0b001, 0b0010, 0b1100, 0b011>;
+def : RWSysReg<"TRCACATR15", 0b0, 0b001, 0b0010, 0b1110, 0b011>;
+def : RWSysReg<"TRCDVCVR0", 0b0, 0b001, 0b0010, 0b0000, 0b100>;
+def : RWSysReg<"TRCDVCVR1", 0b0, 0b001, 0b0010, 0b0100, 0b100>;
+def : RWSysReg<"TRCDVCVR2", 0b0, 0b001, 0b0010, 0b1000, 0b100>;
+def : RWSysReg<"TRCDVCVR3", 0b0, 0b001, 0b0010, 0b1100, 0b100>;
+def : RWSysReg<"TRCDVCVR4", 0b0, 0b001, 0b0010, 0b0000, 0b101>;
+def : RWSysReg<"TRCDVCVR5", 0b0, 0b001, 0b0010, 0b0100, 0b101>;
+def : RWSysReg<"TRCDVCVR6", 0b0, 0b001, 0b0010, 0b1000, 0b101>;
+def : RWSysReg<"TRCDVCVR7", 0b0, 0b001, 0b0010, 0b1100, 0b101>;
+def : RWSysReg<"TRCDVCMR0", 0b0, 0b001, 0b0010, 0b0000, 0b110>;
+def : RWSysReg<"TRCDVCMR1", 0b0, 0b001, 0b0010, 0b0100, 0b110>;
+def : RWSysReg<"TRCDVCMR2", 0b0, 0b001, 0b0010, 0b1000, 0b110>;
+def : RWSysReg<"TRCDVCMR3", 0b0, 0b001, 0b0010, 0b1100, 0b110>;
+def : RWSysReg<"TRCDVCMR4", 0b0, 0b001, 0b0010, 0b0000, 0b111>;
+def : RWSysReg<"TRCDVCMR5", 0b0, 0b001, 0b0010, 0b0100, 0b111>;
+def : RWSysReg<"TRCDVCMR6", 0b0, 0b001, 0b0010, 0b1000, 0b111>;
+def : RWSysReg<"TRCDVCMR7", 0b0, 0b001, 0b0010, 0b1100, 0b111>;
+def : RWSysReg<"TRCCIDCVR0", 0b0, 0b001, 0b0011, 0b0000, 0b000>;
+def : RWSysReg<"TRCCIDCVR1", 0b0, 0b001, 0b0011, 0b0010, 0b000>;
+def : RWSysReg<"TRCCIDCVR2", 0b0, 0b001, 0b0011, 0b0100, 0b000>;
+def : RWSysReg<"TRCCIDCVR3", 0b0, 0b001, 0b0011, 0b0110, 0b000>;
+def : RWSysReg<"TRCCIDCVR4", 0b0, 0b001, 0b0011, 0b1000, 0b000>;
+def : RWSysReg<"TRCCIDCVR5", 0b0, 0b001, 0b0011, 0b1010, 0b000>;
+def : RWSysReg<"TRCCIDCVR6", 0b0, 0b001, 0b0011, 0b1100, 0b000>;
+def : RWSysReg<"TRCCIDCVR7", 0b0, 0b001, 0b0011, 0b1110, 0b000>;
+def : RWSysReg<"TRCVMIDCVR0", 0b0, 0b001, 0b0011, 0b0000, 0b001>;
+def : RWSysReg<"TRCVMIDCVR1", 0b0, 0b001, 0b0011, 0b0010, 0b001>;
+def : RWSysReg<"TRCVMIDCVR2", 0b0, 0b001, 0b0011, 0b0100, 0b001>;
+def : RWSysReg<"TRCVMIDCVR3", 0b0, 0b001, 0b0011, 0b0110, 0b001>;
+def : RWSysReg<"TRCVMIDCVR4", 0b0, 0b001, 0b0011, 0b1000, 0b001>;
+def : RWSysReg<"TRCVMIDCVR5", 0b0, 0b001, 0b0011, 0b1010, 0b001>;
+def : RWSysReg<"TRCVMIDCVR6", 0b0, 0b001, 0b0011, 0b1100, 0b001>;
+def : RWSysReg<"TRCVMIDCVR7", 0b0, 0b001, 0b0011, 0b1110, 0b001>;
+def : RWSysReg<"TRCCIDCCTLR0", 0b0, 0b001, 0b0011, 0b0000, 0b010>;
+def : RWSysReg<"TRCCIDCCTLR1", 0b0, 0b001, 0b0011, 0b0001, 0b010>;
+def : RWSysReg<"TRCVMIDCCTLR0", 0b0, 0b001, 0b0011, 0b0010, 0b010>;
+def : RWSysReg<"TRCVMIDCCTLR1", 0b0, 0b001, 0b0011, 0b0011, 0b010>;
+def : RWSysReg<"TRCITCTRL", 0b0, 0b001, 0b0111, 0b0000, 0b100>;
+def : RWSysReg<"TRCCLAIMSET", 0b0, 0b001, 0b0111, 0b1000, 0b110>;
+def : RWSysReg<"TRCCLAIMCLR", 0b0, 0b001, 0b0111, 0b1001, 0b110>;
// GICv3 registers
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"ICC_BPR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b011>;
-def : RWSysReg<"ICC_BPR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b011>;
-def : RWSysReg<"ICC_PMR_EL1", 0b11, 0b000, 0b0100, 0b0110, 0b000>;
-def : RWSysReg<"ICC_CTLR_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b100>;
-def : RWSysReg<"ICC_CTLR_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b100>;
-def : RWSysReg<"ICC_SRE_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b101>;
-def : RWSysReg<"ICC_SRE_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b101>;
-def : RWSysReg<"ICC_SRE_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b101>;
-def : RWSysReg<"ICC_IGRPEN0_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b110>;
-def : RWSysReg<"ICC_IGRPEN1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b111>;
-def : RWSysReg<"ICC_IGRPEN1_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b111>;
-def : RWSysReg<"ICC_AP0R0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b100>;
-def : RWSysReg<"ICC_AP0R1_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b101>;
-def : RWSysReg<"ICC_AP0R2_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b110>;
-def : RWSysReg<"ICC_AP0R3_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b111>;
-def : RWSysReg<"ICC_AP1R0_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b000>;
-def : RWSysReg<"ICC_AP1R1_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b001>;
-def : RWSysReg<"ICC_AP1R2_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b010>;
-def : RWSysReg<"ICC_AP1R3_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b011>;
-def : RWSysReg<"ICH_AP0R0_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b000>;
-def : RWSysReg<"ICH_AP0R1_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b001>;
-def : RWSysReg<"ICH_AP0R2_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b010>;
-def : RWSysReg<"ICH_AP0R3_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b011>;
-def : RWSysReg<"ICH_AP1R0_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b000>;
-def : RWSysReg<"ICH_AP1R1_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b001>;
-def : RWSysReg<"ICH_AP1R2_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b010>;
-def : RWSysReg<"ICH_AP1R3_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b011>;
-def : RWSysReg<"ICH_HCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b000>;
-def : ROSysReg<"ICH_MISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b010>;
-def : RWSysReg<"ICH_VMCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b111>;
-def : RWSysReg<"ICH_LR0_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b000>;
-def : RWSysReg<"ICH_LR1_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b001>;
-def : RWSysReg<"ICH_LR2_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b010>;
-def : RWSysReg<"ICH_LR3_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b011>;
-def : RWSysReg<"ICH_LR4_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b100>;
-def : RWSysReg<"ICH_LR5_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b101>;
-def : RWSysReg<"ICH_LR6_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b110>;
-def : RWSysReg<"ICH_LR7_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b111>;
-def : RWSysReg<"ICH_LR8_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b000>;
-def : RWSysReg<"ICH_LR9_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b001>;
-def : RWSysReg<"ICH_LR10_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b010>;
-def : RWSysReg<"ICH_LR11_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b011>;
-def : RWSysReg<"ICH_LR12_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b100>;
-def : RWSysReg<"ICH_LR13_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b101>;
-def : RWSysReg<"ICH_LR14_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b110>;
-def : RWSysReg<"ICH_LR15_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b111>;
+def : RWSysReg<"ICC_BPR1_EL1", 0b1, 0b000, 0b1100, 0b1100, 0b011>;
+def : RWSysReg<"ICC_BPR0_EL1", 0b1, 0b000, 0b1100, 0b1000, 0b011>;
+def : RWSysReg<"ICC_PMR_EL1", 0b1, 0b000, 0b0100, 0b0110, 0b000>;
+def : RWSysReg<"ICC_CTLR_EL1", 0b1, 0b000, 0b1100, 0b1100, 0b100>;
+def : RWSysReg<"ICC_CTLR_EL3", 0b1, 0b110, 0b1100, 0b1100, 0b100>;
+def : RWSysReg<"ICC_SRE_EL1", 0b1, 0b000, 0b1100, 0b1100, 0b101>;
+def : RWSysReg<"ICC_SRE_EL2", 0b1, 0b100, 0b1100, 0b1001, 0b101>;
+def : RWSysReg<"ICC_SRE_EL3", 0b1, 0b110, 0b1100, 0b1100, 0b101>;
+def : RWSysReg<"ICC_IGRPEN0_EL1", 0b1, 0b000, 0b1100, 0b1100, 0b110>;
+def : RWSysReg<"ICC_IGRPEN1_EL1", 0b1, 0b000, 0b1100, 0b1100, 0b111>;
+def : RWSysReg<"ICC_IGRPEN1_EL3", 0b1, 0b110, 0b1100, 0b1100, 0b111>;
+def : RWSysReg<"ICC_AP0R0_EL1", 0b1, 0b000, 0b1100, 0b1000, 0b100>;
+def : RWSysReg<"ICC_AP0R1_EL1", 0b1, 0b000, 0b1100, 0b1000, 0b101>;
+def : RWSysReg<"ICC_AP0R2_EL1", 0b1, 0b000, 0b1100, 0b1000, 0b110>;
+def : RWSysReg<"ICC_AP0R3_EL1", 0b1, 0b000, 0b1100, 0b1000, 0b111>;
+def : RWSysReg<"ICC_AP1R0_EL1", 0b1, 0b000, 0b1100, 0b1001, 0b000>;
+def : RWSysReg<"ICC_AP1R1_EL1", 0b1, 0b000, 0b1100, 0b1001, 0b001>;
+def : RWSysReg<"ICC_AP1R2_EL1", 0b1, 0b000, 0b1100, 0b1001, 0b010>;
+def : RWSysReg<"ICC_AP1R3_EL1", 0b1, 0b000, 0b1100, 0b1001, 0b011>;
+def : RWSysReg<"ICH_AP0R0_EL2", 0b1, 0b100, 0b1100, 0b1000, 0b000>;
+def : RWSysReg<"ICH_AP0R1_EL2", 0b1, 0b100, 0b1100, 0b1000, 0b001>;
+def : RWSysReg<"ICH_AP0R2_EL2", 0b1, 0b100, 0b1100, 0b1000, 0b010>;
+def : RWSysReg<"ICH_AP0R3_EL2", 0b1, 0b100, 0b1100, 0b1000, 0b011>;
+def : RWSysReg<"ICH_AP1R0_EL2", 0b1, 0b100, 0b1100, 0b1001, 0b000>;
+def : RWSysReg<"ICH_AP1R1_EL2", 0b1, 0b100, 0b1100, 0b1001, 0b001>;
+def : RWSysReg<"ICH_AP1R2_EL2", 0b1, 0b100, 0b1100, 0b1001, 0b010>;
+def : RWSysReg<"ICH_AP1R3_EL2", 0b1, 0b100, 0b1100, 0b1001, 0b011>;
+def : RWSysReg<"ICH_HCR_EL2", 0b1, 0b100, 0b1100, 0b1011, 0b000>;
+def : ROSysReg<"ICH_MISR_EL2", 0b1, 0b100, 0b1100, 0b1011, 0b010>;
+def : RWSysReg<"ICH_VMCR_EL2", 0b1, 0b100, 0b1100, 0b1011, 0b111>;
+def : RWSysReg<"ICH_LR0_EL2", 0b1, 0b100, 0b1100, 0b1100, 0b000>;
+def : RWSysReg<"ICH_LR1_EL2", 0b1, 0b100, 0b1100, 0b1100, 0b001>;
+def : RWSysReg<"ICH_LR2_EL2", 0b1, 0b100, 0b1100, 0b1100, 0b010>;
+def : RWSysReg<"ICH_LR3_EL2", 0b1, 0b100, 0b1100, 0b1100, 0b011>;
+def : RWSysReg<"ICH_LR4_EL2", 0b1, 0b100, 0b1100, 0b1100, 0b100>;
+def : RWSysReg<"ICH_LR5_EL2", 0b1, 0b100, 0b1100, 0b1100, 0b101>;
+def : RWSysReg<"ICH_LR6_EL2", 0b1, 0b100, 0b1100, 0b1100, 0b110>;
+def : RWSysReg<"ICH_LR7_EL2", 0b1, 0b100, 0b1100, 0b1100, 0b111>;
+def : RWSysReg<"ICH_LR8_EL2", 0b1, 0b100, 0b1100, 0b1101, 0b000>;
+def : RWSysReg<"ICH_LR9_EL2", 0b1, 0b100, 0b1100, 0b1101, 0b001>;
+def : RWSysReg<"ICH_LR10_EL2", 0b1, 0b100, 0b1100, 0b1101, 0b010>;
+def : RWSysReg<"ICH_LR11_EL2", 0b1, 0b100, 0b1100, 0b1101, 0b011>;
+def : RWSysReg<"ICH_LR12_EL2", 0b1, 0b100, 0b1100, 0b1101, 0b100>;
+def : RWSysReg<"ICH_LR13_EL2", 0b1, 0b100, 0b1100, 0b1101, 0b101>;
+def : RWSysReg<"ICH_LR14_EL2", 0b1, 0b100, 0b1100, 0b1101, 0b110>;
+def : RWSysReg<"ICH_LR15_EL2", 0b1, 0b100, 0b1100, 0b1101, 0b111>;
// v8r system registers
let Requires = [{ {AArch64::HasV8_0rOps} }] in {
//Virtualization System Control Register
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"VSCTLR_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000>;
+def : RWSysReg<"VSCTLR_EL2", 0b1, 0b100, 0b0010, 0b0000, 0b000>;
//MPU Type Register
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"MPUIR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b100>;
-def : RWSysReg<"MPUIR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b100>;
+def : RWSysReg<"MPUIR_EL1", 0b1, 0b000, 0b0000, 0b0000, 0b100>;
+def : RWSysReg<"MPUIR_EL2", 0b1, 0b100, 0b0000, 0b0000, 0b100>;
//Protection Region Enable Register
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"PRENR_EL1", 0b11, 0b000, 0b0110, 0b0001, 0b001>;
-def : RWSysReg<"PRENR_EL2", 0b11, 0b100, 0b0110, 0b0001, 0b001>;
+def : RWSysReg<"PRENR_EL1", 0b1, 0b000, 0b0110, 0b0001, 0b001>;
+def : RWSysReg<"PRENR_EL2", 0b1, 0b100, 0b0110, 0b0001, 0b001>;
//Protection Region Selection Register
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"PRSELR_EL1", 0b11, 0b000, 0b0110, 0b0010, 0b001>;
-def : RWSysReg<"PRSELR_EL2", 0b11, 0b100, 0b0110, 0b0010, 0b001>;
+def : RWSysReg<"PRSELR_EL1", 0b1, 0b000, 0b0110, 0b0010, 0b001>;
+def : RWSysReg<"PRSELR_EL2", 0b1, 0b100, 0b0110, 0b0010, 0b001>;
//Protection Region Base Address Register
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"PRBAR_EL1", 0b11, 0b000, 0b0110, 0b1000, 0b000>;
-def : RWSysReg<"PRBAR_EL2", 0b11, 0b100, 0b0110, 0b1000, 0b000>;
+def : RWSysReg<"PRBAR_EL1", 0b1, 0b000, 0b0110, 0b1000, 0b000>;
+def : RWSysReg<"PRBAR_EL2", 0b1, 0b100, 0b0110, 0b1000, 0b000>;
//Protection Region Limit Address Register
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"PRLAR_EL1", 0b11, 0b000, 0b0110, 0b1000, 0b001>;
-def : RWSysReg<"PRLAR_EL2", 0b11, 0b100, 0b0110, 0b1000, 0b001>;
+def : RWSysReg<"PRLAR_EL1", 0b1, 0b000, 0b0110, 0b1000, 0b001>;
+def : RWSysReg<"PRLAR_EL2", 0b1, 0b100, 0b0110, 0b1000, 0b001>;
foreach n = 1-15 in {
foreach x = 1-2 in {
//Direct access to Protection Region Base Address Register for n th MPU region
def : RWSysReg<!strconcat("PRBAR"#n, "_EL"#x),
- 0b11, 0b000, 0b0110, 0b1000, 0b000>{
+ 0b1, 0b000, 0b0110, 0b1000, 0b000>{
let Encoding{5-2} = n;
let Encoding{13} = !add(x,-1);
}
def : RWSysReg<!strconcat("PRLAR"#n, "_EL"#x),
- 0b11, 0b000, 0b0110, 0b1000, 0b001>{
+ 0b1, 0b000, 0b0110, 0b1000, 0b001>{
let Encoding{5-2} = n;
let Encoding{13} = !add(x,-1);
}
@@ -1777,196 +1777,196 @@ foreach x = 1-2 in {
// v8.1a "Privileged Access Never" extension-specific system registers
let Requires = [{ {AArch64::FeaturePAN} }] in
-def : RWSysReg<"PAN", 0b11, 0b000, 0b0100, 0b0010, 0b011>;
+def : RWSysReg<"PAN", 0b1, 0b000, 0b0100, 0b0010, 0b011>;
// v8.1a "Limited Ordering Regions" extension-specific system registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureLOR} }] in {
-def : RWSysReg<"LORSA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b000>;
-def : RWSysReg<"LOREA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b001>;
-def : RWSysReg<"LORN_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b010>;
-def : RWSysReg<"LORC_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b011>;
+def : RWSysReg<"LORSA_EL1", 0b1, 0b000, 0b1010, 0b0100, 0b000>;
+def : RWSysReg<"LOREA_EL1", 0b1, 0b000, 0b1010, 0b0100, 0b001>;
+def : RWSysReg<"LORN_EL1", 0b1, 0b000, 0b1010, 0b0100, 0b010>;
+def : RWSysReg<"LORC_EL1", 0b1, 0b000, 0b1010, 0b0100, 0b011>;
}
// v8.1a "Virtualization Host extensions" system registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureVH} }] in {
-def : RWSysReg<"TTBR1_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b001>;
-def : RWSysReg<"CNTHV_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b000>;
-def : RWSysReg<"CNTHV_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b010>;
-def : RWSysReg<"CNTHV_CTL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b001>;
-def : RWSysReg<"SCTLR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b000>;
-def : RWSysReg<"CPACR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b010>;
-def : RWSysReg<"TTBR0_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b000>;
-def : RWSysReg<"TTBR1_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b001>;
-def : RWSysReg<"TCR_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b010>;
-def : RWSysReg<"AFSR0_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b000>;
-def : RWSysReg<"AFSR1_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b001>;
-def : RWSysReg<"ESR_EL12", 0b11, 0b101, 0b0101, 0b0010, 0b000>;
-def : RWSysReg<"FAR_EL12", 0b11, 0b101, 0b0110, 0b0000, 0b000>;
-def : RWSysReg<"MAIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b000>;
-def : RWSysReg<"AMAIR_EL12", 0b11, 0b101, 0b1010, 0b0011, 0b000>;
-def : RWSysReg<"VBAR_EL12", 0b11, 0b101, 0b1100, 0b0000, 0b000>;
-def : RWSysReg<"CONTEXTIDR_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b001>;
-def : RWSysReg<"CNTKCTL_EL12", 0b11, 0b101, 0b1110, 0b0001, 0b000>;
-def : RWSysReg<"CNTP_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b000>;
-def : RWSysReg<"CNTP_CTL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b001>;
-def : RWSysReg<"CNTP_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b010>;
-def : RWSysReg<"CNTV_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b000>;
-def : RWSysReg<"CNTV_CTL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b001>;
-def : RWSysReg<"CNTV_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b010>;
-def : RWSysReg<"SPSR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b000>;
-def : RWSysReg<"ELR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b001>;
+def : RWSysReg<"TTBR1_EL2", 0b1, 0b100, 0b0010, 0b0000, 0b001>;
+def : RWSysReg<"CNTHV_TVAL_EL2", 0b1, 0b100, 0b1110, 0b0011, 0b000>;
+def : RWSysReg<"CNTHV_CVAL_EL2", 0b1, 0b100, 0b1110, 0b0011, 0b010>;
+def : RWSysReg<"CNTHV_CTL_EL2", 0b1, 0b100, 0b1110, 0b0011, 0b001>;
+def : RWSysReg<"SCTLR_EL12", 0b1, 0b101, 0b0001, 0b0000, 0b000>;
+def : RWSysReg<"CPACR_EL12", 0b1, 0b101, 0b0001, 0b0000, 0b010>;
+def : RWSysReg<"TTBR0_EL12", 0b1, 0b101, 0b0010, 0b0000, 0b000>;
+def : RWSysReg<"TTBR1_EL12", 0b1, 0b101, 0b0010, 0b0000, 0b001>;
+def : RWSysReg<"TCR_EL12", 0b1, 0b101, 0b0010, 0b0000, 0b010>;
+def : RWSysReg<"AFSR0_EL12", 0b1, 0b101, 0b0101, 0b0001, 0b000>;
+def : RWSysReg<"AFSR1_EL12", 0b1, 0b101, 0b0101, 0b0001, 0b001>;
+def : RWSysReg<"ESR_EL12", 0b1, 0b101, 0b0101, 0b0010, 0b000>;
+def : RWSysReg<"FAR_EL12", 0b1, 0b101, 0b0110, 0b0000, 0b000>;
+def : RWSysReg<"MAIR_EL12", 0b1, 0b101, 0b1010, 0b0010, 0b000>;
+def : RWSysReg<"AMAIR_EL12", 0b1, 0b101, 0b1010, 0b0011, 0b000>;
+def : RWSysReg<"VBAR_EL12", 0b1, 0b101, 0b1100, 0b0000, 0b000>;
+def : RWSysReg<"CONTEXTIDR_EL12", 0b1, 0b101, 0b1101, 0b0000, 0b001>;
+def : RWSysReg<"CNTKCTL_EL12", 0b1, 0b101, 0b1110, 0b0001, 0b000>;
+def : RWSysReg<"CNTP_TVAL_EL02", 0b1, 0b101, 0b1110, 0b0010, 0b000>;
+def : RWSysReg<"CNTP_CTL_EL02", 0b1, 0b101, 0b1110, 0b0010, 0b001>;
+def : RWSysReg<"CNTP_CVAL_EL02", 0b1, 0b101, 0b1110, 0b0010, 0b010>;
+def : RWSysReg<"CNTV_TVAL_EL02", 0b1, 0b101, 0b1110, 0b0011, 0b000>;
+def : RWSysReg<"CNTV_CTL_EL02", 0b1, 0b101, 0b1110, 0b0011, 0b001>;
+def : RWSysReg<"CNTV_CVAL_EL02", 0b1, 0b101, 0b1110, 0b0011, 0b010>;
+def : RWSysReg<"SPSR_EL12", 0b1, 0b101, 0b0100, 0b0000, 0b000>;
+def : RWSysReg<"ELR_EL12", 0b1, 0b101, 0b0100, 0b0000, 0b001>;
let Requires = [{ {AArch64::FeatureCONTEXTIDREL2} }] in {
- def : RWSysReg<"CONTEXTIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b001>;
+ def : RWSysReg<"CONTEXTIDR_EL2", 0b1, 0b100, 0b1101, 0b0000, 0b001>;
}
}
// v8.2a registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeaturePsUAO} }] in
-def : RWSysReg<"UAO", 0b11, 0b000, 0b0100, 0b0010, 0b100>;
+def : RWSysReg<"UAO", 0b1, 0b000, 0b0100, 0b0010, 0b100>;
// v8.2a "Statistical Profiling extension" registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureSPE} }] in {
-def : RWSysReg<"PMBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b000>;
-def : RWSysReg<"PMBPTR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b001>;
-def : RWSysReg<"PMBSR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b011>;
-def : ROSysReg<"PMBIDR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b111>;
-def : RWSysReg<"PMSCR_EL2", 0b11, 0b100, 0b1001, 0b1001, 0b000>;
-def : RWSysReg<"PMSCR_EL12", 0b11, 0b101, 0b1001, 0b1001, 0b000>;
-def : RWSysReg<"PMSCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b000>;
-def : RWSysReg<"PMSICR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b010>;
-def : RWSysReg<"PMSIRR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b011>;
-def : RWSysReg<"PMSFCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b100>;
-def : RWSysReg<"PMSEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b101>;
-def : RWSysReg<"PMSLATFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b110>;
-def : ROSysReg<"PMSIDR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b111>;
+def : RWSysReg<"PMBLIMITR_EL1", 0b1, 0b000, 0b1001, 0b1010, 0b000>;
+def : RWSysReg<"PMBPTR_EL1", 0b1, 0b000, 0b1001, 0b1010, 0b001>;
+def : RWSysReg<"PMBSR_EL1", 0b1, 0b000, 0b1001, 0b1010, 0b011>;
+def : ROSysReg<"PMBIDR_EL1", 0b1, 0b000, 0b1001, 0b1010, 0b111>;
+def : RWSysReg<"PMSCR_EL2", 0b1, 0b100, 0b1001, 0b1001, 0b000>;
+def : RWSysReg<"PMSCR_EL12", 0b1, 0b101, 0b1001, 0b1001, 0b000>;
+def : RWSysReg<"PMSCR_EL1", 0b1, 0b000, 0b1001, 0b1001, 0b000>;
+def : RWSysReg<"PMSICR_EL1", 0b1, 0b000, 0b1001, 0b1001, 0b010>;
+def : RWSysReg<"PMSIRR_EL1", 0b1, 0b000, 0b1001, 0b1001, 0b011>;
+def : RWSysReg<"PMSFCR_EL1", 0b1, 0b000, 0b1001, 0b1001, 0b100>;
+def : RWSysReg<"PMSEVFR_EL1", 0b1, 0b000, 0b1001, 0b1001, 0b101>;
+def : RWSysReg<"PMSLATFR_EL1", 0b1, 0b000, 0b1001, 0b1001, 0b110>;
+def : ROSysReg<"PMSIDR_EL1", 0b1, 0b000, 0b1001, 0b1001, 0b111>;
}
// v8.2a "RAS extension" registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureRAS} }] in {
-def : RWSysReg<"ERRSELR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b001>;
-def : RWSysReg<"ERXCTLR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b001>;
-def : RWSysReg<"ERXSTATUS_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b010>;
-def : RWSysReg<"ERXADDR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b011>;
-def : RWSysReg<"ERXMISC0_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b000>;
-def : RWSysReg<"ERXMISC1_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b001>;
-def : RWSysReg<"DISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b001>;
-def : RWSysReg<"VDISR_EL2", 0b11, 0b100, 0b1100, 0b0001, 0b001>;
-def : RWSysReg<"VSESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b011>;
+def : RWSysReg<"ERRSELR_EL1", 0b1, 0b000, 0b0101, 0b0011, 0b001>;
+def : RWSysReg<"ERXCTLR_EL1", 0b1, 0b000, 0b0101, 0b0100, 0b001>;
+def : RWSysReg<"ERXSTATUS_EL1", 0b1, 0b000, 0b0101, 0b0100, 0b010>;
+def : RWSysReg<"ERXADDR_EL1", 0b1, 0b000, 0b0101, 0b0100, 0b011>;
+def : RWSysReg<"ERXMISC0_EL1", 0b1, 0b000, 0b0101, 0b0101, 0b000>;
+def : RWSysReg<"ERXMISC1_EL1", 0b1, 0b000, 0b0101, 0b0101, 0b001>;
+def : RWSysReg<"DISR_EL1", 0b1, 0b000, 0b1100, 0b0001, 0b001>;
+def : RWSysReg<"VDISR_EL2", 0b1, 0b100, 0b1100, 0b0001, 0b001>;
+def : RWSysReg<"VSESR_EL2", 0b1, 0b100, 0b0101, 0b0010, 0b011>;
}
// v8.3a "Pointer authentication extension" registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeaturePAuth} }] in {
-def : RWSysReg<"APIAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b000>;
-def : RWSysReg<"APIAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b001>;
-def : RWSysReg<"APIBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b010>;
-def : RWSysReg<"APIBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b011>;
-def : RWSysReg<"APDAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b000>;
-def : RWSysReg<"APDAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b001>;
-def : RWSysReg<"APDBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b010>;
-def : RWSysReg<"APDBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b011>;
-def : RWSysReg<"APGAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b000>;
-def : RWSysReg<"APGAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b001>;
+def : RWSysReg<"APIAKeyLo_EL1", 0b1, 0b000, 0b0010, 0b0001, 0b000>;
+def : RWSysReg<"APIAKeyHi_EL1", 0b1, 0b000, 0b0010, 0b0001, 0b001>;
+def : RWSysReg<"APIBKeyLo_EL1", 0b1, 0b000, 0b0010, 0b0001, 0b010>;
+def : RWSysReg<"APIBKeyHi_EL1", 0b1, 0b000, 0b0010, 0b0001, 0b011>;
+def : RWSysReg<"APDAKeyLo_EL1", 0b1, 0b000, 0b0010, 0b0010, 0b000>;
+def : RWSysReg<"APDAKeyHi_EL1", 0b1, 0b000, 0b0010, 0b0010, 0b001>;
+def : RWSysReg<"APDBKeyLo_EL1", 0b1, 0b000, 0b0010, 0b0010, 0b010>;
+def : RWSysReg<"APDBKeyHi_EL1", 0b1, 0b000, 0b0010, 0b0010, 0b011>;
+def : RWSysReg<"APGAKeyLo_EL1", 0b1, 0b000, 0b0010, 0b0011, 0b000>;
+def : RWSysReg<"APGAKeyHi_EL1", 0b1, 0b000, 0b0010, 0b0011, 0b001>;
}
// v8.4 "Secure Exception Level 2 extension"
let Requires = [{ {AArch64::FeatureSEL2} }] in {
// v8.4a "Virtualization secure second stage translation" registers
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"VSTCR_EL2" , 0b11, 0b100, 0b0010, 0b0110, 0b010>;
-def : RWSysReg<"VSTTBR_EL2", 0b11, 0b100, 0b0010, 0b0110, 0b000> {
+def : RWSysReg<"VSTCR_EL2" , 0b1, 0b100, 0b0010, 0b0110, 0b010>;
+def : RWSysReg<"VSTTBR_EL2", 0b1, 0b100, 0b0010, 0b0110, 0b000> {
let Requires = [{ {AArch64::HasV8_0aOps} }];
}
// v8.4a "Virtualization timer" registers
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"CNTHVS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b000>;
-def : RWSysReg<"CNTHVS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b010>;
-def : RWSysReg<"CNTHVS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b001>;
-def : RWSysReg<"CNTHPS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b000>;
-def : RWSysReg<"CNTHPS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b010>;
-def : RWSysReg<"CNTHPS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b001>;
+def : RWSysReg<"CNTHVS_TVAL_EL2", 0b1, 0b100, 0b1110, 0b0100, 0b000>;
+def : RWSysReg<"CNTHVS_CVAL_EL2", 0b1, 0b100, 0b1110, 0b0100, 0b010>;
+def : RWSysReg<"CNTHVS_CTL_EL2", 0b1, 0b100, 0b1110, 0b0100, 0b001>;
+def : RWSysReg<"CNTHPS_TVAL_EL2", 0b1, 0b100, 0b1110, 0b0101, 0b000>;
+def : RWSysReg<"CNTHPS_CVAL_EL2", 0b1, 0b100, 0b1110, 0b0101, 0b010>;
+def : RWSysReg<"CNTHPS_CTL_EL2", 0b1, 0b100, 0b1110, 0b0101, 0b001>;
// v8.4a "Virtualization debug state" registers
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>;
+def : RWSysReg<"SDER32_EL2", 0b1, 0b100, 0b0001, 0b0011, 0b001>;
} // FeatureSEL2
// v8.4a RAS registers
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>;
-def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>;
-def : RWSysReg<"ERXMISC2_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b010>;
-def : RWSysReg<"ERXMISC3_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b011>;
-def : ROSysReg<"ERXPFGF_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b100>;
+def : RWSysReg<"ERXPFGCTL_EL1", 0b1, 0b000, 0b0101, 0b0100, 0b101>;
+def : RWSysReg<"ERXPFGCDN_EL1", 0b1, 0b000, 0b0101, 0b0100, 0b110>;
+def : RWSysReg<"ERXMISC2_EL1", 0b1, 0b000, 0b0101, 0b0101, 0b010>;
+def : RWSysReg<"ERXMISC3_EL1", 0b1, 0b000, 0b0101, 0b0101, 0b011>;
+def : ROSysReg<"ERXPFGF_EL1", 0b1, 0b000, 0b0101, 0b0100, 0b100>;
// v8.4a MPAM registers
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"MPAMVPMV_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b001>;
-def : RWSysReg<"MPAMVPM0_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b000>;
-def : RWSysReg<"MPAMVPM1_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b001>;
-def : RWSysReg<"MPAMVPM2_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b010>;
-def : RWSysReg<"MPAMVPM3_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b011>;
-def : RWSysReg<"MPAMVPM4_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b100>;
-def : RWSysReg<"MPAMVPM5_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b101>;
-def : RWSysReg<"MPAMVPM6_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b110>;
-def : RWSysReg<"MPAMVPM7_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b111>;
+def : RWSysReg<"MPAMVPMV_EL2", 0b1, 0b100, 0b1010, 0b0100, 0b001>;
+def : RWSysReg<"MPAMVPM0_EL2", 0b1, 0b100, 0b1010, 0b0110, 0b000>;
+def : RWSysReg<"MPAMVPM1_EL2", 0b1, 0b100, 0b1010, 0b0110, 0b001>;
+def : RWSysReg<"MPAMVPM2_EL2", 0b1, 0b100, 0b1010, 0b0110, 0b010>;
+def : RWSysReg<"MPAMVPM3_EL2", 0b1, 0b100, 0b1010, 0b0110, 0b011>;
+def : RWSysReg<"MPAMVPM4_EL2", 0b1, 0b100, 0b1010, 0b0110, 0b100>;
+def : RWSysReg<"MPAMVPM5_EL2", 0b1, 0b100, 0b1010, 0b0110, 0b101>;
+def : RWSysReg<"MPAMVPM6_EL2", 0b1, 0b100, 0b1010, 0b0110, 0b110>;
+def : RWSysReg<"MPAMVPM7_EL2", 0b1, 0b100, 0b1010, 0b0110, 0b111>;
// v8.4a Activity Monitor registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureAM} }] in {
-def : RWSysReg<"AMCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b000>;
-def : ROSysReg<"AMCFGR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b001>;
-def : ROSysReg<"AMCGCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b010>;
-def : RWSysReg<"AMUSERENR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b011>;
-def : RWSysReg<"AMCNTENCLR0_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b100>;
-def : RWSysReg<"AMCNTENSET0_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b101>;
-def : RWSysReg<"AMEVCNTR00_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b000>;
-def : RWSysReg<"AMEVCNTR01_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b001>;
-def : RWSysReg<"AMEVCNTR02_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b010>;
-def : RWSysReg<"AMEVCNTR03_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b011>;
-def : ROSysReg<"AMEVTYPER00_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b000>;
-def : ROSysReg<"AMEVTYPER01_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b001>;
-def : ROSysReg<"AMEVTYPER02_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b010>;
-def : ROSysReg<"AMEVTYPER03_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b011>;
-def : RWSysReg<"AMCNTENCLR1_EL0", 0b11, 0b011, 0b1101, 0b0011, 0b000>;
-def : RWSysReg<"AMCNTENSET1_EL0", 0b11, 0b011, 0b1101, 0b0011, 0b001>;
-def : RWSysReg<"AMEVCNTR10_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b000>;
-def : RWSysReg<"AMEVCNTR11_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b001>;
-def : RWSysReg<"AMEVCNTR12_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b010>;
-def : RWSysReg<"AMEVCNTR13_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b011>;
-def : RWSysReg<"AMEVCNTR14_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b100>;
-def : RWSysReg<"AMEVCNTR15_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b101>;
-def : RWSysReg<"AMEVCNTR16_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b110>;
-def : RWSysReg<"AMEVCNTR17_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b111>;
-def : RWSysReg<"AMEVCNTR18_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b000>;
-def : RWSysReg<"AMEVCNTR19_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b001>;
-def : RWSysReg<"AMEVCNTR110_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b010>;
-def : RWSysReg<"AMEVCNTR111_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b011>;
-def : RWSysReg<"AMEVCNTR112_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b100>;
-def : RWSysReg<"AMEVCNTR113_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b101>;
-def : RWSysReg<"AMEVCNTR114_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b110>;
-def : RWSysReg<"AMEVCNTR115_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b111>;
-def : RWSysReg<"AMEVTYPER10_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b000>;
-def : RWSysReg<"AMEVTYPER11_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b001>;
-def : RWSysReg<"AMEVTYPER12_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b010>;
-def : RWSysReg<"AMEVTYPER13_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b011>;
-def : RWSysReg<"AMEVTYPER14_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b100>;
-def : RWSysReg<"AMEVTYPER15_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b101>;
-def : RWSysReg<"AMEVTYPER16_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b110>;
-def : RWSysReg<"AMEVTYPER17_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b111>;
-def : RWSysReg<"AMEVTYPER18_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b000>;
-def : RWSysReg<"AMEVTYPER19_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b001>;
-def : RWSysReg<"AMEVTYPER110_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b010>;
-def : RWSysReg<"AMEVTYPER111_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b011>;
-def : RWSysReg<"AMEVTYPER112_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b100>;
-def : RWSysReg<"AMEVTYPER113_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b101>;
-def : RWSysReg<"AMEVTYPER114_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b110>;
-def : RWSysReg<"AMEVTYPER115_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b111>;
+def : RWSysReg<"AMCR_EL0", 0b1, 0b011, 0b1101, 0b0010, 0b000>;
+def : ROSysReg<"AMCFGR_EL0", 0b1, 0b011, 0b1101, 0b0010, 0b001>;
+def : ROSysReg<"AMCGCR_EL0", 0b1, 0b011, 0b1101, 0b0010, 0b010>;
+def : RWSysReg<"AMUSERENR_EL0", 0b1, 0b011, 0b1101, 0b0010, 0b011>;
+def : RWSysReg<"AMCNTENCLR0_EL0", 0b1, 0b011, 0b1101, 0b0010, 0b100>;
+def : RWSysReg<"AMCNTENSET0_EL0", 0b1, 0b011, 0b1101, 0b0010, 0b101>;
+def : RWSysReg<"AMEVCNTR00_EL0", 0b1, 0b011, 0b1101, 0b0100, 0b000>;
+def : RWSysReg<"AMEVCNTR01_EL0", 0b1, 0b011, 0b1101, 0b0100, 0b001>;
+def : RWSysReg<"AMEVCNTR02_EL0", 0b1, 0b011, 0b1101, 0b0100, 0b010>;
+def : RWSysReg<"AMEVCNTR03_EL0", 0b1, 0b011, 0b1101, 0b0100, 0b011>;
+def : ROSysReg<"AMEVTYPER00_EL0", 0b1, 0b011, 0b1101, 0b0110, 0b000>;
+def : ROSysReg<"AMEVTYPER01_EL0", 0b1, 0b011, 0b1101, 0b0110, 0b001>;
+def : ROSysReg<"AMEVTYPER02_EL0", 0b1, 0b011, 0b1101, 0b0110, 0b010>;
+def : ROSysReg<"AMEVTYPER03_EL0", 0b1, 0b011, 0b1101, 0b0110, 0b011>;
+def : RWSysReg<"AMCNTENCLR1_EL0", 0b1, 0b011, 0b1101, 0b0011, 0b000>;
+def : RWSysReg<"AMCNTENSET1_EL0", 0b1, 0b011, 0b1101, 0b0011, 0b001>;
+def : RWSysReg<"AMEVCNTR10_EL0", 0b1, 0b011, 0b1101, 0b1100, 0b000>;
+def : RWSysReg<"AMEVCNTR11_EL0", 0b1, 0b011, 0b1101, 0b1100, 0b001>;
+def : RWSysReg<"AMEVCNTR12_EL0", 0b1, 0b011, 0b1101, 0b1100, 0b010>;
+def : RWSysReg<"AMEVCNTR13_EL0", 0b1, 0b011, 0b1101, 0b1100, 0b011>;
+def : RWSysReg<"AMEVCNTR14_EL0", 0b1, 0b011, 0b1101, 0b1100, 0b100>;
+def : RWSysReg<"AMEVCNTR15_EL0", 0b1, 0b011, 0b1101, 0b1100, 0b101>;
+def : RWSysReg<"AMEVCNTR16_EL0", 0b1, 0b011, 0b1101, 0b1100, 0b110>;
+def : RWSysReg<"AMEVCNTR17_EL0", 0b1, 0b011, 0b1101, 0b1100, 0b111>;
+def : RWSysReg<"AMEVCNTR18_EL0", 0b1, 0b011, 0b1101, 0b1101, 0b000>;
+def : RWSysReg<"AMEVCNTR19_EL0", 0b1, 0b011, 0b1101, 0b1101, 0b001>;
+def : RWSysReg<"AMEVCNTR110_EL0", 0b1, 0b011, 0b1101, 0b1101, 0b010>;
+def : RWSysReg<"AMEVCNTR111_EL0", 0b1, 0b011, 0b1101, 0b1101, 0b011>;
+def : RWSysReg<"AMEVCNTR112_EL0", 0b1, 0b011, 0b1101, 0b1101, 0b100>;
+def : RWSysReg<"AMEVCNTR113_EL0", 0b1, 0b011, 0b1101, 0b1101, 0b101>;
+def : RWSysReg<"AMEVCNTR114_EL0", 0b1, 0b011, 0b1101, 0b1101, 0b110>;
+def : RWSysReg<"AMEVCNTR115_EL0", 0b1, 0b011, 0b1101, 0b1101, 0b111>;
+def : RWSysReg<"AMEVTYPER10_EL0", 0b1, 0b011, 0b1101, 0b1110, 0b000>;
+def : RWSysReg<"AMEVTYPER11_EL0", 0b1, 0b011, 0b1101, 0b1110, 0b001>;
+def : RWSysReg<"AMEVTYPER12_EL0", 0b1, 0b011, 0b1101, 0b1110, 0b010>;
+def : RWSysReg<"AMEVTYPER13_EL0", 0b1, 0b011, 0b1101, 0b1110, 0b011>;
+def : RWSysReg<"AMEVTYPER14_EL0", 0b1, 0b011, 0b1101, 0b1110, 0b100>;
+def : RWSysReg<"AMEVTYPER15_EL0", 0b1, 0b011, 0b1101, 0b1110, 0b101>;
+def : RWSysReg<"AMEVTYPER16_EL0", 0b1, 0b011, 0b1101, 0b1110, 0b110>;
+def : RWSysReg<"AMEVTYPER17_EL0", 0b1, 0b011, 0b1101, 0b1110, 0b111>;
+def : RWSysReg<"AMEVTYPER18_EL0", 0b1, 0b011, 0b1101, 0b1111, 0b000>;
+def : RWSysReg<"AMEVTYPER19_EL0", 0b1, 0b011, 0b1101, 0b1111, 0b001>;
+def : RWSysReg<"AMEVTYPER110_EL0", 0b1, 0b011, 0b1101, 0b1111, 0b010>;
+def : RWSysReg<"AMEVTYPER111_EL0", 0b1, 0b011, 0b1101, 0b1111, 0b011>;
+def : RWSysReg<"AMEVTYPER112_EL0", 0b1, 0b011, 0b1101, 0b1111, 0b100>;
+def : RWSysReg<"AMEVTYPER113_EL0", 0b1, 0b011, 0b1101, 0b1111, 0b101>;
+def : RWSysReg<"AMEVTYPER114_EL0", 0b1, 0b011, 0b1101, 0b1111, 0b110>;
+def : RWSysReg<"AMEVTYPER115_EL0", 0b1, 0b011, 0b1101, 0b1111, 0b111>;
} //FeatureAM
// v8.4a Trace Extension registers
@@ -1977,85 +1977,85 @@ def : RWSysReg<"AMEVTYPER115_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b111>;
//
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureTRACEV8_4} }] in {
-def : RWSysReg<"TRFCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b001>;
-def : RWSysReg<"TRFCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b001>;
-def : RWSysReg<"TRFCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b001>;
+def : RWSysReg<"TRFCR_EL1", 0b1, 0b000, 0b0001, 0b0010, 0b001>;
+def : RWSysReg<"TRFCR_EL2", 0b1, 0b100, 0b0001, 0b0010, 0b001>;
+def : RWSysReg<"TRFCR_EL12", 0b1, 0b101, 0b0001, 0b0010, 0b001>;
} //FeatureTRACEV8_4
// v8.4a Timing insensitivity of data processing instructions
// DIT: Data Independent Timing instructions
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureDIT} }] in {
-def : RWSysReg<"DIT", 0b11, 0b011, 0b0100, 0b0010, 0b101>;
+def : RWSysReg<"DIT", 0b1, 0b011, 0b0100, 0b0010, 0b101>;
} //FeatureDIT
// v8.4a Enhanced Support for Nested Virtualization
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureNV} }] in {
-def : RWSysReg<"VNCR_EL2", 0b11, 0b100, 0b0010, 0b0010, 0b000>;
+def : RWSysReg<"VNCR_EL2", 0b1, 0b100, 0b0010, 0b0010, 0b000>;
} //FeatureNV
// SVE control registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureSVE} }] in {
-def : RWSysReg<"ZCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b000>;
-def : RWSysReg<"ZCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b000>;
-def : RWSysReg<"ZCR_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b000>;
-def : RWSysReg<"ZCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b000>;
+def : RWSysReg<"ZCR_EL1", 0b1, 0b000, 0b0001, 0b0010, 0b000>;
+def : RWSysReg<"ZCR_EL2", 0b1, 0b100, 0b0001, 0b0010, 0b000>;
+def : RWSysReg<"ZCR_EL3", 0b1, 0b110, 0b0001, 0b0010, 0b000>;
+def : RWSysReg<"ZCR_EL12", 0b1, 0b101, 0b0001, 0b0010, 0b000>;
}
// V8.5a Spectre mitigation SSBS register
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureSSBS} }] in
-def : RWSysReg<"SSBS", 0b11, 0b011, 0b0100, 0b0010, 0b110>;
+def : RWSysReg<"SSBS", 0b1, 0b011, 0b0100, 0b0010, 0b110>;
// v8.5a Memory Tagging Extension
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureMTE} }] in {
-def : RWSysReg<"TCO", 0b11, 0b011, 0b0100, 0b0010, 0b111>;
-def : RWSysReg<"GCR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b110>;
-def : RWSysReg<"RGSR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b101>;
-def : RWSysReg<"TFSR_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b000>;
-def : RWSysReg<"TFSR_EL2", 0b11, 0b100, 0b0101, 0b0110, 0b000>;
-def : RWSysReg<"TFSR_EL3", 0b11, 0b110, 0b0101, 0b0110, 0b000>;
-def : RWSysReg<"TFSR_EL12", 0b11, 0b101, 0b0101, 0b0110, 0b000>;
-def : RWSysReg<"TFSRE0_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b001>;
-def : ROSysReg<"GMID_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b100>;
+def : RWSysReg<"TCO", 0b1, 0b011, 0b0100, 0b0010, 0b111>;
+def : RWSysReg<"GCR_EL1", 0b1, 0b000, 0b0001, 0b0000, 0b110>;
+def : RWSysReg<"RGSR_EL1", 0b1, 0b000, 0b0001, 0b0000, 0b101>;
+def : RWSysReg<"TFSR_EL1", 0b1, 0b000, 0b0101, 0b0110, 0b000>;
+def : RWSysReg<"TFSR_EL2", 0b1, 0b100, 0b0101, 0b0110, 0b000>;
+def : RWSysReg<"TFSR_EL3", 0b1, 0b110, 0b0101, 0b0110, 0b000>;
+def : RWSysReg<"TFSR_EL12", 0b1, 0b101, 0b0101, 0b0110, 0b000>;
+def : RWSysReg<"TFSRE0_EL1", 0b1, 0b000, 0b0101, 0b0110, 0b001>;
+def : ROSysReg<"GMID_EL1", 0b1, 0b001, 0b0000, 0b0000, 0b100>;
} // HasMTE
// Embedded Trace Extension R/W System registers
let Requires = [{ {AArch64::FeatureETE} }] in {
// Name Op0 Op1 CRn CRm Op2
-def : RWSysReg<"TRCRSR", 0b10, 0b001, 0b0000, 0b1010, 0b000>;
+def : RWSysReg<"TRCRSR", 0b0, 0b001, 0b0000, 0b1010, 0b000>;
// TRCEXTINSELR0 has the same encoding as ETM TRCEXTINSELR
-def : RWSysReg<"TRCEXTINSELR0", 0b10, 0b001, 0b0000, 0b1000, 0b100>;
-def : RWSysReg<"TRCEXTINSELR1", 0b10, 0b001, 0b0000, 0b1001, 0b100>;
-def : RWSysReg<"TRCEXTINSELR2", 0b10, 0b001, 0b0000, 0b1010, 0b100>;
-def : RWSysReg<"TRCEXTINSELR3", 0b10, 0b001, 0b0000, 0b1011, 0b100>;
+def : RWSysReg<"TRCEXTINSELR0", 0b0, 0b001, 0b0000, 0b1000, 0b100>;
+def : RWSysReg<"TRCEXTINSELR1", 0b0, 0b001, 0b0000, 0b1001, 0b100>;
+def : RWSysReg<"TRCEXTINSELR2", 0b0, 0b001, 0b0000, 0b1010, 0b100>;
+def : RWSysReg<"TRCEXTINSELR3", 0b0, 0b001, 0b0000, 0b1011, 0b100>;
} // FeatureETE
// Trace Buffer Extension System registers
let Requires = [{ {AArch64::FeatureTRBE} }] in {
// Name Op0 Op1 CRn CRm Op2
-def : RWSysReg<"TRBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b000>;
-def : RWSysReg<"TRBPTR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b001>;
-def : RWSysReg<"TRBBASER_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b010>;
-def : RWSysReg<"TRBSR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b011>;
-def : RWSysReg<"TRBMAR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b100>;
-def : RWSysReg<"TRBMPAM_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b101>;
-def : RWSysReg<"TRBTRG_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b110>;
-def : ROSysReg<"TRBIDR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b111>;
+def : RWSysReg<"TRBLIMITR_EL1", 0b1, 0b000, 0b1001, 0b1011, 0b000>;
+def : RWSysReg<"TRBPTR_EL1", 0b1, 0b000, 0b1001, 0b1011, 0b001>;
+def : RWSysReg<"TRBBASER_EL1", 0b1, 0b000, 0b1001, 0b1011, 0b010>;
+def : RWSysReg<"TRBSR_EL1", 0b1, 0b000, 0b1001, 0b1011, 0b011>;
+def : RWSysReg<"TRBMAR_EL1", 0b1, 0b000, 0b1001, 0b1011, 0b100>;
+def : RWSysReg<"TRBMPAM_EL1", 0b1, 0b000, 0b1001, 0b1011, 0b101>;
+def : RWSysReg<"TRBTRG_EL1", 0b1, 0b000, 0b1001, 0b1011, 0b110>;
+def : ROSysReg<"TRBIDR_EL1", 0b1, 0b000, 0b1001, 0b1011, 0b111>;
} // FeatureTRBE
// v8.6a Activity Monitors Virtualization Support
let Requires = [{ {AArch64::FeatureAMVS} }] in {
// Name Op0 Op1 CRn CRm Op2
-def : ROSysReg<"AMCG1IDR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b110>;
+def : ROSysReg<"AMCG1IDR_EL0", 0b1, 0b011, 0b1101, 0b0010, 0b110>;
foreach n = 0-15 in {
foreach x = 0-1 in {
def : RWSysReg<"AMEVCNTVOFF"#x#n#"_EL2",
- 0b11, 0b100, 0b1101, 0b1000, 0b000>{
+ 0b1, 0b100, 0b1101, 0b1000, 0b000>{
let Encoding{4} = x;
let Encoding{3-0} = n;
}
@@ -2066,345 +2066,345 @@ foreach n = 0-15 in {
// v8.6a Fine Grained Virtualization Traps
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureFineGrainedTraps} }] in {
-def : RWSysReg<"HFGRTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b100>;
-def : RWSysReg<"HFGWTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b101>;
-def : RWSysReg<"HFGITR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b110>;
-def : RWSysReg<"HDFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b100>;
-def : RWSysReg<"HDFGWTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b101>;
-def : RWSysReg<"HAFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b110>;
+def : RWSysReg<"HFGRTR_EL2", 0b1, 0b100, 0b0001, 0b0001, 0b100>;
+def : RWSysReg<"HFGWTR_EL2", 0b1, 0b100, 0b0001, 0b0001, 0b101>;
+def : RWSysReg<"HFGITR_EL2", 0b1, 0b100, 0b0001, 0b0001, 0b110>;
+def : RWSysReg<"HDFGRTR_EL2", 0b1, 0b100, 0b0011, 0b0001, 0b100>;
+def : RWSysReg<"HDFGWTR_EL2", 0b1, 0b100, 0b0011, 0b0001, 0b101>;
+def : RWSysReg<"HAFGRTR_EL2", 0b1, 0b100, 0b0011, 0b0001, 0b110>;
// v8.9a/v9.4a additions to Fine Grained Traps (FEAT_FGT2)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"HDFGRTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b000>;
-def : RWSysReg<"HDFGWTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b001>;
-def : RWSysReg<"HFGRTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b010>;
-def : RWSysReg<"HFGWTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b011>;
-def : RWSysReg<"HFGITR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b111>;
+def : RWSysReg<"HDFGRTR2_EL2", 0b1, 0b100, 0b0011, 0b0001, 0b000>;
+def : RWSysReg<"HDFGWTR2_EL2", 0b1, 0b100, 0b0011, 0b0001, 0b001>;
+def : RWSysReg<"HFGRTR2_EL2", 0b1, 0b100, 0b0011, 0b0001, 0b010>;
+def : RWSysReg<"HFGWTR2_EL2", 0b1, 0b100, 0b0011, 0b0001, 0b011>;
+def : RWSysReg<"HFGITR2_EL2", 0b1, 0b100, 0b0011, 0b0001, 0b111>;
}
// v8.6a Enhanced Counter Virtualization
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureEnhancedCounterVirtualization} }] in {
-def : RWSysReg<"CNTSCALE_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b100>;
-def : RWSysReg<"CNTISCALE_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b101>;
-def : RWSysReg<"CNTPOFF_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b110>;
-def : RWSysReg<"CNTVFRQ_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b111>;
-def : ROSysReg<"CNTPCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b101>;
-def : ROSysReg<"CNTVCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b110>;
+def : RWSysReg<"CNTSCALE_EL2", 0b1, 0b100, 0b1110, 0b0000, 0b100>;
+def : RWSysReg<"CNTISCALE_EL2", 0b1, 0b100, 0b1110, 0b0000, 0b101>;
+def : RWSysReg<"CNTPOFF_EL2", 0b1, 0b100, 0b1110, 0b0000, 0b110>;
+def : RWSysReg<"CNTVFRQ_EL2", 0b1, 0b100, 0b1110, 0b0000, 0b111>;
+def : ROSysReg<"CNTPCTSS_EL0", 0b1, 0b011, 0b1110, 0b0000, 0b101>;
+def : ROSysReg<"CNTVCTSS_EL0", 0b1, 0b011, 0b1110, 0b0000, 0b110>;
}
// v8.7a LD64B/ST64B Accelerator Extension system register
let Requires = [{ {AArch64::FeatureLS64} }] in
-def : RWSysReg<"ACCDATA_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b101>;
+def : RWSysReg<"ACCDATA_EL1", 0b1, 0b000, 0b1101, 0b0000, 0b101>;
// Branch Record Buffer system registers
let Requires = [{ {AArch64::FeatureBRBE} }] in {
-def : RWSysReg<"BRBCR_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b000>;
-def : RWSysReg<"BRBCR_EL12", 0b10, 0b101, 0b1001, 0b0000, 0b000>;
-def : RWSysReg<"BRBCR_EL2", 0b10, 0b100, 0b1001, 0b0000, 0b000>;
-def : RWSysReg<"BRBFCR_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b001>;
-def : ROSysReg<"BRBIDR0_EL1", 0b10, 0b001, 0b1001, 0b0010, 0b000>;
-def : RWSysReg<"BRBINFINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b000>;
-def : RWSysReg<"BRBSRCINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b001>;
-def : RWSysReg<"BRBTGTINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b010>;
-def : RWSysReg<"BRBTS_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b010>;
+def : RWSysReg<"BRBCR_EL1", 0b0, 0b001, 0b1001, 0b0000, 0b000>;
+def : RWSysReg<"BRBCR_EL12", 0b0, 0b101, 0b1001, 0b0000, 0b000>;
+def : RWSysReg<"BRBCR_EL2", 0b0, 0b100, 0b1001, 0b0000, 0b000>;
+def : RWSysReg<"BRBFCR_EL1", 0b0, 0b001, 0b1001, 0b0000, 0b001>;
+def : ROSysReg<"BRBIDR0_EL1", 0b0, 0b001, 0b1001, 0b0010, 0b000>;
+def : RWSysReg<"BRBINFINJ_EL1", 0b0, 0b001, 0b1001, 0b0001, 0b000>;
+def : RWSysReg<"BRBSRCINJ_EL1", 0b0, 0b001, 0b1001, 0b0001, 0b001>;
+def : RWSysReg<"BRBTGTINJ_EL1", 0b0, 0b001, 0b1001, 0b0001, 0b010>;
+def : RWSysReg<"BRBTS_EL1", 0b0, 0b001, 0b1001, 0b0000, 0b010>;
foreach n = 0-31 in {
defvar nb = !cast<bits<5>>(n);
- def : ROSysReg<"BRBINF"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b00}>;
- def : ROSysReg<"BRBSRC"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b01}>;
- def : ROSysReg<"BRBTGT"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b10}>;
+ def : ROSysReg<"BRBINF"#n#"_EL1", 0b0, 0b001, 0b1000, nb{3-0}, {nb{4},0b00}>;
+ def : ROSysReg<"BRBSRC"#n#"_EL1", 0b0, 0b001, 0b1000, nb{3-0}, {nb{4},0b01}>;
+ def : ROSysReg<"BRBTGT"#n#"_EL1", 0b0, 0b001, 0b1000, nb{3-0}, {nb{4},0b10}>;
}
}
// Statistical Profiling Extension system register
let Requires = [{ {AArch64::FeatureSPE_EEF} }] in
-def : RWSysReg<"PMSNEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b001>;
+def : RWSysReg<"PMSNEVFR_EL1", 0b1, 0b000, 0b1001, 0b1001, 0b001>;
// Scalable Matrix Extension (SME)
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureSME} }] in {
-def : RWSysReg<"SMCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b110>;
-def : RWSysReg<"SMCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b110>;
-def : RWSysReg<"SMCR_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b110>;
-def : RWSysReg<"SMCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b110>;
-def : RWSysReg<"SVCR", 0b11, 0b011, 0b0100, 0b0010, 0b010>;
-def : RWSysReg<"SMPRI_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b100>;
-def : RWSysReg<"SMPRIMAP_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b101>;
-def : ROSysReg<"SMIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b110>;
-def : RWSysReg<"TPIDR2_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b101>;
+def : RWSysReg<"SMCR_EL1", 0b1, 0b000, 0b0001, 0b0010, 0b110>;
+def : RWSysReg<"SMCR_EL2", 0b1, 0b100, 0b0001, 0b0010, 0b110>;
+def : RWSysReg<"SMCR_EL3", 0b1, 0b110, 0b0001, 0b0010, 0b110>;
+def : RWSysReg<"SMCR_EL12", 0b1, 0b101, 0b0001, 0b0010, 0b110>;
+def : RWSysReg<"SVCR", 0b1, 0b011, 0b0100, 0b0010, 0b010>;
+def : RWSysReg<"SMPRI_EL1", 0b1, 0b000, 0b0001, 0b0010, 0b100>;
+def : RWSysReg<"SMPRIMAP_EL2", 0b1, 0b100, 0b0001, 0b0010, 0b101>;
+def : ROSysReg<"SMIDR_EL1", 0b1, 0b001, 0b0000, 0b0000, 0b110>;
+def : RWSysReg<"TPIDR2_EL0", 0b1, 0b011, 0b1101, 0b0000, 0b101>;
} // HasSME
// v8.4a MPAM and SME registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureMPAM, AArch64::FeatureSME} }] in {
-def : RWSysReg<"MPAMSM_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b011>;
+def : RWSysReg<"MPAMSM_EL1", 0b1, 0b000, 0b1010, 0b0101, 0b011>;
} // HasMPAM, HasSME
// v8.8a Non-Maskable Interrupts
let Requires = [{ {AArch64::FeatureNMI} }] in {
// Op0 Op1 CRn CRm Op2
- def : RWSysReg<"ALLINT", 0b11, 0b000, 0b0100, 0b0011, 0b000>;
- def : ROSysReg<"ICC_NMIAR1_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b101>; // FEAT_GICv3_NMI
+ def : RWSysReg<"ALLINT", 0b1, 0b000, 0b0100, 0b0011, 0b000>;
+ def : ROSysReg<"ICC_NMIAR1_EL1", 0b1, 0b000, 0b1100, 0b1001, 0b101>; // FEAT_GICv3_NMI
}
// v9.4a Guarded Control Stack Extension (GCS)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"GCSCR_EL1", 0b11, 0b000, 0b0010, 0b0101, 0b000>;
-def : RWSysReg<"GCSPR_EL1", 0b11, 0b000, 0b0010, 0b0101, 0b001>;
-def : RWSysReg<"GCSCRE0_EL1", 0b11, 0b000, 0b0010, 0b0101, 0b010>;
-def : RWSysReg<"GCSPR_EL0", 0b11, 0b011, 0b0010, 0b0101, 0b001>;
-def : RWSysReg<"GCSCR_EL2", 0b11, 0b100, 0b0010, 0b0101, 0b000>;
-def : RWSysReg<"GCSPR_EL2", 0b11, 0b100, 0b0010, 0b0101, 0b001>;
-def : RWSysReg<"GCSCR_EL12", 0b11, 0b101, 0b0010, 0b0101, 0b000>;
-def : RWSysReg<"GCSPR_EL12", 0b11, 0b101, 0b0010, 0b0101, 0b001>;
-def : RWSysReg<"GCSCR_EL3", 0b11, 0b110, 0b0010, 0b0101, 0b000>;
-def : RWSysReg<"GCSPR_EL3", 0b11, 0b110, 0b0010, 0b0101, 0b001>;
+def : RWSysReg<"GCSCR_EL1", 0b1, 0b000, 0b0010, 0b0101, 0b000>;
+def : RWSysReg<"GCSPR_EL1", 0b1, 0b000, 0b0010, 0b0101, 0b001>;
+def : RWSysReg<"GCSCRE0_EL1", 0b1, 0b000, 0b0010, 0b0101, 0b010>;
+def : RWSysReg<"GCSPR_EL0", 0b1, 0b011, 0b0010, 0b0101, 0b001>;
+def : RWSysReg<"GCSCR_EL2", 0b1, 0b100, 0b0010, 0b0101, 0b000>;
+def : RWSysReg<"GCSPR_EL2", 0b1, 0b100, 0b0010, 0b0101, 0b001>;
+def : RWSysReg<"GCSCR_EL12", 0b1, 0b101, 0b0010, 0b0101, 0b000>;
+def : RWSysReg<"GCSPR_EL12", 0b1, 0b101, 0b0010, 0b0101, 0b001>;
+def : RWSysReg<"GCSCR_EL3", 0b1, 0b110, 0b0010, 0b0101, 0b000>;
+def : RWSysReg<"GCSPR_EL3", 0b1, 0b110, 0b0010, 0b0101, 0b001>;
// v8.9a/v9.4a Memory Attribute Index Enhancement (FEAT_AIE)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"AMAIR2_EL1", 0b11, 0b000, 0b1010, 0b0011, 0b001>;
-def : RWSysReg<"AMAIR2_EL12", 0b11, 0b101, 0b1010, 0b0011, 0b001>;
-def : RWSysReg<"AMAIR2_EL2", 0b11, 0b100, 0b1010, 0b0011, 0b001>;
-def : RWSysReg<"AMAIR2_EL3", 0b11, 0b110, 0b1010, 0b0011, 0b001>;
-def : RWSysReg<"MAIR2_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b001>;
-def : RWSysReg<"MAIR2_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b001>;
-def : RWSysReg<"MAIR2_EL2", 0b11, 0b100, 0b1010, 0b0001, 0b001>;
-def : RWSysReg<"MAIR2_EL3", 0b11, 0b110, 0b1010, 0b0001, 0b001>;
+def : RWSysReg<"AMAIR2_EL1", 0b1, 0b000, 0b1010, 0b0011, 0b001>;
+def : RWSysReg<"AMAIR2_EL12", 0b1, 0b101, 0b1010, 0b0011, 0b001>;
+def : RWSysReg<"AMAIR2_EL2", 0b1, 0b100, 0b1010, 0b0011, 0b001>;
+def : RWSysReg<"AMAIR2_EL3", 0b1, 0b110, 0b1010, 0b0011, 0b001>;
+def : RWSysReg<"MAIR2_EL1", 0b1, 0b000, 0b1010, 0b0010, 0b001>;
+def : RWSysReg<"MAIR2_EL12", 0b1, 0b101, 0b1010, 0b0010, 0b001>;
+def : RWSysReg<"MAIR2_EL2", 0b1, 0b100, 0b1010, 0b0001, 0b001>;
+def : RWSysReg<"MAIR2_EL3", 0b1, 0b110, 0b1010, 0b0001, 0b001>;
// v8.9a/9.4a Stage 1 Permission Indirection Extension (FEAT_S1PIE)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"PIRE0_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b010>;
-def : RWSysReg<"PIRE0_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b010>;
-def : RWSysReg<"PIRE0_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b010>;
-def : RWSysReg<"PIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b011>;
-def : RWSysReg<"PIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b011>;
-def : RWSysReg<"PIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b011>;
-def : RWSysReg<"PIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b011>;
+def : RWSysReg<"PIRE0_EL1", 0b1, 0b000, 0b1010, 0b0010, 0b010>;
+def : RWSysReg<"PIRE0_EL12", 0b1, 0b101, 0b1010, 0b0010, 0b010>;
+def : RWSysReg<"PIRE0_EL2", 0b1, 0b100, 0b1010, 0b0010, 0b010>;
+def : RWSysReg<"PIR_EL1", 0b1, 0b000, 0b1010, 0b0010, 0b011>;
+def : RWSysReg<"PIR_EL12", 0b1, 0b101, 0b1010, 0b0010, 0b011>;
+def : RWSysReg<"PIR_EL2", 0b1, 0b100, 0b1010, 0b0010, 0b011>;
+def : RWSysReg<"PIR_EL3", 0b1, 0b110, 0b1010, 0b0010, 0b011>;
// v8.9a/v9.4a Stage 2 Permission Indirection Extension (FEAT_S2PIE)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"S2PIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b101>;
+def : RWSysReg<"S2PIR_EL2", 0b1, 0b100, 0b1010, 0b0010, 0b101>;
// v8.9a/v9.4a Stage 1 Permission Overlay Extension (FEAT_S1POE)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"POR_EL0", 0b11, 0b011, 0b1010, 0b0010, 0b100>;
-def : RWSysReg<"POR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b100>;
-def : RWSysReg<"POR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b100>;
-def : RWSysReg<"POR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b100>;
-def : RWSysReg<"POR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b100>;
+def : RWSysReg<"POR_EL0", 0b1, 0b011, 0b1010, 0b0010, 0b100>;
+def : RWSysReg<"POR_EL1", 0b1, 0b000, 0b1010, 0b0010, 0b100>;
+def : RWSysReg<"POR_EL12", 0b1, 0b101, 0b1010, 0b0010, 0b100>;
+def : RWSysReg<"POR_EL2", 0b1, 0b100, 0b1010, 0b0010, 0b100>;
+def : RWSysReg<"POR_EL3", 0b1, 0b110, 0b1010, 0b0010, 0b100>;
// v8.9a/v9.4a Stage 2 Permission Overlay Extension (FEAT_S2POE)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"S2POR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b101>;
+def : RWSysReg<"S2POR_EL1", 0b1, 0b000, 0b1010, 0b0010, 0b101>;
// v8.9a/v9.4a Extension to System Control Registers (FEAT_SCTLR2)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"SCTLR2_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b011>;
-def : RWSysReg<"SCTLR2_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b011>;
-def : RWSysReg<"SCTLR2_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b011>;
-def : RWSysReg<"SCTLR2_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b011>;
+def : RWSysReg<"SCTLR2_EL1", 0b1, 0b000, 0b0001, 0b0000, 0b011>;
+def : RWSysReg<"SCTLR2_EL12", 0b1, 0b101, 0b0001, 0b0000, 0b011>;
+def : RWSysReg<"SCTLR2_EL2", 0b1, 0b100, 0b0001, 0b0000, 0b011>;
+def : RWSysReg<"SCTLR2_EL3", 0b1, 0b110, 0b0001, 0b0000, 0b011>;
// v8.9a/v9.4a Extension to Translation Control Registers (FEAT_TCR2)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"TCR2_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b011>;
-def : RWSysReg<"TCR2_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b011>;
-def : RWSysReg<"TCR2_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b011>;
+def : RWSysReg<"TCR2_EL1", 0b1, 0b000, 0b0010, 0b0000, 0b011>;
+def : RWSysReg<"TCR2_EL12", 0b1, 0b101, 0b0010, 0b0000, 0b011>;
+def : RWSysReg<"TCR2_EL2", 0b1, 0b100, 0b0010, 0b0000, 0b011>;
// v8.9a/9.4a Translation Hardening Extension (FEAT_THE)
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureTHE} }] in {
-def : RWSysReg<"RCWMASK_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b110>;
-def : RWSysReg<"RCWSMASK_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b011>;
+def : RWSysReg<"RCWMASK_EL1", 0b1, 0b000, 0b1101, 0b0000, 0b110>;
+def : RWSysReg<"RCWSMASK_EL1", 0b1, 0b000, 0b1101, 0b0000, 0b011>;
}
// v8.9a/9.4a new Debug feature (FEAT_DEBUGv8p9)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"MDSELR_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b010>;
+def : RWSysReg<"MDSELR_EL1", 0b0, 0b000, 0b0000, 0b0100, 0b010>;
// v8.9a/9.4a new Performance Monitors Extension (FEAT_PMUv3p9)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"PMUACR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b100>;
+def : RWSysReg<"PMUACR_EL1", 0b1, 0b000, 0b1001, 0b1110, 0b100>;
// v8.9a/9.4a PMU Snapshot Extension (FEAT_PMUv3_SS)
// Op0 Op1 CRn CRm Op2
-def : ROSysReg<"PMCCNTSVR_EL1", 0b10, 0b000, 0b1110, 0b1011, 0b111>;
-def : ROSysReg<"PMICNTSVR_EL1", 0b10, 0b000, 0b1110, 0b1100, 0b000>;
-def : RWSysReg<"PMSSCR_EL1", 0b11, 0b000, 0b1001, 0b1101, 0b011>;
+def : ROSysReg<"PMCCNTSVR_EL1", 0b0, 0b000, 0b1110, 0b1011, 0b111>;
+def : ROSysReg<"PMICNTSVR_EL1", 0b0, 0b000, 0b1110, 0b1100, 0b000>;
+def : RWSysReg<"PMSSCR_EL1", 0b1, 0b000, 0b1001, 0b1101, 0b011>;
foreach n = 0-30 in {
defvar nb = !cast<bits<5>>(n);
- def : ROSysReg<"PMEVCNTSVR"#n#"_EL1", 0b10, 0b000, 0b1110, {0b10,nb{4-3}}, nb{2-0}>;
+ def : ROSysReg<"PMEVCNTSVR"#n#"_EL1", 0b0, 0b000, 0b1110, {0b10,nb{4-3}}, nb{2-0}>;
}
// v8.9a/v9.4a PMUv3 Fixed-function instruction counter (FEAT_PMUv3_ICNTR)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"PMICNTR_EL0", 0b11, 0b011, 0b1001, 0b0100, 0b000>;
-def : RWSysReg<"PMICFILTR_EL0", 0b11, 0b011, 0b1001, 0b0110, 0b000>;
+def : RWSysReg<"PMICNTR_EL0", 0b1, 0b011, 0b1001, 0b0100, 0b000>;
+def : RWSysReg<"PMICFILTR_EL0", 0b1, 0b011, 0b1001, 0b0110, 0b000>;
// v8.9a/v9.4a PMUv3 Performance Monitors Zero with Mask (FEAT_PMUv3p9/FEAT_PMUv3_ICNTR)
// Op0 Op1 CRn CRm Op2
-def : WOSysReg<"PMZR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b100>;
+def : WOSysReg<"PMZR_EL0", 0b1, 0b011, 0b1001, 0b1101, 0b100>;
// v8.9a/9.4a Synchronous-Exception-Based Event Profiling extension (FEAT_SEBEP)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"PMECR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b101>;
-def : RWSysReg<"PMIAR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b111>;
+def : RWSysReg<"PMECR_EL1", 0b1, 0b000, 0b1001, 0b1110, 0b101>;
+def : RWSysReg<"PMIAR_EL1", 0b1, 0b000, 0b1001, 0b1110, 0b111>;
// v8.9a/9.4a System Performance Monitors Extension (FEAT_SPMU)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"SPMACCESSR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b011>;
-def : RWSysReg<"SPMACCESSR_EL12", 0b10, 0b101, 0b1001, 0b1101, 0b011>;
-def : RWSysReg<"SPMACCESSR_EL2", 0b10, 0b100, 0b1001, 0b1101, 0b011>;
-def : RWSysReg<"SPMACCESSR_EL3", 0b10, 0b110, 0b1001, 0b1101, 0b011>;
-def : RWSysReg<"SPMCNTENCLR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b010>;
-def : RWSysReg<"SPMCNTENSET_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b001>;
-def : RWSysReg<"SPMCR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b000>;
-def : ROSysReg<"SPMDEVAFF_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b110>;
-def : ROSysReg<"SPMDEVARCH_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b101>;
+def : RWSysReg<"SPMACCESSR_EL1", 0b0, 0b000, 0b1001, 0b1101, 0b011>;
+def : RWSysReg<"SPMACCESSR_EL12", 0b0, 0b101, 0b1001, 0b1101, 0b011>;
+def : RWSysReg<"SPMACCESSR_EL2", 0b0, 0b100, 0b1001, 0b1101, 0b011>;
+def : RWSysReg<"SPMACCESSR_EL3", 0b0, 0b110, 0b1001, 0b1101, 0b011>;
+def : RWSysReg<"SPMCNTENCLR_EL0", 0b0, 0b011, 0b1001, 0b1100, 0b010>;
+def : RWSysReg<"SPMCNTENSET_EL0", 0b0, 0b011, 0b1001, 0b1100, 0b001>;
+def : RWSysReg<"SPMCR_EL0", 0b0, 0b011, 0b1001, 0b1100, 0b000>;
+def : ROSysReg<"SPMDEVAFF_EL1", 0b0, 0b000, 0b1001, 0b1101, 0b110>;
+def : ROSysReg<"SPMDEVARCH_EL1", 0b0, 0b000, 0b1001, 0b1101, 0b101>;
foreach n = 0-15 in {
defvar nb = !cast<bits<4>>(n);
// Op0 Op1 CRn CRm Op2
- def : RWSysReg<"SPMEVCNTR"#n#"_EL0", 0b10, 0b011, 0b1110, {0b000,nb{3}}, nb{2-0}>;
- def : RWSysReg<"SPMEVFILT2R"#n#"_EL0", 0b10, 0b011, 0b1110, {0b011,nb{3}}, nb{2-0}>;
- def : RWSysReg<"SPMEVFILTR"#n#"_EL0", 0b10, 0b011, 0b1110, {0b010,nb{3}}, nb{2-0}>;
- def : RWSysReg<"SPMEVTYPER"#n#"_EL0", 0b10, 0b011, 0b1110, {0b001,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"SPMEVCNTR"#n#"_EL0", 0b0, 0b011, 0b1110, {0b000,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"SPMEVFILT2R"#n#"_EL0", 0b0, 0b011, 0b1110, {0b011,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"SPMEVFILTR"#n#"_EL0", 0b0, 0b011, 0b1110, {0b010,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"SPMEVTYPER"#n#"_EL0", 0b0, 0b011, 0b1110, {0b001,nb{3}}, nb{2-0}>;
}
// Op0 Op1 CRn CRm Op2
-def : ROSysReg<"SPMIIDR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b100>;
-def : RWSysReg<"SPMINTENCLR_EL1", 0b10, 0b000, 0b1001, 0b1110, 0b010>;
-def : RWSysReg<"SPMINTENSET_EL1", 0b10, 0b000, 0b1001, 0b1110, 0b001>;
-def : RWSysReg<"SPMOVSCLR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b011>;
-def : RWSysReg<"SPMOVSSET_EL0", 0b10, 0b011, 0b1001, 0b1110, 0b011>;
-def : RWSysReg<"SPMSELR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b101>;
-def : ROSysReg<"SPMCGCR0_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b000>;
-def : ROSysReg<"SPMCGCR1_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b001>;
-def : ROSysReg<"SPMCFGR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b111>;
-def : RWSysReg<"SPMROOTCR_EL3", 0b10, 0b110, 0b1001, 0b1110, 0b111>;
-def : RWSysReg<"SPMSCR_EL1", 0b10, 0b111, 0b1001, 0b1110, 0b111>;
+def : ROSysReg<"SPMIIDR_EL1", 0b0, 0b000, 0b1001, 0b1101, 0b100>;
+def : RWSysReg<"SPMINTENCLR_EL1", 0b0, 0b000, 0b1001, 0b1110, 0b010>;
+def : RWSysReg<"SPMINTENSET_EL1", 0b0, 0b000, 0b1001, 0b1110, 0b001>;
+def : RWSysReg<"SPMOVSCLR_EL0", 0b0, 0b011, 0b1001, 0b1100, 0b011>;
+def : RWSysReg<"SPMOVSSET_EL0", 0b0, 0b011, 0b1001, 0b1110, 0b011>;
+def : RWSysReg<"SPMSELR_EL0", 0b0, 0b011, 0b1001, 0b1100, 0b101>;
+def : ROSysReg<"SPMCGCR0_EL1", 0b0, 0b000, 0b1001, 0b1101, 0b000>;
+def : ROSysReg<"SPMCGCR1_EL1", 0b0, 0b000, 0b1001, 0b1101, 0b001>;
+def : ROSysReg<"SPMCFGR_EL1", 0b0, 0b000, 0b1001, 0b1101, 0b111>;
+def : RWSysReg<"SPMROOTCR_EL3", 0b0, 0b110, 0b1001, 0b1110, 0b111>;
+def : RWSysReg<"SPMSCR_EL1", 0b0, 0b111, 0b1001, 0b1110, 0b111>;
// v8.9a/9.4a Instrumentation Extension (FEAT_ITE)
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureITE} }] in {
-def : RWSysReg<"TRCITEEDCR", 0b10, 0b001, 0b0000, 0b0010, 0b001>;
-def : RWSysReg<"TRCITECR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b011>;
-def : RWSysReg<"TRCITECR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b011>;
-def : RWSysReg<"TRCITECR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b011>;
+def : RWSysReg<"TRCITEEDCR", 0b0, 0b001, 0b0000, 0b0010, 0b001>;
+def : RWSysReg<"TRCITECR_EL1", 0b1, 0b000, 0b0001, 0b0010, 0b011>;
+def : RWSysReg<"TRCITECR_EL12", 0b1, 0b101, 0b0001, 0b0010, 0b011>;
+def : RWSysReg<"TRCITECR_EL2", 0b1, 0b100, 0b0001, 0b0010, 0b011>;
}
// v8.9a/9.4a SPE Data Source Filtering (FEAT_SPE_FDS)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"PMSDSFR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b100>;
+def : RWSysReg<"PMSDSFR_EL1", 0b1, 0b000, 0b1001, 0b1010, 0b100>;
// v8.9a/9.4a RASv2 (FEAT_RASv2)
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureRASv2} }] in
-def : ROSysReg<"ERXGSR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b010>;
+def : ROSysReg<"ERXGSR_EL1", 0b1, 0b000, 0b0101, 0b0011, 0b010>;
// v8.9a/9.4a Physical Fault Address (FEAT_PFAR)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"PFAR_EL1", 0b11, 0b000, 0b0110, 0b0000, 0b101>;
-def : RWSysReg<"PFAR_EL12", 0b11, 0b101, 0b0110, 0b0000, 0b101>;
-def : RWSysReg<"PFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b101>;
+def : RWSysReg<"PFAR_EL1", 0b1, 0b000, 0b0110, 0b0000, 0b101>;
+def : RWSysReg<"PFAR_EL12", 0b1, 0b101, 0b0110, 0b0000, 0b101>;
+def : RWSysReg<"PFAR_EL2", 0b1, 0b100, 0b0110, 0b0000, 0b101>;
// v9.4a Exception-based event profiling (FEAT_EBEP)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"PM", 0b11, 0b000, 0b0100, 0b0011, 0b001>;
+def : RWSysReg<"PM", 0b1, 0b000, 0b0100, 0b0011, 0b001>;
// 2023 ISA Extension
// AArch64 Floating-point Mode Register controls behaviors of the FP8
// instructions (FEAT_FPMR)
// Op0 Op1 CRn CRm Op2
-def : ROSysReg<"ID_AA64FPFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b111>;
-def : RWSysReg<"FPMR", 0b11, 0b011, 0b0100, 0b0100, 0b010>;
+def : ROSysReg<"ID_AA64FPFR0_EL1", 0b1, 0b000, 0b0000, 0b0100, 0b111>;
+def : RWSysReg<"FPMR", 0b1, 0b011, 0b0100, 0b0100, 0b010>;
// v9.5a Software Stepping Enhancements (FEAT_STEP2)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"MDSTEPOP_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b010>;
+def : RWSysReg<"MDSTEPOP_EL1", 0b0, 0b000, 0b0000, 0b0101, 0b010>;
// v9.5a System PMU zero register (FEAT_SPMU2)
// Op0 Op1 CRn CRm Op2
-def : WOSysReg<"SPMZR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b100>;
+def : WOSysReg<"SPMZR_EL0", 0b0, 0b011, 0b1001, 0b1100, 0b100>;
// v9.5a Delegated SError exceptions for EL3 (FEAT_E3DSE)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"VDISR_EL3", 0b11, 0b110, 0b1100, 0b0001, 0b001>;
-def : RWSysReg<"VSESR_EL3", 0b11, 0b110, 0b0101, 0b0010, 0b011>;
+def : RWSysReg<"VDISR_EL3", 0b1, 0b110, 0b1100, 0b0001, 0b001>;
+def : RWSysReg<"VSESR_EL3", 0b1, 0b110, 0b0101, 0b0010, 0b011>;
// v9.5a Hardware Dirty State Tracking Structure (FEAT_HDBSS)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"HDBSSBR_EL2", 0b11, 0b100, 0b0010, 0b0011, 0b010>;
-def : RWSysReg<"HDBSSPROD_EL2", 0b11, 0b100, 0b0010, 0b0011, 0b011>;
+def : RWSysReg<"HDBSSBR_EL2", 0b1, 0b100, 0b0010, 0b0011, 0b010>;
+def : RWSysReg<"HDBSSPROD_EL2", 0b1, 0b100, 0b0010, 0b0011, 0b011>;
// v9.5a Hardware Accelerator for Cleaning Dirty State (FEAT_HACDBS)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"HACDBSBR_EL2", 0b11, 0b100, 0b0010, 0b0011, 0b100>;
-def : RWSysReg<"HACDBSCONS_EL2", 0b11, 0b100, 0b0010, 0b0011, 0b101>;
+def : RWSysReg<"HACDBSBR_EL2", 0b1, 0b100, 0b0010, 0b0011, 0b100>;
+def : RWSysReg<"HACDBSCONS_EL2", 0b1, 0b100, 0b0010, 0b0011, 0b101>;
// v9.5a Fine Grained Write Trap EL3 (FEAT_FGWTE3)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"FGWTE3_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b101>;
+def : RWSysReg<"FGWTE3_EL3", 0b1, 0b110, 0b0001, 0b0001, 0b101>;
// v9.6a Memory partitioning and monitoring (FEAT_MPAM) registers
// Op0 Op1 CRn CRm Op2
-def : ROSysReg<"MPAMBWIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b101>;
-def : RWSysReg<"MPAMBW3_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b100>;
-def : RWSysReg<"MPAMBW2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b100>;
-def : RWSysReg<"MPAMBW1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b100>;
-def : RWSysReg<"MPAMBW1_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b100>;
-def : RWSysReg<"MPAMBW0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b101>;
-def : RWSysReg<"MPAMBWCAP_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b110>;
-def : RWSysReg<"MPAMBWSM_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b111>;
+def : ROSysReg<"MPAMBWIDR_EL1", 0b1, 0b000, 0b1010, 0b0100, 0b101>;
+def : RWSysReg<"MPAMBW3_EL3", 0b1, 0b110, 0b1010, 0b0101, 0b100>;
+def : RWSysReg<"MPAMBW2_EL2", 0b1, 0b100, 0b1010, 0b0101, 0b100>;
+def : RWSysReg<"MPAMBW1_EL1", 0b1, 0b000, 0b1010, 0b0101, 0b100>;
+def : RWSysReg<"MPAMBW1_EL12", 0b1, 0b101, 0b1010, 0b0101, 0b100>;
+def : RWSysReg<"MPAMBW0_EL1", 0b1, 0b000, 0b1010, 0b0101, 0b101>;
+def : RWSysReg<"MPAMBWCAP_EL2", 0b1, 0b100, 0b1010, 0b0101, 0b110>;
+def : RWSysReg<"MPAMBWSM_EL1", 0b1, 0b000, 0b1010, 0b0101, 0b111>;
// v9.7a Memory partitioning and monitoring version 2
// (FEAT_MPAMv2) registers
// Op0 Op1 CRn CRm Op2
// MPAM system registers that are also available for MPAMv2
-def : RWSysReg<"MPAM0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b001>;
-def : RWSysReg<"MPAM1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b000>;
-def : RWSysReg<"MPAM1_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b000>;
-def : RWSysReg<"MPAM2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b000>;
-def : RWSysReg<"MPAM3_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b000>;
-def : RWSysReg<"MPAMHCR_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b000>;
-def : ROSysReg<"MPAMIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b100>;
+def : RWSysReg<"MPAM0_EL1", 0b1, 0b000, 0b1010, 0b0101, 0b001>;
+def : RWSysReg<"MPAM1_EL1", 0b1, 0b000, 0b1010, 0b0101, 0b000>;
+def : RWSysReg<"MPAM1_EL12", 0b1, 0b101, 0b1010, 0b0101, 0b000>;
+def : RWSysReg<"MPAM2_EL2", 0b1, 0b100, 0b1010, 0b0101, 0b000>;
+def : RWSysReg<"MPAM3_EL3", 0b1, 0b110, 0b1010, 0b0101, 0b000>;
+def : RWSysReg<"MPAMHCR_EL2", 0b1, 0b100, 0b1010, 0b0100, 0b000>;
+def : ROSysReg<"MPAMIDR_EL1", 0b1, 0b000, 0b1010, 0b0100, 0b100>;
// Only MPAMv2 registers
-def : RWSysReg<"MPAMCTL_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b010>;
-def : RWSysReg<"MPAMCTL_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b010>;
-def : RWSysReg<"MPAMCTL_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b010>;
-def : RWSysReg<"MPAMCTL_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b010>;
-def : RWSysReg<"MPAMVIDCR_EL2", 0b11, 0b100, 0b1010, 0b0111, 0b000>;
-def : RWSysReg<"MPAMVIDSR_EL2", 0b11, 0b100, 0b1010, 0b0111, 0b001>;
-def : RWSysReg<"MPAMVIDSR_EL3", 0b11, 0b110, 0b1010, 0b0111, 0b001>;
+def : RWSysReg<"MPAMCTL_EL1", 0b1, 0b000, 0b1010, 0b0101, 0b010>;
+def : RWSysReg<"MPAMCTL_EL12", 0b1, 0b101, 0b1010, 0b0101, 0b010>;
+def : RWSysReg<"MPAMCTL_EL2", 0b1, 0b100, 0b1010, 0b0101, 0b010>;
+def : RWSysReg<"MPAMCTL_EL3", 0b1, 0b110, 0b1010, 0b0101, 0b010>;
+def : RWSysReg<"MPAMVIDCR_EL2", 0b1, 0b100, 0b1010, 0b0111, 0b000>;
+def : RWSysReg<"MPAMVIDSR_EL2", 0b1, 0b100, 0b1010, 0b0111, 0b001>;
+def : RWSysReg<"MPAMVIDSR_EL3", 0b1, 0b110, 0b1010, 0b0111, 0b001>;
// v9.7a General Improvements
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"SCR2_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b010>;
+def : RWSysReg<"SCR2_EL3", 0b1, 0b110, 0b0001, 0b0010, 0b010>;
//===----------------------------------------------------------------------===//
// FEAT_SRMASK v9.6a registers
//===----------------------------------------------------------------------===//
-def : RWSysReg<"SCTLRMASK_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b000>;
-def : RWSysReg<"SCTLRMASK_EL2", 0b11, 0b100, 0b0001, 0b0100, 0b000>;
-def : RWSysReg<"SCTLRMASK_EL12", 0b11, 0b101, 0b0001, 0b0100, 0b000>;
-def : RWSysReg<"CPACRMASK_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b010>;
-def : RWSysReg<"CPTRMASK_EL2", 0b11, 0b100, 0b0001, 0b0100, 0b010>;
-def : RWSysReg<"CPACRMASK_EL12", 0b11, 0b101, 0b0001, 0b0100, 0b010>;
-def : RWSysReg<"SCTLR2MASK_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b011>;
-def : RWSysReg<"SCTLR2MASK_EL2", 0b11, 0b100, 0b0001, 0b0100, 0b011>;
-def : RWSysReg<"SCTLR2MASK_EL12", 0b11, 0b101, 0b0001, 0b0100, 0b011>;
-def : RWSysReg<"CPACRALIAS_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b100>;
-def : RWSysReg<"SCTLRALIAS_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b110>;
-def : RWSysReg<"SCTLR2ALIAS_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b111>;
-def : RWSysReg<"TCRMASK_EL1", 0b11, 0b000, 0b0010, 0b0111, 0b010>;
-def : RWSysReg<"TCRMASK_EL2", 0b11, 0b100, 0b0010, 0b0111, 0b010>;
-def : RWSysReg<"TCRMASK_EL12", 0b11, 0b101, 0b0010, 0b0111, 0b010>;
-def : RWSysReg<"TCR2MASK_EL1", 0b11, 0b000, 0b0010, 0b0111, 0b011>;
-def : RWSysReg<"TCR2MASK_EL2", 0b11, 0b100, 0b0010, 0b0111, 0b011>;
-def : RWSysReg<"TCR2MASK_EL12", 0b11, 0b101, 0b0010, 0b0111, 0b011>;
-def : RWSysReg<"TCRALIAS_EL1", 0b11, 0b000, 0b0010, 0b0111, 0b110>;
-def : RWSysReg<"TCR2ALIAS_EL1", 0b11, 0b000, 0b0010, 0b0111, 0b111>;
-def : RWSysReg<"ACTLRMASK_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b001>;
-def : RWSysReg<"ACTLRMASK_EL2", 0b11, 0b100, 0b0001, 0b0100, 0b001>;
-def : RWSysReg<"ACTLRMASK_EL12", 0b11, 0b101, 0b0001, 0b0100, 0b001>;
-def : RWSysReg<"ACTLRALIAS_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b101>;
+def : RWSysReg<"SCTLRMASK_EL1", 0b1, 0b000, 0b0001, 0b0100, 0b000>;
+def : RWSysReg<"SCTLRMASK_EL2", 0b1, 0b100, 0b0001, 0b0100, 0b000>;
+def : RWSysReg<"SCTLRMASK_EL12", 0b1, 0b101, 0b0001, 0b0100, 0b000>;
+def : RWSysReg<"CPACRMASK_EL1", 0b1, 0b000, 0b0001, 0b0100, 0b010>;
+def : RWSysReg<"CPTRMASK_EL2", 0b1, 0b100, 0b0001, 0b0100, 0b010>;
+def : RWSysReg<"CPACRMASK_EL12", 0b1, 0b101, 0b0001, 0b0100, 0b010>;
+def : RWSysReg<"SCTLR2MASK_EL1", 0b1, 0b000, 0b0001, 0b0100, 0b011>;
+def : RWSysReg<"SCTLR2MASK_EL2", 0b1, 0b100, 0b0001, 0b0100, 0b011>;
+def : RWSysReg<"SCTLR2MASK_EL12", 0b1, 0b101, 0b0001, 0b0100, 0b011>;
+def : RWSysReg<"CPACRALIAS_EL1", 0b1, 0b000, 0b0001, 0b0100, 0b100>;
+def : RWSysReg<"SCTLRALIAS_EL1", 0b1, 0b000, 0b0001, 0b0100, 0b110>;
+def : RWSysReg<"SCTLR2ALIAS_EL1", 0b1, 0b000, 0b0001, 0b0100, 0b111>;
+def : RWSysReg<"TCRMASK_EL1", 0b1, 0b000, 0b0010, 0b0111, 0b010>;
+def : RWSysReg<"TCRMASK_EL2", 0b1, 0b100, 0b0010, 0b0111, 0b010>;
+def : RWSysReg<"TCRMASK_EL12", 0b1, 0b101, 0b0010, 0b0111, 0b010>;
+def : RWSysReg<"TCR2MASK_EL1", 0b1, 0b000, 0b0010, 0b0111, 0b011>;
+def : RWSysReg<"TCR2MASK_EL2", 0b1, 0b100, 0b0010, 0b0111, 0b011>;
+def : RWSysReg<"TCR2MASK_EL12", 0b1, 0b101, 0b0010, 0b0111, 0b011>;
+def : RWSysReg<"TCRALIAS_EL1", 0b1, 0b000, 0b0010, 0b0111, 0b110>;
+def : RWSysReg<"TCR2ALIAS_EL1", 0b1, 0b000, 0b0010, 0b0111, 0b111>;
+def : RWSysReg<"ACTLRMASK_EL1", 0b1, 0b000, 0b0001, 0b0100, 0b001>;
+def : RWSysReg<"ACTLRMASK_EL2", 0b1, 0b100, 0b0001, 0b0100, 0b001>;
+def : RWSysReg<"ACTLRMASK_EL12", 0b1, 0b101, 0b0001, 0b0100, 0b001>;
+def : RWSysReg<"ACTLRALIAS_EL1", 0b1, 0b000, 0b0001, 0b0100, 0b101>;
//===----------------------------------------------------------------------===//
// v9.6a PCDPHINT instruction options.
@@ -2445,20 +2445,20 @@ def KEEP : PHint<0b00, 0b000, 0b0000, 0b0000, 0b000, "keep">;
def STRM : PHint<0b00, 0b000, 0b0000, 0b0000, 0b001, "strm">;
// v9.6a Realm management extension enhancements
-def : RWSysReg<"GPCBW_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b101>;
+def : RWSysReg<"GPCBW_EL3", 0b1, 0b110, 0b0010, 0b0001, 0b101>;
// v9.6a Statistical Profiling Extension exception registers (FEAT_SPE_EXC)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"PMBMAR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b101>;
-def : RWSysReg<"PMBSR_EL12", 0b11, 0b101, 0b1001, 0b1010, 0b011>;
-def : RWSysReg<"PMBSR_EL2", 0b11, 0b100, 0b1001, 0b1010, 0b011>;
-def : RWSysReg<"PMBSR_EL3", 0b11, 0b110, 0b1001, 0b1010, 0b011>;
+def : RWSysReg<"PMBMAR_EL1", 0b1, 0b000, 0b1001, 0b1010, 0b101>;
+def : RWSysReg<"PMBSR_EL12", 0b1, 0b101, 0b1001, 0b1010, 0b011>;
+def : RWSysReg<"PMBSR_EL2", 0b1, 0b100, 0b1001, 0b1010, 0b011>;
+def : RWSysReg<"PMBSR_EL3", 0b1, 0b110, 0b1001, 0b1010, 0b011>;
// v9.6a Trace Buffer Management Events exception registers (FEAT_TRBE_EXC)
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"TRBSR_EL12", 0b11, 0b101, 0b1001, 0b1011, 0b011>;
-def : RWSysReg<"TRBSR_EL2", 0b11, 0b100, 0b1001, 0b1011, 0b011>;
-def : RWSysReg<"TRBSR_EL3", 0b11, 0b110, 0b1001, 0b1011, 0b011>;
+def : RWSysReg<"TRBSR_EL12", 0b1, 0b101, 0b1001, 0b1011, 0b011>;
+def : RWSysReg<"TRBSR_EL2", 0b1, 0b100, 0b1001, 0b1011, 0b011>;
+def : RWSysReg<"TRBSR_EL3", 0b1, 0b110, 0b1001, 0b1011, 0b011>;
// v9.6 FEAT_PoPS
//
@@ -2473,15 +2473,15 @@ def : DC<"CIGDVAPS", 0b000, 0b0111, 0b1111, 0b101>;
// v9.7a TLBI domains system registers (MemSys)
foreach n = 0-3 in {
defvar nb = !cast<bits<3>>(n);
- def : RWSysReg<"VTLBID"#n#"_EL2", 0b11, 0b100, 0b0010, 0b1000, nb>;
+ def : RWSysReg<"VTLBID"#n#"_EL2", 0b1, 0b100, 0b0010, 0b1000, nb>;
}
foreach n = 0-3 in {
defvar nb = !cast<bits<3>>(n);
- def : RWSysReg<"VTLBIDOS"#n#"_EL2", 0b11, 0b100, 0b0010, 0b1001, nb>;
+ def : RWSysReg<"VTLBIDOS"#n#"_EL2", 0b1, 0b100, 0b0010, 0b1001, nb>;
}
-def : ROSysReg<"TLBIDIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b110>;
+def : ROSysReg<"TLBIDIDR_EL1", 0b1, 0b000, 0b1010, 0b0100, 0b110>;
// MPAM Lookaside Buffer Invalidate (MLBI) instructions
class MLBI<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, bit needsreg> {
@@ -2519,39 +2519,39 @@ def : MLBI<"VPMGE1", 0b100, 0b0111, 0b0000, 0b111, 1>;
// v9.7-A GICv5 (FEAT_GCIE)
// CPU Interface Registers
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"ICC_APR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b000>;
-def : RWSysReg<"ICC_APR_EL3", 0b11, 0b110, 0b1100, 0b1000, 0b000>;
-def : RWSysReg<"ICC_CR0_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b001>;
-def : RWSysReg<"ICC_CR0_EL3", 0b11, 0b110, 0b1100, 0b1001, 0b000>;
-def : ROSysReg<"ICC_DOMHPPIR_EL3", 0b11, 0b110, 0b1100, 0b1000, 0b010>;
-def : ROSysReg<"ICC_HAPR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b011>;
-def : ROSysReg<"ICC_HPPIR_EL1", 0b11, 0b000, 0b1100, 0b1010, 0b011>;
-def : ROSysReg<"ICC_HPPIR_EL3", 0b11, 0b110, 0b1100, 0b1001, 0b001>;
-def : ROSysReg<"ICC_IAFFIDR_EL1", 0b11, 0b000, 0b1100, 0b1010, 0b101>;
-def : RWSysReg<"ICC_ICSR_EL1", 0b11, 0b000, 0b1100, 0b1010, 0b100>;
-def : ROSysReg<"ICC_IDR0_EL1", 0b11, 0b000, 0b1100, 0b1010, 0b010>;
-def : RWSysReg<"ICC_PCR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b010>;
-def : RWSysReg<"ICC_PCR_EL3", 0b11, 0b110, 0b1100, 0b1000, 0b001>;
+def : RWSysReg<"ICC_APR_EL1", 0b1, 0b001, 0b1100, 0b0000, 0b000>;
+def : RWSysReg<"ICC_APR_EL3", 0b1, 0b110, 0b1100, 0b1000, 0b000>;
+def : RWSysReg<"ICC_CR0_EL1", 0b1, 0b001, 0b1100, 0b0000, 0b001>;
+def : RWSysReg<"ICC_CR0_EL3", 0b1, 0b110, 0b1100, 0b1001, 0b000>;
+def : ROSysReg<"ICC_DOMHPPIR_EL3", 0b1, 0b110, 0b1100, 0b1000, 0b010>;
+def : ROSysReg<"ICC_HAPR_EL1", 0b1, 0b001, 0b1100, 0b0000, 0b011>;
+def : ROSysReg<"ICC_HPPIR_EL1", 0b1, 0b000, 0b1100, 0b1010, 0b011>;
+def : ROSysReg<"ICC_HPPIR_EL3", 0b1, 0b110, 0b1100, 0b1001, 0b001>;
+def : ROSysReg<"ICC_IAFFIDR_EL1", 0b1, 0b000, 0b1100, 0b1010, 0b101>;
+def : RWSysReg<"ICC_ICSR_EL1", 0b1, 0b000, 0b1100, 0b1010, 0b100>;
+def : ROSysReg<"ICC_IDR0_EL1", 0b1, 0b000, 0b1100, 0b1010, 0b010>;
+def : RWSysReg<"ICC_PCR_EL1", 0b1, 0b001, 0b1100, 0b0000, 0b010>;
+def : RWSysReg<"ICC_PCR_EL3", 0b1, 0b110, 0b1100, 0b1000, 0b001>;
// Virtual CPU Interface Registers
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"ICV_APR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b000>;
-def : RWSysReg<"ICV_CR0_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b001>;
-def : RWSysReg<"ICV_HAPR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b011>;
-def : RWSysReg<"ICV_HPPIR_EL1", 0b11, 0b000, 0b1100, 0b1010, 0b011>;
-def : RWSysReg<"ICV_PCR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b010>;
+def : RWSysReg<"ICV_APR_EL1", 0b1, 0b001, 0b1100, 0b0000, 0b000>;
+def : RWSysReg<"ICV_CR0_EL1", 0b1, 0b001, 0b1100, 0b0000, 0b001>;
+def : RWSysReg<"ICV_HAPR_EL1", 0b1, 0b001, 0b1100, 0b0000, 0b011>;
+def : RWSysReg<"ICV_HPPIR_EL1", 0b1, 0b000, 0b1100, 0b1010, 0b011>;
+def : RWSysReg<"ICV_PCR_EL1", 0b1, 0b001, 0b1100, 0b0000, 0b010>;
foreach n=0-3 in {
defvar nb = !cast<bits<2>>(n);
// Op0 Op1 CRn CRm Op2
- def : RWSysReg<"ICC_PPI_DOMAINR"#n#"_EL3", 0b11, 0b110, 0b1100, 0b1000, {0b1,nb{1-0}}>;
+ def : RWSysReg<"ICC_PPI_DOMAINR"#n#"_EL3", 0b1, 0b110, 0b1100, 0b1000, {0b1,nb{1-0}}>;
}
foreach n=0-15 in{
defvar nb = !cast<bits<4>>(n);
// Op0 Op1 CRn CRm Op2
- def : RWSysReg<"ICC_PPI_PRIORITYR"#n#"_EL1", 0b11, 0b000, 0b1100, {0b111,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"ICC_PPI_PRIORITYR"#n#"_EL1", 0b1, 0b000, 0b1100, {0b111,nb{3}}, nb{2-0}>;
}
// PPI and Virtual PPI Registers
@@ -2559,12 +2559,12 @@ multiclass PPIRegisters<string prefix> {
foreach n=0-1 in {
defvar nb = !cast<bit>(n);
// Op0 Op1 CRn CRm Op2
- def : RWSysReg<prefix#"_PPI_CACTIVER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b00,nb}>;
- def : RWSysReg<prefix#"_PPI_CPENDR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b10,nb}>;
- def : RWSysReg<prefix#"_PPI_ENABLER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1010, {0b11,nb}>;
- def : RWSysReg<prefix#"_PPI_SACTIVER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b01,nb}>;
- def : RWSysReg<prefix#"_PPI_SPENDR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b11,nb}>;
- def : RWSysReg<prefix#"_PPI_HMR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1010, {0b00,nb}>;
+ def : RWSysReg<prefix#"_PPI_CACTIVER"#n#"_EL1", 0b1, 0b000, 0b1100, 0b1101, {0b00,nb}>;
+ def : RWSysReg<prefix#"_PPI_CPENDR"#n#"_EL1", 0b1, 0b000, 0b1100, 0b1101, {0b10,nb}>;
+ def : RWSysReg<prefix#"_PPI_ENABLER"#n#"_EL1", 0b1, 0b000, 0b1100, 0b1010, {0b11,nb}>;
+ def : RWSysReg<prefix#"_PPI_SACTIVER"#n#"_EL1", 0b1, 0b000, 0b1100, 0b1101, {0b01,nb}>;
+ def : RWSysReg<prefix#"_PPI_SPENDR"#n#"_EL1", 0b1, 0b000, 0b1100, 0b1101, {0b11,nb}>;
+ def : RWSysReg<prefix#"_PPI_HMR"#n#"_EL1", 0b1, 0b000, 0b1100, 0b1010, {0b00,nb}>;
}
}
@@ -2574,32 +2574,32 @@ defm : PPIRegisters<"ICV">; // Virtual PPI Registers
foreach n=0-15 in {
defvar nb = !cast<bits<4>>(n);
// Op0 Op1 CRn CRm Op2
- def : RWSysReg<"ICV_PPI_PRIORITYR"#n#"_EL1", 0b11, 0b000, 0b1100, {0b111,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"ICV_PPI_PRIORITYR"#n#"_EL1", 0b1, 0b000, 0b1100, {0b111,nb{3}}, nb{2-0}>;
}
// Hypervisor Control Registers
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"ICH_APR_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b100>;
-def : RWSysReg<"ICH_CONTEXTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b110>;
-def : RWSysReg<"ICH_HFGITR_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b111>;
-def : RWSysReg<"ICH_HFGRTR_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b100>;
-def : RWSysReg<"ICH_HFGWTR_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b110>;
-def : ROSysReg<"ICH_HPPIR_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b101>;
-def : RWSysReg<"ICH_VCTLR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b100>;
+def : RWSysReg<"ICH_APR_EL2", 0b1, 0b100, 0b1100, 0b1000, 0b100>;
+def : RWSysReg<"ICH_CONTEXTR_EL2", 0b1, 0b100, 0b1100, 0b1011, 0b110>;
+def : RWSysReg<"ICH_HFGITR_EL2", 0b1, 0b100, 0b1100, 0b1001, 0b111>;
+def : RWSysReg<"ICH_HFGRTR_EL2", 0b1, 0b100, 0b1100, 0b1001, 0b100>;
+def : RWSysReg<"ICH_HFGWTR_EL2", 0b1, 0b100, 0b1100, 0b1001, 0b110>;
+def : ROSysReg<"ICH_HPPIR_EL2", 0b1, 0b100, 0b1100, 0b1000, 0b101>;
+def : RWSysReg<"ICH_VCTLR_EL2", 0b1, 0b100, 0b1100, 0b1011, 0b100>;
foreach n=0-1 in {
defvar nb = !cast<bit>(n);
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"ICH_PPI_ACTIVER"#n#"_EL2", 0b11, 0b100, 0b1100, 0b1010, {0b11,nb}>;
-def : RWSysReg<"ICH_PPI_DVIR"#n#"_EL2", 0b11, 0b100, 0b1100, 0b1010, {0b00,nb}>;
-def : RWSysReg<"ICH_PPI_ENABLER"#n#"_EL2", 0b11, 0b100, 0b1100, 0b1010, {0b01,nb}>;
-def : RWSysReg<"ICH_PPI_PENDR"#n#"_EL2", 0b11, 0b100, 0b1100, 0b1010, {0b10,nb}>;
+def : RWSysReg<"ICH_PPI_ACTIVER"#n#"_EL2", 0b1, 0b100, 0b1100, 0b1010, {0b11,nb}>;
+def : RWSysReg<"ICH_PPI_DVIR"#n#"_EL2", 0b1, 0b100, 0b1100, 0b1010, {0b00,nb}>;
+def : RWSysReg<"ICH_PPI_ENABLER"#n#"_EL2", 0b1, 0b100, 0b1100, 0b1010, {0b01,nb}>;
+def : RWSysReg<"ICH_PPI_PENDR"#n#"_EL2", 0b1, 0b100, 0b1100, 0b1010, {0b10,nb}>;
}
foreach n=0-15 in {
defvar nb = !cast<bits<4>>(n);
// Op0 Op1 CRn CRm Op2
- def : RWSysReg<"ICH_PPI_PRIORITYR"#n#"_EL2", 0b11, 0b100, 0b1100, {0b111,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"ICH_PPI_PRIORITYR"#n#"_EL2", 0b1, 0b100, 0b1100, {0b111,nb{3}}, nb{2-0}>;
}
//===----------------------------------------------------------------------===//
@@ -2721,109 +2721,109 @@ def : GIC<"ldrcfg", 0b110, 0b1100, 0b0001, 0b101>;
// Stage 1 Permission Overlays Extension 2 (FEAT_S1POE2).
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"DPOTBR0_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b110>;
-def : RWSysReg<"DPOTBR0_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b110>;
-def : RWSysReg<"DPOTBR1_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b111>;
-def : RWSysReg<"DPOTBR1_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b111>;
-def : RWSysReg<"DPOTBR0_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b110>;
-def : RWSysReg<"DPOTBR1_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b111>;
-def : RWSysReg<"DPOTBR0_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b110>;
+def : RWSysReg<"DPOTBR0_EL1", 0b1, 0b000, 0b0010, 0b0000, 0b110>;
+def : RWSysReg<"DPOTBR0_EL12", 0b1, 0b101, 0b0010, 0b0000, 0b110>;
+def : RWSysReg<"DPOTBR1_EL1", 0b1, 0b000, 0b0010, 0b0000, 0b111>;
+def : RWSysReg<"DPOTBR1_EL12", 0b1, 0b101, 0b0010, 0b0000, 0b111>;
+def : RWSysReg<"DPOTBR0_EL2", 0b1, 0b100, 0b0010, 0b0000, 0b110>;
+def : RWSysReg<"DPOTBR1_EL2", 0b1, 0b100, 0b0010, 0b0000, 0b111>;
+def : RWSysReg<"DPOTBR0_EL3", 0b1, 0b110, 0b0010, 0b0000, 0b110>;
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"IRTBRU_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b100>;
-def : RWSysReg<"IRTBRU_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b100>;
-def : RWSysReg<"IRTBRP_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b101>;
-def : RWSysReg<"IRTBRP_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b101>;
-def : RWSysReg<"IRTBRU_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b100>;
-def : RWSysReg<"IRTBRP_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b101>;
-def : RWSysReg<"IRTBRP_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b101>;
+def : RWSysReg<"IRTBRU_EL1", 0b1, 0b000, 0b0010, 0b0000, 0b100>;
+def : RWSysReg<"IRTBRU_EL12", 0b1, 0b101, 0b0010, 0b0000, 0b100>;
+def : RWSysReg<"IRTBRP_EL1", 0b1, 0b000, 0b0010, 0b0000, 0b101>;
+def : RWSysReg<"IRTBRP_EL12", 0b1, 0b101, 0b0010, 0b0000, 0b101>;
+def : RWSysReg<"IRTBRU_EL2", 0b1, 0b100, 0b0010, 0b0000, 0b100>;
+def : RWSysReg<"IRTBRP_EL2", 0b1, 0b100, 0b0010, 0b0000, 0b101>;
+def : RWSysReg<"IRTBRP_EL3", 0b1, 0b110, 0b0010, 0b0000, 0b101>;
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"TTTBRU_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b110>;
-def : RWSysReg<"TTTBRU_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b110>;
-def : RWSysReg<"TTTBRP_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b111>;
-def : RWSysReg<"TTTBRP_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b111>;
-def : RWSysReg<"TTTBRU_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b110>;
-def : RWSysReg<"TTTBRP_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b111>;
-def : RWSysReg<"TTTBRP_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b111>;
+def : RWSysReg<"TTTBRU_EL1", 0b1, 0b000, 0b1010, 0b0010, 0b110>;
+def : RWSysReg<"TTTBRU_EL12", 0b1, 0b101, 0b1010, 0b0010, 0b110>;
+def : RWSysReg<"TTTBRP_EL1", 0b1, 0b000, 0b1010, 0b0010, 0b111>;
+def : RWSysReg<"TTTBRP_EL12", 0b1, 0b101, 0b1010, 0b0010, 0b111>;
+def : RWSysReg<"TTTBRU_EL2", 0b1, 0b100, 0b1010, 0b0010, 0b110>;
+def : RWSysReg<"TTTBRP_EL2", 0b1, 0b100, 0b1010, 0b0010, 0b111>;
+def : RWSysReg<"TTTBRP_EL3", 0b1, 0b110, 0b1010, 0b0010, 0b111>;
foreach n = 0-15 in {
defvar nb = !cast<bits<4>>(n);
// Op0 Op1 CRn CRm Op2
- def : RWSysReg<"FGDTP"#n#"_EL1", 0b11, 0b000, 0b0011, {0b001,nb{3}}, nb{2-0}>;
- def : RWSysReg<"FGDTP"#n#"_EL2", 0b11, 0b100, 0b0011, {0b001,nb{3}}, nb{2-0}>;
- def : RWSysReg<"FGDTP"#n#"_EL12", 0b11, 0b101, 0b0011, {0b001,nb{3}}, nb{2-0}>;
- def : RWSysReg<"FGDTP"#n#"_EL3", 0b11, 0b110, 0b0011, {0b001,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"FGDTP"#n#"_EL1", 0b1, 0b000, 0b0011, {0b001,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"FGDTP"#n#"_EL2", 0b1, 0b100, 0b0011, {0b001,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"FGDTP"#n#"_EL12", 0b1, 0b101, 0b0011, {0b001,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"FGDTP"#n#"_EL3", 0b1, 0b110, 0b0011, {0b001,nb{3}}, nb{2-0}>;
- def : RWSysReg<"FGDTU"#n#"_EL1", 0b11, 0b000, 0b0011, {0b010,nb{3}}, nb{2-0}>;
- def : RWSysReg<"FGDTU"#n#"_EL2", 0b11, 0b100, 0b0011, {0b010,nb{3}}, nb{2-0}>;
- def : RWSysReg<"FGDTU"#n#"_EL12", 0b11, 0b101, 0b0011, {0b010,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"FGDTU"#n#"_EL1", 0b1, 0b000, 0b0011, {0b010,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"FGDTU"#n#"_EL2", 0b1, 0b100, 0b0011, {0b010,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"FGDTU"#n#"_EL12", 0b1, 0b101, 0b0011, {0b010,nb{3}}, nb{2-0}>;
}
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"LDSTT_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b111>;
-def : RWSysReg<"LDSTT_EL12", 0b11, 0b101, 0b0010, 0b0001, 0b111>;
-def : RWSysReg<"LDSTT_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b111>;
+def : RWSysReg<"LDSTT_EL1", 0b1, 0b000, 0b0010, 0b0001, 0b111>;
+def : RWSysReg<"LDSTT_EL12", 0b1, 0b101, 0b0010, 0b0001, 0b111>;
+def : RWSysReg<"LDSTT_EL2", 0b1, 0b100, 0b0010, 0b0001, 0b111>;
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"TINDEX_EL0", 0b11, 0b011, 0b0100, 0b0000, 0b011>;
-def : RWSysReg<"TINDEX_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b011>;
-def : RWSysReg<"TINDEX_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b011>;
-def : RWSysReg<"TINDEX_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b011>;
-def : RWSysReg<"TINDEX_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b011>;
+def : RWSysReg<"TINDEX_EL0", 0b1, 0b011, 0b0100, 0b0000, 0b011>;
+def : RWSysReg<"TINDEX_EL1", 0b1, 0b000, 0b0100, 0b0000, 0b011>;
+def : RWSysReg<"TINDEX_EL2", 0b1, 0b100, 0b0100, 0b0000, 0b011>;
+def : RWSysReg<"TINDEX_EL12", 0b1, 0b101, 0b0100, 0b0000, 0b011>;
+def : RWSysReg<"TINDEX_EL3", 0b1, 0b110, 0b0100, 0b0000, 0b011>;
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"STINDEX_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b010>;
-def : RWSysReg<"STINDEX_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b010>;
-def : RWSysReg<"STINDEX_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b010>;
-def : RWSysReg<"STINDEX_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b010>;
+def : RWSysReg<"STINDEX_EL1", 0b1, 0b000, 0b0100, 0b0000, 0b010>;
+def : RWSysReg<"STINDEX_EL2", 0b1, 0b100, 0b0100, 0b0000, 0b010>;
+def : RWSysReg<"STINDEX_EL12", 0b1, 0b101, 0b0100, 0b0000, 0b010>;
+def : RWSysReg<"STINDEX_EL3", 0b1, 0b110, 0b0100, 0b0000, 0b010>;
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"TPIDR3_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b000>;
-def : RWSysReg<"TPIDR3_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b000>;
-def : RWSysReg<"TPIDR3_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b000>;
-def : RWSysReg<"TPIDR3_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b000>;
-def : RWSysReg<"TPIDR3_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b000>;
+def : RWSysReg<"TPIDR3_EL0", 0b1, 0b011, 0b1101, 0b0000, 0b000>;
+def : RWSysReg<"TPIDR3_EL1", 0b1, 0b000, 0b1101, 0b0000, 0b000>;
+def : RWSysReg<"TPIDR3_EL12", 0b1, 0b101, 0b1101, 0b0000, 0b000>;
+def : RWSysReg<"TPIDR3_EL2", 0b1, 0b100, 0b1101, 0b0000, 0b000>;
+def : RWSysReg<"TPIDR3_EL3", 0b1, 0b110, 0b1101, 0b0000, 0b000>;
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"VNCCR_EL2", 0b11, 0b100, 0b0010, 0b0010, 0b001>;
+def : RWSysReg<"VNCCR_EL2", 0b1, 0b100, 0b0010, 0b0010, 0b001>;
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"DPOCR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b010>;
+def : RWSysReg<"DPOCR_EL0", 0b1, 0b011, 0b0100, 0b0101, 0b010>;
foreach n = 0-15 in {
defvar nb = !cast<bits<4>>(n);
// Op0 Op1 CRn CRm Op2
- def : RWSysReg<"AFGDTP"#n#"_EL1", 0b11, 0b000, 0b0011, {0b011,nb{3}}, nb{2-0}>;
- def : RWSysReg<"AFGDTU"#n#"_EL1", 0b11, 0b000, 0b0011, {0b100,nb{3}}, nb{2-0}>;
- def : RWSysReg<"AFGDTP"#n#"_EL2", 0b11, 0b100, 0b0011, {0b011,nb{3}}, nb{2-0}>;
- def : RWSysReg<"AFGDTU"#n#"_EL2", 0b11, 0b100, 0b0011, {0b100,nb{3}}, nb{2-0}>;
- def : RWSysReg<"AFGDTP"#n#"_EL12", 0b11, 0b101, 0b0011, {0b011,nb{3}}, nb{2-0}>;
- def : RWSysReg<"AFGDTU"#n#"_EL12", 0b11, 0b101, 0b0011, {0b100,nb{3}}, nb{2-0}>;
- def : RWSysReg<"AFGDTP"#n#"_EL3", 0b11, 0b110, 0b0011, {0b011,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"AFGDTP"#n#"_EL1", 0b1, 0b000, 0b0011, {0b011,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"AFGDTU"#n#"_EL1", 0b1, 0b000, 0b0011, {0b100,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"AFGDTP"#n#"_EL2", 0b1, 0b100, 0b0011, {0b011,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"AFGDTU"#n#"_EL2", 0b1, 0b100, 0b0011, {0b100,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"AFGDTP"#n#"_EL12", 0b1, 0b101, 0b0011, {0b011,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"AFGDTU"#n#"_EL12", 0b1, 0b101, 0b0011, {0b100,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"AFGDTP"#n#"_EL3", 0b1, 0b110, 0b0011, {0b011,nb{3}}, nb{2-0}>;
}
// Extra S1POE2 Hypervisor Configuration Registers
// Op0 Op1 CRn CRm Op2
-def : RWSysReg<"HCRMASK_EL2", 0b11, 0b100, 0b0001, 0b0101, 0b110>;
-def : RWSysReg<"HCRXMASK_EL2", 0b11, 0b100, 0b0001, 0b0101, 0b111>;
-def : RWSysReg<"NVHCR_EL2", 0b11, 0b100, 0b0001, 0b0101, 0b000>;
-def : RWSysReg<"NVHCRX_EL2", 0b11, 0b100, 0b0001, 0b0101, 0b001>;
-def : RWSysReg<"NVHCRMASK_EL2", 0b11, 0b100, 0b0001, 0b0101, 0b100>;
-def : RWSysReg<"NVHCRXMASK_EL2", 0b11, 0b100, 0b0001, 0b0101, 0b101>;
+def : RWSysReg<"HCRMASK_EL2", 0b1, 0b100, 0b0001, 0b0101, 0b110>;
+def : RWSysReg<"HCRXMASK_EL2", 0b1, 0b100, 0b0001, 0b0101, 0b111>;
+def : RWSysReg<"NVHCR_EL2", 0b1, 0b100, 0b0001, 0b0101, 0b000>;
+def : RWSysReg<"NVHCRX_EL2", 0b1, 0b100, 0b0001, 0b0101, 0b001>;
+def : RWSysReg<"NVHCRMASK_EL2", 0b1, 0b100, 0b0001, 0b0101, 0b100>;
+def : RWSysReg<"NVHCRXMASK_EL2", 0b1, 0b100, 0b0001, 0b0101, 0b101>;
// S1POE2 Thread private state extension (FEAT_TPS/TPSP).
foreach n = 0-1 in {
defvar nb = !cast<bits<1>>(n);
// Op0 Op1 CRn CRm Op2
- def : RWSysReg<"TPMIN"#n#"_EL0", 0b11, 0b011, 0b0010, 0b0010, {0b1,nb,0}>;
- def : RWSysReg<"TPMAX"#n#"_EL0", 0b11, 0b011, 0b0010, 0b0010, {0b1,nb,1}>;
- def : RWSysReg<"TPMIN"#n#"_EL1", 0b11, 0b000, 0b0010, 0b0010, {0b1,nb,0}>;
- def : RWSysReg<"TPMAX"#n#"_EL1", 0b11, 0b000, 0b0010, 0b0010, {0b1,nb,1}>;
- def : RWSysReg<"TPMIN"#n#"_EL2", 0b11, 0b100, 0b0010, 0b0010, {0b1,nb,0}>;
- def : RWSysReg<"TPMAX"#n#"_EL2", 0b11, 0b100, 0b0010, 0b0010, {0b1,nb,1}>;
- def : RWSysReg<"TPMIN"#n#"_EL12", 0b11, 0b101, 0b0010, 0b0010, {0b1,nb,0}>;
- def : RWSysReg<"TPMAX"#n#"_EL12", 0b11, 0b101, 0b0010, 0b0010, {0b1,nb,1}>;
+ def : RWSysReg<"TPMIN"#n#"_EL0", 0b1, 0b011, 0b0010, 0b0010, {0b1,nb,0}>;
+ def : RWSysReg<"TPMAX"#n#"_EL0", 0b1, 0b011, 0b0010, 0b0010, {0b1,nb,1}>;
+ def : RWSysReg<"TPMIN"#n#"_EL1", 0b1, 0b000, 0b0010, 0b0010, {0b1,nb,0}>;
+ def : RWSysReg<"TPMAX"#n#"_EL1", 0b1, 0b000, 0b0010, 0b0010, {0b1,nb,1}>;
+ def : RWSysReg<"TPMIN"#n#"_EL2", 0b1, 0b100, 0b0010, 0b0010, {0b1,nb,0}>;
+ def : RWSysReg<"TPMAX"#n#"_EL2", 0b1, 0b100, 0b0010, 0b0010, {0b1,nb,1}>;
+ def : RWSysReg<"TPMIN"#n#"_EL12", 0b1, 0b101, 0b0010, 0b0010, {0b1,nb,0}>;
+ def : RWSysReg<"TPMAX"#n#"_EL12", 0b1, 0b101, 0b0010, 0b0010, {0b1,nb,1}>;
}
class PLBIEntry<bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, string name,
diff --git a/llvm/test/CodeGen/AArch64/aarch64-sme-za-call-lowering.ll b/llvm/test/CodeGen/AArch64/aarch64-sme-za-call-lowering.ll
index 0b8645f66b5f3..e7d764fabc2b7 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-sme-za-call-lowering.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-sme-za-call-lowering.ll
@@ -25,16 +25,16 @@ define void @requires_za_save() nounwind "aarch64_inout_za" {
; CHECK-AFTER-SMEABI-NEXT: STPXi [[MSUBXrrr]], [[RDSVLI_XI]], %stack.0, 0
; CHECK-AFTER-SMEABI-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0, 0
; CHECK-AFTER-SMEABI-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[ADDXri]]
- ; CHECK-AFTER-SMEABI-NEXT: MSR 56965, [[COPY1]]
+ ; CHECK-AFTER-SMEABI-NEXT: MSR 24197, [[COPY1]]
; CHECK-AFTER-SMEABI-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-AFTER-SMEABI-NEXT: RequiresZASavePseudo
; CHECK-AFTER-SMEABI-NEXT: BL @private_za_callee, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
; CHECK-AFTER-SMEABI-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-AFTER-SMEABI-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
- ; CHECK-AFTER-SMEABI-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
+ ; CHECK-AFTER-SMEABI-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 24197, implicit-def $nzcv
; CHECK-AFTER-SMEABI-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-AFTER-SMEABI-NEXT: RestoreZAPseudo [[MRS]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
- ; CHECK-AFTER-SMEABI-NEXT: MSR 56965, $xzr
+ ; CHECK-AFTER-SMEABI-NEXT: MSR 24197, $xzr
; CHECK-AFTER-SMEABI-NEXT: RET_ReallyLR
call void @private_za_callee()
ret void
@@ -61,7 +61,7 @@ define void @requires_za_save_streaming_mode_change() nounwind "aarch64_inout_za
; CHECK-AFTER-SMEABI-NEXT: STPXi [[MSUBXrrr]], [[RDSVLI_XI]], %stack.0, 0
; CHECK-AFTER-SMEABI-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0, 0
; CHECK-AFTER-SMEABI-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[ADDXri]]
- ; CHECK-AFTER-SMEABI-NEXT: MSR 56965, [[COPY1]]
+ ; CHECK-AFTER-SMEABI-NEXT: MSR 24197, [[COPY1]]
; CHECK-AFTER-SMEABI-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-AFTER-SMEABI-NEXT: RequiresZASavePseudo
; CHECK-AFTER-SMEABI-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $sp, implicit $vg, implicit-def $vg, implicit-def $fpmr
@@ -69,10 +69,10 @@ define void @requires_za_save_streaming_mode_change() nounwind "aarch64_inout_za
; CHECK-AFTER-SMEABI-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-AFTER-SMEABI-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
; CHECK-AFTER-SMEABI-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
- ; CHECK-AFTER-SMEABI-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
+ ; CHECK-AFTER-SMEABI-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 24197, implicit-def $nzcv
; CHECK-AFTER-SMEABI-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-AFTER-SMEABI-NEXT: RestoreZAPseudo [[MRS]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
- ; CHECK-AFTER-SMEABI-NEXT: MSR 56965, $xzr
+ ; CHECK-AFTER-SMEABI-NEXT: MSR 24197, $xzr
; CHECK-AFTER-SMEABI-NEXT: RET_ReallyLR
call void @private_za_callee()
ret void
diff --git a/llvm/test/CodeGen/AArch64/expand-sme-pseudos.mir b/llvm/test/CodeGen/AArch64/expand-sme-pseudos.mir
index 9b745d56c4b7f..48cc2a1e5b8aa 100644
--- a/llvm/test/CodeGen/AArch64/expand-sme-pseudos.mir
+++ b/llvm/test/CodeGen/AArch64/expand-sme-pseudos.mir
@@ -55,7 +55,7 @@ body: |
; CHECK-NEXT: liveins: $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: BL &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $lr, implicit $sp
- ; CHECK-NEXT: MSR 56965, $xzr
+ ; CHECK-NEXT: MSR 24197, $xzr
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: .2:
@@ -86,7 +86,7 @@ body: |
; CHECK-NEXT: liveins: $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: BL &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $lr, implicit $sp, implicit-def $zab0
- ; CHECK-NEXT: MSR 56965, $xzr
+ ; CHECK-NEXT: MSR 24197, $xzr
; CHECK-NEXT: ZERO_M 255, implicit-def $zab0
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
@@ -118,7 +118,7 @@ body: |
; CHECK-NEXT: liveins: $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: BL &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $lr, implicit $sp, implicit-def $zt0
- ; CHECK-NEXT: MSR 56965, $xzr
+ ; CHECK-NEXT: MSR 24197, $xzr
; CHECK-NEXT: $zt0 = ZERO_T
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
@@ -150,7 +150,7 @@ body: |
; CHECK-NEXT: liveins: $x8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: BL &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $lr, implicit $sp, implicit-def $zab0, implicit-def $zt0
- ; CHECK-NEXT: MSR 56965, $xzr
+ ; CHECK-NEXT: MSR 24197, $xzr
; CHECK-NEXT: ZERO_M 255, implicit-def $zab0
; CHECK-NEXT: $zt0 = ZERO_T
; CHECK-NEXT: B %bb.2
diff --git a/llvm/test/CodeGen/AArch64/machine-sme-abi-find-insert-pt.mir b/llvm/test/CodeGen/AArch64/machine-sme-abi-find-insert-pt.mir
index ed768dec77998..7aa89f990b71a 100644
--- a/llvm/test/CodeGen/AArch64/machine-sme-abi-find-insert-pt.mir
+++ b/llvm/test/CodeGen/AArch64/machine-sme-abi-find-insert-pt.mir
@@ -33,16 +33,16 @@ body: |
; CHECK-NEXT: STPXi [[MSUBXrrr]], [[RDSVLI_XI]], %stack.0, 0
; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0, 0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[ADDXri]]
- ; CHECK-NEXT: MSR 56965, [[COPY1]]
+ ; CHECK-NEXT: MSR 24197, [[COPY1]]
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: RequiresZASavePseudo
; CHECK-NEXT: BL @clobber, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
- ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
+ ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 24197, implicit-def $nzcv
; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-NEXT: RestoreZAPseudo [[MRS]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
- ; CHECK-NEXT: MSR 56965, $xzr
+ ; CHECK-NEXT: MSR 24197, $xzr
; CHECK-NEXT: $nzcv = IMPLICIT_DEF
; CHECK-NEXT: $zab0 = IMPLICIT_DEF
; CHECK-NEXT: FAKE_USE $nzcv
@@ -74,16 +74,16 @@ body: |
; CHECK-NEXT: STPXi [[MSUBXrrr]], [[RDSVLI_XI]], %stack.0, 0
; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0, 0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[ADDXri]]
- ; CHECK-NEXT: MSR 56965, [[COPY1]]
+ ; CHECK-NEXT: MSR 24197, [[COPY1]]
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: RequiresZASavePseudo
; CHECK-NEXT: BL @clobber, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
- ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
+ ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 24197, implicit-def $nzcv
; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-NEXT: RestoreZAPseudo [[MRS]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
- ; CHECK-NEXT: MSR 56965, $xzr
+ ; CHECK-NEXT: MSR 24197, $xzr
; CHECK-NEXT: $x0 = IMPLICIT_DEF
; CHECK-NEXT: $nzcv = IMPLICIT_DEF
; CHECK-NEXT: FAKE_USE $x0
@@ -121,10 +121,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $sp
; CHECK-NEXT: $nzcv = IMPLICIT_DEF
; CHECK-NEXT: $zab0 = IMPLICIT_DEF
- ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 55824, implicit-def $nzcv, implicit $nzcv
+ ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 23056, implicit-def $nzcv, implicit $nzcv
; CHECK-NEXT: $x0 = COPY [[COPY1]]
; CHECK-NEXT: BL &__arm_sme_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x1, implicit-def $lr, implicit $sp, implicit $x0
- ; CHECK-NEXT: MSR 55824, [[MRS]], implicit-def $nzcv
+ ; CHECK-NEXT: MSR 23056, [[MRS]], implicit-def $nzcv
; CHECK-NEXT: Bcc 2, %bb.1, implicit $nzcv
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
@@ -193,19 +193,19 @@ body: |
; CHECK-NEXT: STPXi [[MSUBXrrr]], [[RDSVLI_XI]], %stack.0, 0
; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0, 0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[ADDXri]]
- ; CHECK-NEXT: MSR 56965, [[COPY1]]
+ ; CHECK-NEXT: MSR 24197, [[COPY1]]
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: RequiresZASavePseudo
; CHECK-NEXT: BL @clobber, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
; CHECK-NEXT: $nzcv = IMPLICIT_DEF
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 55824, implicit-def $nzcv, implicit $nzcv
+ ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 23056, implicit-def $nzcv, implicit $nzcv
; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
- ; CHECK-NEXT: [[MRS1:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
+ ; CHECK-NEXT: [[MRS1:%[0-9]+]]:gpr64 = MRS 24197, implicit-def $nzcv
; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-NEXT: RestoreZAPseudo [[MRS1]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
- ; CHECK-NEXT: MSR 56965, $xzr
- ; CHECK-NEXT: MSR 55824, [[MRS]], implicit-def $nzcv
+ ; CHECK-NEXT: MSR 24197, $xzr
+ ; CHECK-NEXT: MSR 23056, [[MRS]], implicit-def $nzcv
; CHECK-NEXT: $zab0 = IMPLICIT_DEF
; CHECK-NEXT: FAKE_USE $nzcv
; CHECK-NEXT: RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/sme-abi-eh-liveins.mir b/llvm/test/CodeGen/AArch64/sme-abi-eh-liveins.mir
index 711745e528bbf..0dfbdd0d49011 100644
--- a/llvm/test/CodeGen/AArch64/sme-abi-eh-liveins.mir
+++ b/llvm/test/CodeGen/AArch64/sme-abi-eh-liveins.mir
@@ -31,15 +31,15 @@ body: |
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0, 0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[ADDXri]]
- ; CHECK-NEXT: MSR 56965, [[COPY1]]
+ ; CHECK-NEXT: MSR 24197, [[COPY1]]
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: RequiresZASavePseudo
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
- ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
+ ; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 24197, implicit-def $nzcv
; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-NEXT: RestoreZAPseudo [[MRS]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
- ; CHECK-NEXT: MSR 56965, $xzr
+ ; CHECK-NEXT: MSR 24197, $xzr
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1 (landing-pad):
@@ -47,10 +47,10 @@ body: |
; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
- ; CHECK-NEXT: [[MRS1:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
+ ; CHECK-NEXT: [[MRS1:%[0-9]+]]:gpr64 = MRS 24197, implicit-def $nzcv
; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-NEXT: RestoreZAPseudo [[MRS1]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
- ; CHECK-NEXT: MSR 56965, $xzr
+ ; CHECK-NEXT: MSR 24197, $xzr
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: InOutZAUsePseudo
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
diff --git a/llvm/test/CodeGen/AArch64/sme-lazy-sve-nzcv-live.mir b/llvm/test/CodeGen/AArch64/sme-lazy-sve-nzcv-live.mir
index 9f33c0614cee0..7e98367b829c8 100644
--- a/llvm/test/CodeGen/AArch64/sme-lazy-sve-nzcv-live.mir
+++ b/llvm/test/CodeGen/AArch64/sme-lazy-sve-nzcv-live.mir
@@ -57,16 +57,16 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32common = COPY $w0
; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0, 0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[ADDXri]]
- ; CHECK-NEXT: MSR 56965, [[COPY2]]
+ ; CHECK-NEXT: MSR 24197, [[COPY2]]
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: RequiresZASavePseudo
; CHECK-NEXT: BL @clobber, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
- ; CHECK-NEXT: [[MRS1:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
+ ; CHECK-NEXT: [[MRS1:%[0-9]+]]:gpr64 = MRS 24197, implicit-def $nzcv
; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0
; CHECK-NEXT: RestoreZAPseudo [[MRS1]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
- ; CHECK-NEXT: MSR 56965, $xzr
+ ; CHECK-NEXT: MSR 24197, $xzr
; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY1]], 101, 0, implicit-def $nzcv
; CHECK-NEXT: Bcc 11, %bb.2, implicit $nzcv
; CHECK-NEXT: B %bb.1
>From b08d57a8cc2d6bf0f3a6619662148310ab673344 Mon Sep 17 00:00:00 2001
From: Marian Lukac <Marian.Lukac at arm.com>
Date: Wed, 11 Mar 2026 20:27:38 +0000
Subject: [PATCH 02/12] [NFC] autogenerate disassembler tests with invalid
MSR/MRS use
---
.../MC/Disassembler/AArch64/armv8.2a-uao.txt | 21 +-
.../MC/Disassembler/AArch64/armv8.4a-dit.txt | 13 +-
.../AArch64/armv8.5a-dataproc.txt | 116 ++-
.../MC/Disassembler/AArch64/armv8.5a-mte.txt | 704 ++++++++----------
.../MC/Disassembler/AArch64/armv8.5a-sb.txt | 5 +-
.../MC/Disassembler/AArch64/armv8.5a-ssbs.txt | 13 +-
.../MC/Disassembler/AArch64/armv8.7a-wfxt.txt | 9 +-
.../MC/Disassembler/AArch64/armv8.7a-xs.txt | 263 ++++---
.../MC/Disassembler/AArch64/armv8.8a-nmi.txt | 25 +-
9 files changed, 563 insertions(+), 606 deletions(-)
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.2a-uao.txt b/llvm/test/MC/Disassembler/AArch64/armv8.2a-uao.txt
index 6c6817d85e4cf..2e45be4b342fe 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.2a-uao.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.2a-uao.txt
@@ -1,19 +1,20 @@
+# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple aarch64-none-linux-gnu --disassemble < %s 2>&1 | FileCheck --check-prefix=NO_V82A %s
[0x7f,0x40,0x00,0xd5]
+# CHECK: msr UAO, #0
+# NO_V82A: msr S0_0_C4_C0_3, xzr
[0x7f,0x41,0x00,0xd5]
+# CHECK: msr UAO, #1
+# NO_V82A: msr S0_0_C4_C1_3, xzr
[0x7f,0x4f,0x00,0xd5]
-# CHECK: msr UAO, #0
-# CHECK: msr UAO, #1
-# CHECK: msr UAO, #15
-# NO_V82A: msr S0_0_C4_C0_3, xzr
-# NO_V82A: msr S0_0_C4_C1_3, xzr
-# NO_V82A: msr S0_0_C4_C15_3, xzr
+# CHECK: msr UAO, #15
+# NO_V82A: msr S0_0_C4_C15_3, xzr
[0x81,0x42,0x18,0xd5]
+# CHECK: msr UAO, x1
+# NO_V82A: msr S3_0_C4_C2_4, x1
[0x82,0x42,0x38,0xd5]
-# CHECK: msr UAO, x1
-# CHECK: mrs x2, UAO
-# NO_V82A: msr S3_0_C4_C2_4, x1
-# NO_V82A: mrs x2, S3_0_C4_C2_4
+# CHECK: mrs x2, UAO
+# NO_V82A: mrs x2, S3_0_C4_C2_4
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt b/llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt
index f3d7da72c210c..b923ed8515ffa 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt
@@ -1,15 +1,16 @@
+# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
[0x5f,0x41,0x03,0xd5]
+# CHECK: msr DIT, #1
+# CHECK-NO-V84: msr S0_3_C4_C1_2, xzr
[0xa0,0x42,0x1b,0xd5]
+# CHECK: msr DIT, x0
+# CHECK-NO-V84: msr S3_3_C4_C2_5, x0
[0xa0,0x42,0x3b,0xd5]
+# CHECK: mrs x0, DIT
+# CHECK-NO-V84: mrs x0, S3_3_C4_C2_5
-#CHECK: msr DIT, #1
-#CHECK: msr DIT, x0
-#CHECK: mrs x0, DIT
-#CHECK-NO-V84: msr S0_3_C4_C1_2, xzr
-#CHECK-NO-V84: msr S3_3_C4_C2_5, x0
-#CHECK-NO-V84: mrs x0, S3_3_C4_C2_5
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-dataproc.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-dataproc.txt
index 29899bd834085..96eb158d5a3a0 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-dataproc.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-dataproc.txt
@@ -1,101 +1,77 @@
+# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.5a --disassemble < %s | FileCheck %s
-# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.5a --disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK-NOV85
-# RUN: FileCheck %s --check-prefix=CHECK-NOV85-ERROR < %t
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.5a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOV85
# Flag manipulation
[0x3f,0x40,0x00,0xd5]
-[0x5f,0x40,0x00,0xd5]
-
# CHECK: xaflag
+# CHECK-NOV85: msr S0_0_C4_C0_1, xzr
+[0x5f,0x40,0x00,0xd5]
# CHECK: axflag
+# CHECK-NOV85: msr S0_0_C4_C0_2, xzr
+
-# CHECK-NOV85: msr S0_0_C4_C0_1, xzr
-# CHECK-NOV85: msr S0_0_C4_C0_2, xzr
# FP-to-int rounding, scalar
[0x20,0x40,0x28,0x1e]
+# CHECK: frint32z s0, s1
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x20,0x40,0x68,0x1e]
+# CHECK: frint32z d0, d1
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x62,0x40,0x29,0x1e]
+# CHECK: frint64z s2, s3
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x62,0x40,0x69,0x1e]
+# CHECK: frint64z d2, d3
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xa4,0xc0,0x28,0x1e]
+# CHECK: frint32x s4, s5
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xa4,0xc0,0x68,0x1e]
+# CHECK: frint32x d4, d5
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe6,0xc0,0x29,0x1e]
+# CHECK: frint64x s6, s7
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe6,0xc0,0x69,0x1e]
-
-# CHECK: frint32z s0, s1
-# CHECK: frint32z d0, d1
-# CHECK: frint64z s2, s3
-# CHECK: frint64z d2, d3
-# CHECK: frint32x s4, s5
-# CHECK: frint32x d4, d5
-# CHECK: frint64x s6, s7
-# CHECK: frint64x d6, d7
-
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0x20,0x40,0x28,0x1e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0x20,0x40,0x68,0x1e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0x62,0x40,0x29,0x1e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0x62,0x40,0x69,0x1e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0xa4,0xc0,0x28,0x1e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0xa4,0xc0,0x68,0x1e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0xe6,0xc0,0x29,0x1e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0xe6,0xc0,0x69,0x1e]
+# CHECK: frint64x d6, d7
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
# FP-to-int rounding, vector
[0x20,0xe8,0x21,0x0e]
+# CHECK: frint32z v0.2s, v1.2s
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x20,0xe8,0x61,0x4e]
+# CHECK: frint32z v0.2d, v1.2d
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x20,0xe8,0x21,0x4e]
+# CHECK: frint32z v0.4s, v1.4s
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x62,0xf8,0x21,0x0e]
+# CHECK: frint64z v2.2s, v3.2s
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x62,0xf8,0x61,0x4e]
+# CHECK: frint64z v2.2d, v3.2d
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x62,0xf8,0x21,0x4e]
+# CHECK: frint64z v2.4s, v3.4s
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xa4,0xe8,0x21,0x2e]
+# CHECK: frint32x v4.2s, v5.2s
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xa4,0xe8,0x61,0x6e]
+# CHECK: frint32x v4.2d, v5.2d
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xa4,0xe8,0x21,0x6e]
+# CHECK: frint32x v4.4s, v5.4s
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe6,0xf8,0x21,0x2e]
+# CHECK: frint64x v6.2s, v7.2s
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe6,0xf8,0x61,0x6e]
+# CHECK: frint64x v6.2d, v7.2d
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe6,0xf8,0x21,0x6e]
-
-#CHECK: frint32z v0.2s, v1.2s
-#CHECK: frint32z v0.2d, v1.2d
-#CHECK: frint32z v0.4s, v1.4s
-#CHECK: frint64z v2.2s, v3.2s
-#CHECK: frint64z v2.2d, v3.2d
-#CHECK: frint64z v2.4s, v3.4s
-#CHECK: frint32x v4.2s, v5.2s
-#CHECK: frint32x v4.2d, v5.2d
-#CHECK: frint32x v4.4s, v5.4s
-#CHECK: frint64x v6.2s, v7.2s
-#CHECK: frint64x v6.2d, v7.2d
-#CHECK: frint64x v6.4s, v7.4s
-
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0x20,0xe8,0x21,0x0e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0x20,0xe8,0x61,0x4e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0x20,0xe8,0x21,0x4e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0x62,0xf8,0x21,0x0e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0x62,0xf8,0x61,0x4e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0x62,0xf8,0x21,0x4e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0xa4,0xe8,0x21,0x2e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0xa4,0xe8,0x61,0x6e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0xa4,0xe8,0x21,0x6e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0xe6,0xf8,0x21,0x2e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0xe6,0xf8,0x61,0x6e]
-# CHECK-NOV85-ERROR: invalid instruction encoding
-# CHECK-NOV85-ERROR-NEXT: [0xe6,0xf8,0x21,0x6e]
+# CHECK: frint64x v6.4s, v7.4s
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
index f93aae235abcd..2f9859ee248c9 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
@@ -1,613 +1,509 @@
+# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple=aarch64 -mattr=+mte -disassemble < %s | FileCheck %s
# RUN: not llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOMTE
# RUN: not llvm-mc -triple=aarch64 -mattr=-mte -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOMTE
[0x20,0x10,0xdf,0x9a]
+# CHECK: irg x0, x1
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x3f,0x10,0xdf,0x9a]
+# CHECK: irg sp, x1
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe0,0x13,0xdf,0x9a]
+# CHECK: irg x0, sp
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x20,0x10,0xc2,0x9a]
+# CHECK: irg x0, x1, x2
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x3f,0x10,0xc2,0x9a]
+# CHECK: irg sp, x1, x2
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
-# CHECK: irg x0, x1
-# CHECK: irg sp, x1
-# CHECK: irg x0, sp
-# CHECK: irg x0, x1, x2
-# CHECK: irg sp, x1, x2
-
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x10,0xdf,0x9a]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x3f,0x10,0xdf,0x9a]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe0,0x13,0xdf,0x9a]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x10,0xc2,0x9a]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x3f,0x10,0xc2,0x9a]
[0x20,0x04,0x80,0x91]
+# CHECK: addg x0, x1, #0, #1
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x5f,0x0c,0x82,0x91]
+# CHECK: addg sp, x2, #32, #3
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe0,0x17,0x84,0x91]
+# CHECK: addg x0, sp, #64, #5
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x83,0x18,0xbf,0x91]
+# CHECK: addg x3, x4, #1008, #6
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xc5,0x3c,0x87,0x91]
+# CHECK: addg x5, x6, #112, #15
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x20,0x04,0x80,0xd1]
+# CHECK: subg x0, x1, #0, #1
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x5f,0x0c,0x82,0xd1]
+# CHECK: subg sp, x2, #32, #3
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe0,0x17,0x84,0xd1]
+# CHECK: subg x0, sp, #64, #5
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x83,0x18,0xbf,0xd1]
+# CHECK: subg x3, x4, #1008, #6
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xc5,0x3c,0x87,0xd1]
+# CHECK: subg x5, x6, #112, #15
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
+
+
-# CHECK: addg x0, x1, #0, #1
-# CHECK: addg sp, x2, #32, #3
-# CHECK: addg x0, sp, #64, #5
-# CHECK: addg x3, x4, #1008, #6
-# CHECK: addg x5, x6, #112, #15
-
-# CHECK: subg x0, x1, #0, #1
-# CHECK: subg sp, x2, #32, #3
-# CHECK: subg x0, sp, #64, #5
-# CHECK: subg x3, x4, #1008, #6
-# CHECK: subg x5, x6, #112, #15
-
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x04,0x80,0x91]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x5f,0x0c,0x82,0x91]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe0,0x17,0x84,0x91]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x83,0x18,0xbf,0x91]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xc5,0x3c,0x87,0x91]
-
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x04,0x80,0xd1]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x5f,0x0c,0x82,0xd1]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe0,0x17,0x84,0xd1]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x83,0x18,0xbf,0xd1]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xc5,0x3c,0x87,0xd1]
[0x20,0x14,0xc2,0x9a]
+# CHECK: gmi x0, x1, x2
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe3,0x17,0xc4,0x9a]
+# CHECK: gmi x3, sp, x4
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x1f,0x14,0xde,0x9a]
+# CHECK: gmi xzr, x0, x30
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x1e,0x14,0xdf,0x9a]
+# CHECK: gmi x30, x0, xzr
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
-# CHECK: gmi x0, x1, x2
-# CHECK: gmi x3, sp, x4
-# CHECK: gmi xzr, x0, x30
-# CHECK: gmi x30, x0, xzr
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x14,0xc2,0x9a]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe3,0x17,0xc4,0x9a]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x1f,0x14,0xde,0x9a]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x1e,0x14,0xdf,0x9a]
[0x20,0x00,0xc2,0x9a]
+# CHECK: subp x0, x1, x2
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x20,0x00,0xc2,0xba]
+# CHECK: subps x0, x1, x2
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe0,0x03,0xdf,0x9a]
+# CHECK: subp x0, sp, sp
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe0,0x03,0xdf,0xba]
+# CHECK: subps x0, sp, sp
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x1f,0x00,0xc1,0xba]
+# CHECK: subps xzr, x0, x1
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xff,0x03,0xdf,0xba]
+# CHECK: subps xzr, sp, sp
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
-# CHECK: subp x0, x1, x2
-# CHECK: subps x0, x1, x2
-# CHECK: subp x0, sp, sp
-# CHECK: subps x0, sp, sp
-# CHECK: subps xzr, x0, x1
-# CHECK: subps xzr, sp, sp
-
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x00,0xc2,0x9a]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x00,0xc2,0xba]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe0,0x03,0xdf,0x9a]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe0,0x03,0xdf,0xba]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x1f,0x00,0xc1,0xba]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xff,0x03,0xdf,0xba]
[0x20,0x08,0x30,0xd9]
+# CHECK: stg x0, [x1, #-4096]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x41,0xf8,0x2f,0xd9]
+# CHECK: stg x1, [x2, #4080]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe2,0x1b,0x20,0xd9]
+# CHECK: stg x2, [sp, #16]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x23,0x08,0x20,0xd9]
+# CHECK: stg x3, [x1]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x3f,0x08,0x20,0xd9]
+# CHECK: stg sp, [x1]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
-# CHECK: stg x0, [x1, #-4096]
-# CHECK: stg x1, [x2, #4080]
-# CHECK: stg x2, [sp, #16]
-# CHECK: stg x3, [x1]
-# CHECK: stg sp, [x1]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x08,0x30,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x41,0xf8,0x2f,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe2,0x1b,0x20,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x23,0x08,0x20,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x3f,0x08,0x20,0xd9]
[0x20,0x08,0x70,0xd9]
+# CHECK: stzg x0, [x1, #-4096]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x41,0xf8,0x6f,0xd9]
+# CHECK: stzg x1, [x2, #4080]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe2,0x1b,0x60,0xd9]
+# CHECK: stzg x2, [sp, #16]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x23,0x08,0x60,0xd9]
+# CHECK: stzg x3, [x1]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x3f,0x08,0x60,0xd9]
+# CHECK: stzg sp, [x1]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
-# CHECK: stzg x0, [x1, #-4096]
-# CHECK: stzg x1, [x2, #4080]
-# CHECK: stzg x2, [sp, #16]
-# CHECK: stzg x3, [x1]
-# CHECK: stzg sp, [x1]
-
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x08,0x70,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x41,0xf8,0x6f,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe2,0x1b,0x60,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x23,0x08,0x60,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x3f,0x08,0x60,0xd9]
[0x20,0x0c,0x30,0xd9]
+# CHECK: stg x0, [x1, #-4096]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x41,0xfc,0x2f,0xd9]
+# CHECK: stg x1, [x2, #4080]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe2,0x1f,0x20,0xd9]
+# CHECK: stg x2, [sp, #16]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xff,0x1f,0x20,0xd9]
+# CHECK: stg sp, [sp, #16]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
-# CHECK: stg x0, [x1, #-4096]!
-# CHECK: stg x1, [x2, #4080]!
-# CHECK: stg x2, [sp, #16]!
-# CHECK: stg sp, [sp, #16]!
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x0c,0x30,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x41,0xfc,0x2f,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe2,0x1f,0x20,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xff,0x1f,0x20,0xd9]
[0x20,0x0c,0x70,0xd9]
+# CHECK: stzg x0, [x1, #-4096]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x41,0xfc,0x6f,0xd9]
+# CHECK: stzg x1, [x2, #4080]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe2,0x1f,0x60,0xd9]
+# CHECK: stzg x2, [sp, #16]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xff,0x1f,0x60,0xd9]
+# CHECK: stzg sp, [sp, #16]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
-# CHECK: stzg x0, [x1, #-4096]!
-# CHECK: stzg x1, [x2, #4080]!
-# CHECK: stzg x2, [sp, #16]!
-# CHECK: stzg sp, [sp, #16]!
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x0c,0x70,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x41,0xfc,0x6f,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe2,0x1f,0x60,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xff,0x1f,0x60,0xd9]
[0x20,0x04,0x30,0xd9]
+# CHECK: stg x0, [x1], #-4096
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x41,0xf4,0x2f,0xd9]
+# CHECK: stg x1, [x2], #4080
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe2,0x17,0x20,0xd9]
+# CHECK: stg x2, [sp], #16
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xff,0x17,0x20,0xd9]
+# CHECK: stg sp, [sp], #16
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
-# CHECK: stg x0, [x1], #-4096
-# CHECK: stg x1, [x2], #4080
-# CHECK: stg x2, [sp], #16
-# CHECK: stg sp, [sp], #16
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x04,0x30,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x41,0xf4,0x2f,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe2,0x17,0x20,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xff,0x17,0x20,0xd9]
[0x20,0x04,0x70,0xd9]
+# CHECK: stzg x0, [x1], #-4096
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x41,0xf4,0x6f,0xd9]
+# CHECK: stzg x1, [x2], #4080
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe2,0x17,0x60,0xd9]
+# CHECK: stzg x2, [sp], #16
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xff,0x17,0x60,0xd9]
+# CHECK: stzg sp, [sp], #16
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
-# CHECK: stzg x0, [x1], #-4096
-# CHECK: stzg x1, [x2], #4080
-# CHECK: stzg x2, [sp], #16
-# CHECK: stzg sp, [sp], #16
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x04,0x70,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x41,0xf4,0x6f,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe2,0x17,0x60,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xff,0x17,0x60,0xd9]
[0x20,0x08,0xb0,0xd9]
+# CHECK: st2g x0, [x1, #-4096]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x41,0xf8,0xaf,0xd9]
+# CHECK: st2g x1, [x2, #4080]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe2,0x1b,0xa0,0xd9]
+# CHECK: st2g x2, [sp, #16]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x23,0x08,0xa0,0xd9]
+# CHECK: st2g x3, [x1]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x3f,0x08,0xa0,0xd9]
+# CHECK: st2g sp, [x1]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
-# CHECK: st2g x0, [x1, #-4096]
-# CHECK: st2g x1, [x2, #4080]
-# CHECK: st2g x2, [sp, #16]
-# CHECK: st2g x3, [x1]
-# CHECK: st2g sp, [x1]
-
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x08,0xb0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x41,0xf8,0xaf,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe2,0x1b,0xa0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x23,0x08,0xa0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x3f,0x08,0xa0,0xd9]
[0x20,0x08,0xf0,0xd9]
+# CHECK: stz2g x0, [x1, #-4096]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x41,0xf8,0xef,0xd9]
+# CHECK: stz2g x1, [x2, #4080]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe2,0x1b,0xe0,0xd9]
+# CHECK: stz2g x2, [sp, #16]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x23,0x08,0xe0,0xd9]
+# CHECK: stz2g x3, [x1]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x3f,0x08,0xe0,0xd9]
+# CHECK: stz2g sp, [x1]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
-# CHECK: stz2g x0, [x1, #-4096]
-# CHECK: stz2g x1, [x2, #4080]
-# CHECK: stz2g x2, [sp, #16]
-# CHECK: stz2g x3, [x1]
-# CHECK: stz2g sp, [x1]
-
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x08,0xf0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x41,0xf8,0xef,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe2,0x1b,0xe0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x23,0x08,0xe0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x3f,0x08,0xe0,0xd9]
[0x20,0x0c,0xb0,0xd9]
+# CHECK: st2g x0, [x1, #-4096]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x41,0xfc,0xaf,0xd9]
+# CHECK: st2g x1, [x2, #4080]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe2,0x1f,0xa0,0xd9]
+# CHECK: st2g x2, [sp, #16]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xff,0x1f,0xa0,0xd9]
+# CHECK: st2g sp, [sp, #16]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
-# CHECK: st2g x0, [x1, #-4096]!
-# CHECK: st2g x1, [x2, #4080]!
-# CHECK: st2g x2, [sp, #16]!
-# CHECK: st2g sp, [sp, #16]!
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x0c,0xb0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x41,0xfc,0xaf,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe2,0x1f,0xa0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xff,0x1f,0xa0,0xd9]
[0x20,0x0c,0xf0,0xd9]
+# CHECK: stz2g x0, [x1, #-4096]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x41,0xfc,0xef,0xd9]
+# CHECK: stz2g x1, [x2, #4080]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe2,0x1f,0xe0,0xd9]
+# CHECK: stz2g x2, [sp, #16]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xff,0x1f,0xe0,0xd9]
+# CHECK: stz2g sp, [sp, #16]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
-# CHECK: stz2g x0, [x1, #-4096]!
-# CHECK: stz2g x1, [x2, #4080]!
-# CHECK: stz2g x2, [sp, #16]!
-# CHECK: stz2g sp, [sp, #16]!
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x0c,0xf0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x41,0xfc,0xef,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe2,0x1f,0xe0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xff,0x1f,0xe0,0xd9]
[0x20,0x04,0xb0,0xd9]
+# CHECK: st2g x0, [x1], #-4096
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x41,0xf4,0xaf,0xd9]
+# CHECK: st2g x1, [x2], #4080
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe2,0x17,0xa0,0xd9]
+# CHECK: st2g x2, [sp], #16
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xff,0x17,0xa0,0xd9]
+# CHECK: st2g sp, [sp], #16
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
-# CHECK: st2g x0, [x1], #-4096
-# CHECK: st2g x1, [x2], #4080
-# CHECK: st2g x2, [sp], #16
-# CHECK: st2g sp, [sp], #16
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x04,0xb0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x41,0xf4,0xaf,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe2,0x17,0xa0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xff,0x17,0xa0,0xd9]
[0x20,0x04,0xf0,0xd9]
+# CHECK: stz2g x0, [x1], #-4096
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x41,0xf4,0xef,0xd9]
+# CHECK: stz2g x1, [x2], #4080
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe2,0x17,0xe0,0xd9]
+# CHECK: stz2g x2, [sp], #16
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xff,0x17,0xe0,0xd9]
+# CHECK: stz2g sp, [sp], #16
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
-# CHECK: stz2g x0, [x1], #-4096
-# CHECK: stz2g x1, [x2], #4080
-# CHECK: stz2g x2, [sp], #16
-# CHECK: stz2g sp, [sp], #16
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x04,0xf0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x41,0xf4,0xef,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe2,0x17,0xe0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xff,0x17,0xe0,0xd9]
[0x40,0x04,0x20,0x69]
+# CHECK: stgp x0, x1, [x2, #-1024]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x40,0x84,0x1f,0x69]
+# CHECK: stgp x0, x1, [x2, #1008]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe0,0x87,0x00,0x69]
+# CHECK: stgp x0, x1, [sp, #16]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x5f,0x84,0x00,0x69]
+# CHECK: stgp xzr, x1, [x2, #16]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x40,0xfc,0x00,0x69]
+# CHECK: stgp x0, xzr, [x2, #16]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x40,0x7c,0x00,0x69]
+# CHECK: stgp x0, xzr, [x2]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
-# CHECK: stgp x0, x1, [x2, #-1024]
-# CHECK: stgp x0, x1, [x2, #1008]
-# CHECK: stgp x0, x1, [sp, #16]
-# CHECK: stgp xzr, x1, [x2, #16]
-# CHECK: stgp x0, xzr, [x2, #16]
-# CHECK: stgp x0, xzr, [x2]
-
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x40,0x04,0x20,0x69]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x40,0x84,0x1f,0x69]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe0,0x87,0x00,0x69]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x5f,0x84,0x00,0x69]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x40,0xfc,0x00,0x69]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x40,0x7c,0x00,0x69]
[0x40,0x04,0xa0,0x69]
+# CHECK: stgp x0, x1, [x2, #-1024]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x40,0x84,0x9f,0x69]
+# CHECK: stgp x0, x1, [x2, #1008]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe0,0x87,0x80,0x69]
+# CHECK: stgp x0, x1, [sp, #16]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x5f,0x84,0x80,0x69]
+# CHECK: stgp xzr, x1, [x2, #16]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x40,0xfc,0x80,0x69]
+# CHECK: stgp x0, xzr, [x2, #16]!
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
-# CHECK: stgp x0, x1, [x2, #-1024]!
-# CHECK: stgp x0, x1, [x2, #1008]!
-# CHECK: stgp x0, x1, [sp, #16]!
-# CHECK: stgp xzr, x1, [x2, #16]!
-# CHECK: stgp x0, xzr, [x2, #16]!
-
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x40,0x04,0xa0,0x69]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x40,0x84,0x9f,0x69]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe0,0x87,0x80,0x69]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x5f,0x84,0x80,0x69]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x40,0xfc,0x80,0x69]
[0x40,0x04,0xa0,0x68]
+# CHECK: stgp x0, x1, [x2], #-1024
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x40,0x84,0x9f,0x68]
+# CHECK: stgp x0, x1, [x2], #1008
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe0,0x87,0x80,0x68]
+# CHECK: stgp x0, x1, [sp], #16
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x5f,0x84,0x80,0x68]
+# CHECK: stgp xzr, x1, [x2], #16
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x40,0xfc,0x80,0x68]
+# CHECK: stgp x0, xzr, [x2], #16
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
-# CHECK: stgp x0, x1, [x2], #-1024
-# CHECK: stgp x0, x1, [x2], #1008
-# CHECK: stgp x0, x1, [sp], #16
-# CHECK: stgp xzr, x1, [x2], #16
-# CHECK: stgp x0, xzr, [x2], #16
-
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x40,0x04,0xa0,0x68]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x40,0x84,0x9f,0x68]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe0,0x87,0x80,0x68]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x5f,0x84,0x80,0x68]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x40,0xfc,0x80,0x68]
[0x20,0x00,0x60,0xd9]
+# CHECK: ldg x0, [x1]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe2,0x03,0x70,0xd9]
+# CHECK: ldg x2, [sp, #-4096]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x83,0xf0,0x6f,0xd9]
+# CHECK: ldg x3, [x4, #4080]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
-# CHECK: ldg x0, [x1]
-# CHECK: ldg x2, [sp, #-4096]
-# CHECK: ldg x3, [x4, #4080]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x00,0x60,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe2,0x03,0x70,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x83,0xf0,0x6f,0xd9]
[0x20,0x00,0xe0,0xd9]
+# CHECK: ldgm x0, [x1]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe1,0x03,0xe0,0xd9]
+# CHECK: ldgm x1, [sp]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x5f,0x00,0xe0,0xd9]
+# CHECK: ldgm xzr, [x2]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x20,0x00,0xa0,0xd9]
+# CHECK: stgm x0, [x1]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe1,0x03,0xa0,0xd9]
+# CHECK: stgm x1, [sp]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x5f,0x00,0xa0,0xd9]
+# CHECK: stgm xzr, [x2]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x20,0x00,0x20,0xd9]
+# CHECK: stzgm x0, [x1]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe1,0x03,0x20,0xd9]
+# CHECK: stzgm x1, [sp]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x5f,0x00,0x20,0xd9]
+# CHECK: stzgm xzr, [x2]
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
-# CHECK: ldgm x0, [x1]
-# CHECK: ldgm x1, [sp]
-# CHECK: ldgm xzr, [x2]
-# CHECK: stgm x0, [x1]
-# CHECK: stgm x1, [sp]
-# CHECK: stgm xzr, [x2]
-# CHECK: stzgm x0, [x1]
-# CHECK: stzgm x1, [sp]
-# CHECK: stzgm xzr, [x2]
-
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x00,0xe0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe1,0x03,0xe0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x5f,0x00,0xe0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x00,0xa0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe1,0x03,0xa0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x5f,0x00,0xa0,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x20,0x00,0x20,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0xe1,0x03,0x20,0xd9]
-# NOMTE: warning: invalid instruction encoding
-# NOMTE-NEXT: [0x5f,0x00,0x20,0xd9]
[0x60,0x76,0x08,0xd5]
+# CHECK: dc igvac, x0
+# NOMTE: sys #0, c7, c6, #3, x0
[0x81,0x76,0x08,0xd5]
+# CHECK: dc igsw, x1
+# NOMTE: sys #0, c7, c6, #4, x1
[0x82,0x7a,0x08,0xd5]
+# CHECK: dc cgsw, x2
+# NOMTE: sys #0, c7, c10, #4, x2
[0x83,0x7e,0x08,0xd5]
+# CHECK: dc cigsw, x3
+# NOMTE: sys #0, c7, c14, #4, x3
[0x64,0x7a,0x0b,0xd5]
+# CHECK: dc cgvac, x4
+# NOMTE: sys #3, c7, c10, #3, x4
[0x65,0x7c,0x0b,0xd5]
+# CHECK: dc cgvap, x5
+# NOMTE: sys #3, c7, c12, #3, x5
[0x66,0x7d,0x0b,0xd5]
+# CHECK: dc cgvadp, x6
+# NOMTE: sys #3, c7, c13, #3, x6
[0x67,0x7e,0x0b,0xd5]
+# CHECK: dc cigvac, x7
+# NOMTE: sys #3, c7, c14, #3, x7
[0x68,0x74,0x0b,0xd5]
+# CHECK: dc gva, x8
+# NOMTE: sys #3, c7, c4, #3, x8
[0xa9,0x76,0x08,0xd5]
+# CHECK: dc igdvac, x9
+# NOMTE: sys #0, c7, c6, #5, x9
[0xca,0x76,0x08,0xd5]
+# CHECK: dc igdsw, x10
+# NOMTE: sys #0, c7, c6, #6, x10
[0xcb,0x7a,0x08,0xd5]
+# CHECK: dc cgdsw, x11
+# NOMTE: sys #0, c7, c10, #6, x11
[0xcc,0x7e,0x08,0xd5]
+# CHECK: dc cigdsw, x12
+# NOMTE: sys #0, c7, c14, #6, x12
[0xad,0x7a,0x0b,0xd5]
+# CHECK: dc cgdvac, x13
+# NOMTE: sys #3, c7, c10, #5, x13
[0xae,0x7c,0x0b,0xd5]
+# CHECK: dc cgdvap, x14
+# NOMTE: sys #3, c7, c12, #5, x14
[0xaf,0x7d,0x0b,0xd5]
+# CHECK: dc cgdvadp, x15
+# NOMTE: sys #3, c7, c13, #5, x15
[0xb0,0x7e,0x0b,0xd5]
+# CHECK: dc cigdvac, x16
+# NOMTE: sys #3, c7, c14, #5, x16
[0x91,0x74,0x0b,0xd5]
+# CHECK: dc gzva, x17
+# NOMTE: sys #3, c7, c4, #4, x17
+
-# CHECK: dc igvac, x0
-# CHECK: dc igsw, x1
-# CHECK: dc cgsw, x2
-# CHECK: dc cigsw, x3
-# CHECK: dc cgvac, x4
-# CHECK: dc cgvap, x5
-# CHECK: dc cgvadp, x6
-# CHECK: dc cigvac, x7
-# CHECK: dc gva, x8
-# CHECK: dc igdvac, x9
-# CHECK: dc igdsw, x10
-# CHECK: dc cgdsw, x11
-# CHECK: dc cigdsw, x12
-# CHECK: dc cgdvac, x13
-# CHECK: dc cgdvap, x14
-# CHECK: dc cgdvadp, x15
-# CHECK: dc cigdvac, x16
-# CHECK: dc gzva, x17
-
-# NOMTE: sys #0, c7, c6, #3, x0
-# NOMTE: sys #0, c7, c6, #4, x1
-# NOMTE: sys #0, c7, c10, #4, x2
-# NOMTE: sys #0, c7, c14, #4, x3
-# NOMTE: sys #3, c7, c10, #3, x4
-# NOMTE: sys #3, c7, c12, #3, x5
-# NOMTE: sys #3, c7, c13, #3, x6
-# NOMTE: sys #3, c7, c14, #3, x7
-# NOMTE: sys #3, c7, c4, #3, x8
-# NOMTE: sys #0, c7, c6, #5, x9
-# NOMTE: sys #0, c7, c6, #6, x10
-# NOMTE: sys #0, c7, c10, #6, x11
-# NOMTE: sys #0, c7, c14, #6, x12
-# NOMTE: sys #3, c7, c10, #5, x13
-# NOMTE: sys #3, c7, c12, #5, x14
-# NOMTE: sys #3, c7, c13, #5, x15
-# NOMTE: sys #3, c7, c14, #5, x16
-# NOMTE: sys #3, c7, c4, #4, x17
[0xe0,0x42,0x3b,0xd5]
+# CHECK: mrs x0, TCO
+# NOMTE: mrs x0, S3_3_C4_C2_7
[0xc1,0x10,0x38,0xd5]
+# CHECK: mrs x1, GCR_EL1
+# NOMTE: mrs x1, S3_0_C1_C0_6
[0xa2,0x10,0x38,0xd5]
+# CHECK: mrs x2, RGSR_EL1
+# NOMTE: mrs x2, S3_0_C1_C0_5
[0x03,0x56,0x38,0xd5]
+# CHECK: mrs x3, TFSR_EL1
+# NOMTE: mrs x3, S3_0_C5_C6_0
[0x04,0x56,0x3c,0xd5]
+# CHECK: mrs x4, TFSR_EL2
+# NOMTE: mrs x4, S3_4_C5_C6_0
[0x05,0x56,0x3e,0xd5]
+# CHECK: mrs x5, TFSR_EL3
+# NOMTE: mrs x5, S3_6_C5_C6_0
[0x06,0x56,0x3d,0xd5]
+# CHECK: mrs x6, TFSR_EL12
+# NOMTE: mrs x6, S3_5_C5_C6_0
[0x27,0x56,0x38,0xd5]
+# CHECK: mrs x7, TFSRE0_EL1
+# NOMTE: mrs x7, S3_0_C5_C6_1
[0x88,0x00,0x39,0xd5]
+# CHECK: mrs x8, GMID_EL1
+# NOMTE: mrs x8, S3_1_C0_C0_4
+
-# CHECK: mrs x0, TCO
-# CHECK: mrs x1, GCR_EL1
-# CHECK: mrs x2, RGSR_EL1
-# CHECK: mrs x3, TFSR_EL1
-# CHECK: mrs x4, TFSR_EL2
-# CHECK: mrs x5, TFSR_EL3
-# CHECK: mrs x6, TFSR_EL12
-# CHECK: mrs x7, TFSRE0_EL1
-# CHECK: mrs x8, GMID_EL1
-
-# NOMTE: mrs x0, S3_3_C4_C2_7
-# NOMTE: mrs x1, S3_0_C1_C0_6
-# NOMTE: mrs x2, S3_0_C1_C0_5
-# NOMTE: mrs x3, S3_0_C5_C6_0
-# NOMTE: mrs x4, S3_4_C5_C6_0
-# NOMTE: mrs x5, S3_6_C5_C6_0
-# NOMTE: mrs x6, S3_5_C5_C6_0
-# NOMTE: mrs x7, S3_0_C5_C6_1
-# NOMTE: mrs x8, S3_1_C0_C0_4
[0x9f,0x40,0x03,0xd5]
+# CHECK: msr TCO, #0
+# NOMTE: msr S0_3_C4_C0_4, xzr
-# CHECK: msr TCO, #0
-# NOMTE: msr S0_3_C4_C0_4, xzr
[0xe0,0x42,0x1b,0xd5]
+# CHECK: msr TCO, x0
+# NOMTE: msr S3_3_C4_C2_7, x0
[0xc1,0x10,0x18,0xd5]
+# CHECK: msr GCR_EL1, x1
+# NOMTE: msr S3_0_C1_C0_6, x1
[0xa2,0x10,0x18,0xd5]
+# CHECK: msr RGSR_EL1, x2
+# NOMTE: msr S3_0_C1_C0_5, x2
[0x03,0x56,0x18,0xd5]
+# CHECK: msr TFSR_EL1, x3
+# NOMTE: msr S3_0_C5_C6_0, x3
[0x04,0x56,0x1c,0xd5]
+# CHECK: msr TFSR_EL2, x4
+# NOMTE: msr S3_4_C5_C6_0, x4
[0x05,0x56,0x1e,0xd5]
+# CHECK: msr TFSR_EL3, x5
+# NOMTE: msr S3_6_C5_C6_0, x5
[0x06,0x56,0x1d,0xd5]
+# CHECK: msr TFSR_EL12, x6
+# NOMTE: msr S3_5_C5_C6_0, x6
[0x27,0x56,0x18,0xd5]
+# CHECK: msr TFSRE0_EL1, x7
+# NOMTE: msr S3_0_C5_C6_1, x7
[0x88,0x00,0x19,0xd5]
+# CHECK: msr S3_1_C0_C0_4, x8
+# NOMTE: msr S3_1_C0_C0_4, x8
-# CHECK: msr TCO, x0
-# CHECK: msr GCR_EL1, x1
-# CHECK: msr RGSR_EL1, x2
-# CHECK: msr TFSR_EL1, x3
-# CHECK: msr TFSR_EL2, x4
-# CHECK: msr TFSR_EL3, x5
-# CHECK: msr TFSR_EL12, x6
-# CHECK: msr TFSRE0_EL1, x7
# GMID_EL1 is read only
-# CHECK: msr S3_1_C0_C0_4, x8
-
-# NOMTE: msr S3_3_C4_C2_7, x0
-# NOMTE: msr S3_0_C1_C0_6, x1
-# NOMTE: msr S3_0_C1_C0_5, x2
-# NOMTE: msr S3_0_C5_C6_0, x3
-# NOMTE: msr S3_4_C5_C6_0, x4
-# NOMTE: msr S3_6_C5_C6_0, x5
-# NOMTE: msr S3_5_C5_C6_0, x6
-# NOMTE: msr S3_0_C5_C6_1, x7
-# NOMTE: msr S3_1_C0_C0_4, x8
+
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt
index 25f32d45d625d..d3d7e8e6112f2 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt
@@ -1,9 +1,10 @@
+# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+sb -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+v8.5a -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=-sb -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
# New reg
0xff 0x30 0x03 0xd5
-
# CHECK: sb
-# NOSB: msr S0_3_C3_C0_7, xzr
+# NOSB: msr S0_3_C3_C0_7, xzr
+
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt
index 84d4fa6accccf..2ff24ee8c567f 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple=aarch64 -mattr=+ssbs -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s --check-prefix=NOSPECID
# RUN: llvm-mc -triple=aarch64 -mcpu=cortex-a76 -disassemble < %s | FileCheck %s
@@ -6,11 +7,11 @@
# RUN: llvm-mc -triple=aarch64 -mattr=-ssbs -disassemble < %s | FileCheck %s --check-prefix=NOSPECID
[0x3f 0x41 0x03 0xd5]
+# CHECK: msr SSBS, #1
+# NOSPECID: msr S0_3_C4_C1_1, xzr
[0xc3 0x42 0x1b 0xd5]
+# CHECK: msr SSBS, x3
+# NOSPECID: msr S3_3_C4_C2_6, x3
[0xc2 0x42 0x3b 0xd5]
-# CHECK: msr SSBS, #1
-# CHECK: msr SSBS, x3
-# CHECK: mrs x2, SSBS
-# NOSPECID: msr S0_3_C4_C1_1, xzr
-# NOSPECID: msr S3_3_C4_C2_6, x3
-# NOSPECID: mrs x2, S3_3_C4_C2_6
+# CHECK: mrs x2, SSBS
+# NOSPECID: mrs x2, S3_3_C4_C2_6
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt b/llvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt
index 232ba2dbcb527..58ce8e9aa7316 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt
@@ -1,11 +1,12 @@
+# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple=aarch64 -mattr=+wfxt -disassemble %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mattr=+v8.7a -disassemble %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck --check-prefix=CHECK-NO-WFxT %s
[0x11,0x10,0x03,0xd5]
-# CHECK: wfet x17
-# CHECK-NO-WFxT: msr S0_3_C1_C0_0, x17
+# CHECK: wfet x17
+# CHECK-NO-WFxT: msr S0_3_C1_C0_0, x17
[0x23,0x10,0x03,0xd5]
-# CHECK: wfit x3
-# CHECK-NO-WFxT: msr S0_3_C1_C0_1, x3
+# CHECK: wfit x3
+# CHECK-NO-WFxT: msr S0_3_C1_C0_1, x3
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt b/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
index ce09954f5f0f8..7bf36abe68e29 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
@@ -1,94 +1,127 @@
+# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple=aarch64 -mattr=+v8.4a,+xs -disassemble %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mattr=+v8.7a -disassemble %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mattr=+v8.4a -disassemble %s | FileCheck --check-prefix=CHECK-NO-XS %s
[0x3f,0x32,0x03,0xd5]
+# CHECK: dsb oshnxs
+# CHECK-NO-XS: msr S0_3_C3_C2_1, xzr
[0x3f,0x36,0x03,0xd5]
+# CHECK: dsb nshnxs
+# CHECK-NO-XS: msr S0_3_C3_C6_1, xzr
[0x3f,0x3a,0x03,0xd5]
+# CHECK: dsb ishnxs
+# CHECK-NO-XS: msr S0_3_C3_C10_1, xzr
[0x3f,0x3e,0x03,0xd5]
-# CHECK: dsb oshnxs
-# CHECK: dsb nshnxs
-# CHECK: dsb ishnxs
-# CHECK: dsb synxs
-# CHECK-NO-XS: msr S0_3_C3_C2_1, xzr
-# CHECK-NO-XS: msr S0_3_C3_C6_1, xzr
-# CHECK-NO-XS: msr S0_3_C3_C10_1, xzr
-# CHECK-NO-XS: msr S0_3_C3_C14_1, xzr
+# CHECK: dsb synxs
+# CHECK-NO-XS: msr S0_3_C3_C14_1, xzr
[0x3f,0x30,0x03,0xd5]
+# CHECK: msr S0_3_C3_C0_1, xzr
+# CHECK-NO-XS: msr S0_3_C3_C0_1, xzr
[0x3f,0x35,0x03,0xd5]
+# CHECK: msr S0_3_C3_C5_1, xzr
+# CHECK-NO-XS: msr S0_3_C3_C5_1, xzr
[0x3f,0x3f,0x03,0xd5]
-# CHECK: msr S0_3_C3_C0_1, xzr
-# CHECK: msr S0_3_C3_C5_1, xzr
-# CHECK: msr S0_3_C3_C15_1, xzr
-# CHECK-NO-XS: msr S0_3_C3_C0_1, xzr
-# CHECK-NO-XS: msr S0_3_C3_C5_1, xzr
-# CHECK-NO-XS: msr S0_3_C3_C15_1, xzr
+# CHECK: msr S0_3_C3_C15_1, xzr
+# CHECK-NO-XS: msr S0_3_C3_C15_1, xzr
[0x21,0x90,0x0c,0xd5]
+# CHECK: tlbi ipas2e1isnxs, x1
+# CHECK-NO-XS: sys #4, c9, c0, #1, x1
[0xa1,0x90,0x0c,0xd5]
+# CHECK: tlbi ipas2le1isnxs, x1
+# CHECK-NO-XS: sys #4, c9, c0, #5, x1
[0x1f,0x93,0x08,0xd5]
+# CHECK: tlbi vmalle1isnxs
+# CHECK-NO-XS: sys #0, c9, c3, #0
[0x1f,0x93,0x0c,0xd5]
+# CHECK: tlbi alle2isnxs
+# CHECK-NO-XS: sys #4, c9, c3, #0
[0x1f,0x93,0x0e,0xd5]
+# CHECK: tlbi alle3isnxs
+# CHECK-NO-XS: sys #6, c9, c3, #0
[0x21,0x93,0x08,0xd5]
+# CHECK: tlbi vae1isnxs, x1
+# CHECK-NO-XS: sys #0, c9, c3, #1, x1
[0x21,0x93,0x0c,0xd5]
+# CHECK: tlbi vae2isnxs, x1
+# CHECK-NO-XS: sys #4, c9, c3, #1, x1
[0x21,0x93,0x0e,0xd5]
+# CHECK: tlbi vae3isnxs, x1
+# CHECK-NO-XS: sys #6, c9, c3, #1, x1
[0x41,0x93,0x08,0xd5]
+# CHECK: tlbi aside1isnxs, x1
+# CHECK-NO-XS: sys #0, c9, c3, #2, x1
[0x61,0x93,0x08,0xd5]
+# CHECK: tlbi vaae1isnxs, x1
+# CHECK-NO-XS: sys #0, c9, c3, #3, x1
[0x9f,0x93,0x0c,0xd5]
+# CHECK: tlbi alle1isnxs
+# CHECK-NO-XS: sys #4, c9, c3, #4
[0xa1,0x93,0x08,0xd5]
+# CHECK: tlbi vale1isnxs, x1
+# CHECK-NO-XS: sys #0, c9, c3, #5, x1
[0xa1,0x93,0x0c,0xd5]
+# CHECK: tlbi vale2isnxs, x1
+# CHECK-NO-XS: sys #4, c9, c3, #5, x1
[0xa1,0x93,0x0e,0xd5]
+# CHECK: tlbi vale3isnxs, x1
+# CHECK-NO-XS: sys #6, c9, c3, #5, x1
[0xdf,0x93,0x0c,0xd5]
+# CHECK: tlbi vmalls12e1isnxs
+# CHECK-NO-XS: sys #4, c9, c3, #6
[0xe1,0x93,0x08,0xd5]
+# CHECK: tlbi vaale1isnxs, x1
+# CHECK-NO-XS: sys #0, c9, c3, #7, x1
[0x21,0x94,0x0c,0xd5]
+# CHECK: tlbi ipas2e1nxs, x1
+# CHECK-NO-XS: sys #4, c9, c4, #1, x1
[0xa1,0x94,0x0c,0xd5]
+# CHECK: tlbi ipas2le1nxs, x1
+# CHECK-NO-XS: sys #4, c9, c4, #5, x1
[0x1f,0x97,0x08,0xd5]
+# CHECK: tlbi vmalle1nxs
+# CHECK-NO-XS: sys #0, c9, c7, #0
[0x1f,0x97,0x0c,0xd5]
+# CHECK: tlbi alle2nxs
+# CHECK-NO-XS: sys #4, c9, c7, #0
[0x1f,0x97,0x0e,0xd5]
+# CHECK: tlbi alle3nxs
+# CHECK-NO-XS: sys #6, c9, c7, #0
[0x21,0x97,0x08,0xd5]
+# CHECK: tlbi vae1nxs, x1
+# CHECK-NO-XS: sys #0, c9, c7, #1, x1
[0x21,0x97,0x0c,0xd5]
+# CHECK: tlbi vae2nxs, x1
+# CHECK-NO-XS: sys #4, c9, c7, #1, x1
[0x21,0x97,0x0e,0xd5]
+# CHECK: tlbi vae3nxs, x1
+# CHECK-NO-XS: sys #6, c9, c7, #1, x1
[0x41,0x97,0x08,0xd5]
+# CHECK: tlbi aside1nxs, x1
+# CHECK-NO-XS: sys #0, c9, c7, #2, x1
[0x61,0x97,0x08,0xd5]
+# CHECK: tlbi vaae1nxs, x1
+# CHECK-NO-XS: sys #0, c9, c7, #3, x1
[0x9f,0x97,0x0c,0xd5]
+# CHECK: tlbi alle1nxs
+# CHECK-NO-XS: sys #4, c9, c7, #4
[0xa1,0x97,0x08,0xd5]
+# CHECK: tlbi vale1nxs, x1
+# CHECK-NO-XS: sys #0, c9, c7, #5, x1
[0xa1,0x97,0x0c,0xd5]
+# CHECK: tlbi vale2nxs, x1
+# CHECK-NO-XS: sys #4, c9, c7, #5, x1
[0xa1,0x97,0x0e,0xd5]
+# CHECK: tlbi vale3nxs, x1
+# CHECK-NO-XS: sys #6, c9, c7, #5, x1
[0xdf,0x97,0x0c,0xd5]
+# CHECK: tlbi vmalls12e1nxs
+# CHECK-NO-XS: sys #4, c9, c7, #6
[0xe1,0x97,0x08,0xd5]
-# CHECK: tlbi ipas2e1isnxs, x1
-# CHECK: tlbi ipas2le1isnxs, x1
-# CHECK: tlbi vmalle1isnxs
-# CHECK: tlbi alle2isnxs
-# CHECK: tlbi alle3isnxs
-# CHECK: tlbi vae1isnxs, x1
-# CHECK: tlbi vae2isnxs, x1
-# CHECK: tlbi vae3isnxs, x1
-# CHECK: tlbi aside1isnxs, x1
-# CHECK: tlbi vaae1isnxs, x1
-# CHECK: tlbi alle1isnxs
-# CHECK: tlbi vale1isnxs, x1
-# CHECK: tlbi vale2isnxs, x1
-# CHECK: tlbi vale3isnxs, x1
-# CHECK: tlbi vmalls12e1isnxs
-# CHECK: tlbi vaale1isnxs, x1
-# CHECK: tlbi ipas2e1nxs, x1
-# CHECK: tlbi ipas2le1nxs, x1
-# CHECK: tlbi vmalle1nxs
-# CHECK: tlbi alle2nxs
-# CHECK: tlbi alle3nxs
-# CHECK: tlbi vae1nxs, x1
-# CHECK: tlbi vae2nxs, x1
-# CHECK: tlbi vae3nxs, x1
-# CHECK: tlbi aside1nxs, x1
-# CHECK: tlbi vaae1nxs, x1
-# CHECK: tlbi alle1nxs
-# CHECK: tlbi vale1nxs, x1
-# CHECK: tlbi vale2nxs, x1
-# CHECK: tlbi vale3nxs, x1
-# CHECK: tlbi vmalls12e1nxs
-# CHECK: tlbi vaale1nxs, x1
+# CHECK: tlbi vaale1nxs, x1
+# CHECK-NO-XS: sys #0, c9, c7, #7, x1
# CHECK_NO_XS: sys #4, c9, c0, #1, x1
# CHECK_NO_XS: sys #4, c9, c0, #5, x1
# CHECK_NO_XS: sys #0, c9, c3, #0
@@ -123,97 +156,143 @@
# CHECK_NO_XS: sys #0, c9, c7, #7, x1
[0x1f,0x91,0x08,0xd5]
+# CHECK: tlbi vmalle1osnxs
+# CHECK-NO-XS: sys #0, c9, c1, #0
[0x21,0x91,0x08,0xd5]
+# CHECK: tlbi vae1osnxs, x1
+# CHECK-NO-XS: sys #0, c9, c1, #1, x1
[0x41,0x91,0x08,0xd5]
+# CHECK: tlbi aside1osnxs, x1
+# CHECK-NO-XS: sys #0, c9, c1, #2, x1
[0x61,0x91,0x08,0xd5]
+# CHECK: tlbi vaae1osnxs, x1
+# CHECK-NO-XS: sys #0, c9, c1, #3, x1
[0xa1,0x91,0x08,0xd5]
+# CHECK: tlbi vale1osnxs, x1
+# CHECK-NO-XS: sys #0, c9, c1, #5, x1
[0xe1,0x91,0x08,0xd5]
+# CHECK: tlbi vaale1osnxs, x1
+# CHECK-NO-XS: sys #0, c9, c1, #7, x1
[0x01,0x94,0x0c,0xd5]
+# CHECK: tlbi ipas2e1osnxs, x1
+# CHECK-NO-XS: sys #4, c9, c4, #0, x1
[0x81,0x94,0x0c,0xd5]
+# CHECK: tlbi ipas2le1osnxs, x1
+# CHECK-NO-XS: sys #4, c9, c4, #4, x1
[0x21,0x91,0x0c,0xd5]
+# CHECK: tlbi vae2osnxs, x1
+# CHECK-NO-XS: sys #4, c9, c1, #1, x1
[0xa1,0x91,0x0c,0xd5]
+# CHECK: tlbi vale2osnxs, x1
+# CHECK-NO-XS: sys #4, c9, c1, #5, x1
[0xdf,0x91,0x0c,0xd5]
+# CHECK: tlbi vmalls12e1osnxs
+# CHECK-NO-XS: sys #4, c9, c1, #6
[0x21,0x91,0x0e,0xd5]
+# CHECK: tlbi vae3osnxs, x1
+# CHECK-NO-XS: sys #6, c9, c1, #1, x1
[0xa1,0x91,0x0e,0xd5]
+# CHECK: tlbi vale3osnxs, x1
+# CHECK-NO-XS: sys #6, c9, c1, #5, x1
[0x1f,0x91,0x0c,0xd5]
+# CHECK: tlbi alle2osnxs
+# CHECK-NO-XS: sys #4, c9, c1, #0
[0x9f,0x91,0x0c,0xd5]
+# CHECK: tlbi alle1osnxs
+# CHECK-NO-XS: sys #4, c9, c1, #4
[0x1f,0x91,0x0e,0xd5]
+# CHECK: tlbi alle3osnxs
+# CHECK-NO-XS: sys #6, c9, c1, #0
[0x21,0x96,0x08,0xd5]
+# CHECK: tlbi rvae1nxs, x1
+# CHECK-NO-XS: sys #0, c9, c6, #1, x1
[0x61,0x96,0x08,0xd5]
+# CHECK: tlbi rvaae1nxs, x1
+# CHECK-NO-XS: sys #0, c9, c6, #3, x1
[0xa1,0x96,0x08,0xd5]
+# CHECK: tlbi rvale1nxs, x1
+# CHECK-NO-XS: sys #0, c9, c6, #5, x1
[0xe1,0x96,0x08,0xd5]
+# CHECK: tlbi rvaale1nxs, x1
+# CHECK-NO-XS: sys #0, c9, c6, #7, x1
[0x21,0x92,0x08,0xd5]
+# CHECK: tlbi rvae1isnxs, x1
+# CHECK-NO-XS: sys #0, c9, c2, #1, x1
[0x61,0x92,0x08,0xd5]
+# CHECK: tlbi rvaae1isnxs, x1
+# CHECK-NO-XS: sys #0, c9, c2, #3, x1
[0xa1,0x92,0x08,0xd5]
+# CHECK: tlbi rvale1isnxs, x1
+# CHECK-NO-XS: sys #0, c9, c2, #5, x1
[0xe1,0x92,0x08,0xd5]
+# CHECK: tlbi rvaale1isnxs, x1
+# CHECK-NO-XS: sys #0, c9, c2, #7, x1
[0x21,0x95,0x08,0xd5]
+# CHECK: tlbi rvae1osnxs, x1
+# CHECK-NO-XS: sys #0, c9, c5, #1, x1
[0x61,0x95,0x08,0xd5]
+# CHECK: tlbi rvaae1osnxs, x1
+# CHECK-NO-XS: sys #0, c9, c5, #3, x1
[0xa1,0x95,0x08,0xd5]
+# CHECK: tlbi rvale1osnxs, x1
+# CHECK-NO-XS: sys #0, c9, c5, #5, x1
[0xe1,0x95,0x08,0xd5]
+# CHECK: tlbi rvaale1osnxs, x1
+# CHECK-NO-XS: sys #0, c9, c5, #7, x1
[0x41,0x90,0x0c,0xd5]
+# CHECK: tlbi ripas2e1isnxs, x1
+# CHECK-NO-XS: sys #4, c9, c0, #2, x1
[0xc1,0x90,0x0c,0xd5]
+# CHECK: tlbi ripas2le1isnxs, x1
+# CHECK-NO-XS: sys #4, c9, c0, #6, x1
[0x41,0x94,0x0c,0xd5]
+# CHECK: tlbi ripas2e1nxs, x1
+# CHECK-NO-XS: sys #4, c9, c4, #2, x1
[0xc1,0x94,0x0c,0xd5]
+# CHECK: tlbi ripas2le1nxs, x1
+# CHECK-NO-XS: sys #4, c9, c4, #6, x1
[0x61,0x94,0x0c,0xd5]
+# CHECK: tlbi ripas2e1osnxs, x1
+# CHECK-NO-XS: sys #4, c9, c4, #3, x1
[0xe1,0x94,0x0c,0xd5]
+# CHECK: tlbi ripas2le1osnxs, x1
+# CHECK-NO-XS: sys #4, c9, c4, #7, x1
[0x21,0x96,0x0c,0xd5]
+# CHECK: tlbi rvae2nxs, x1
+# CHECK-NO-XS: sys #4, c9, c6, #1, x1
[0xa1,0x96,0x0c,0xd5]
+# CHECK: tlbi rvale2nxs, x1
+# CHECK-NO-XS: sys #4, c9, c6, #5, x1
[0x21,0x92,0x0c,0xd5]
+# CHECK: tlbi rvae2isnxs, x1
+# CHECK-NO-XS: sys #4, c9, c2, #1, x1
[0xa1,0x92,0x0c,0xd5]
+# CHECK: tlbi rvale2isnxs, x1
+# CHECK-NO-XS: sys #4, c9, c2, #5, x1
[0x21,0x95,0x0c,0xd5]
+# CHECK: tlbi rvae2osnxs, x1
+# CHECK-NO-XS: sys #4, c9, c5, #1, x1
[0xa1,0x95,0x0c,0xd5]
+# CHECK: tlbi rvale2osnxs, x1
+# CHECK-NO-XS: sys #4, c9, c5, #5, x1
[0x21,0x96,0x0e,0xd5]
+# CHECK: tlbi rvae3nxs, x1
+# CHECK-NO-XS: sys #6, c9, c6, #1, x1
[0xa1,0x96,0x0e,0xd5]
+# CHECK: tlbi rvale3nxs, x1
+# CHECK-NO-XS: sys #6, c9, c6, #5, x1
[0x21,0x92,0x0e,0xd5]
+# CHECK: tlbi rvae3isnxs, x1
+# CHECK-NO-XS: sys #6, c9, c2, #1, x1
[0xa1,0x92,0x0e,0xd5]
+# CHECK: tlbi rvale3isnxs, x1
+# CHECK-NO-XS: sys #6, c9, c2, #5, x1
[0x21,0x95,0x0e,0xd5]
+# CHECK: tlbi rvae3osnxs, x1
+# CHECK-NO-XS: sys #6, c9, c5, #1, x1
[0xa1,0x95,0x0e,0xd5]
-# CHECK: tlbi vmalle1osnxs
-# CHECK: tlbi vae1osnxs, x1
-# CHECK: tlbi aside1osnxs, x1
-# CHECK: tlbi vaae1osnxs, x1
-# CHECK: tlbi vale1osnxs, x1
-# CHECK: tlbi vaale1osnxs, x1
-# CHECK: tlbi ipas2e1osnxs, x1
-# CHECK: tlbi ipas2le1osnxs, x1
-# CHECK: tlbi vae2osnxs, x1
-# CHECK: tlbi vale2osnxs, x1
-# CHECK: tlbi vmalls12e1osnxs
-# CHECK: tlbi vae3osnxs, x1
-# CHECK: tlbi vale3osnxs, x1
-# CHECK: tlbi alle2osnxs
-# CHECK: tlbi alle1osnxs
-# CHECK: tlbi alle3osnxs
-# CHECK: tlbi rvae1nxs, x1
-# CHECK: tlbi rvaae1nxs, x1
-# CHECK: tlbi rvale1nxs, x1
-# CHECK: tlbi rvaale1nxs, x1
-# CHECK: tlbi rvae1isnxs, x1
-# CHECK: tlbi rvaae1isnxs, x1
-# CHECK: tlbi rvale1isnxs, x1
-# CHECK: tlbi rvaale1isnxs, x1
-# CHECK: tlbi rvae1osnxs, x1
-# CHECK: tlbi rvaae1osnxs, x1
-# CHECK: tlbi rvale1osnxs, x1
-# CHECK: tlbi rvaale1osnxs, x1
-# CHECK: tlbi ripas2e1isnxs, x1
-# CHECK: tlbi ripas2le1isnxs, x1
-# CHECK: tlbi ripas2e1nxs, x1
-# CHECK: tlbi ripas2le1nxs, x1
-# CHECK: tlbi ripas2e1osnxs, x1
-# CHECK: tlbi ripas2le1osnxs, x1
-# CHECK: tlbi rvae2nxs, x1
-# CHECK: tlbi rvale2nxs, x1
-# CHECK: tlbi rvae2isnxs, x1
-# CHECK: tlbi rvale2isnxs, x1
-# CHECK: tlbi rvae2osnxs, x1
-# CHECK: tlbi rvale2osnxs, x1
-# CHECK: tlbi rvae3nxs, x1
-# CHECK: tlbi rvale3nxs, x1
-# CHECK: tlbi rvae3isnxs, x1
-# CHECK: tlbi rvale3isnxs, x1
-# CHECK: tlbi rvae3osnxs, x1
-# CHECK: tlbi rvale3osnxs, x1
+# CHECK: tlbi rvale3osnxs, x1
+# CHECK-NO-XS: sys #6, c9, c5, #5, x1
# CHECK_NO_XS: sys #0, c9, c1, #0
# CHECK_NO_XS: sys #0, c9, c1, #1, x1
# CHECK_NO_XS: sys #0, c9, c1, #2, x1
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt b/llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt
index 9b2b86e410978..ec124010a527d 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt
@@ -1,30 +1,31 @@
+# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple=aarch64 -mattr=+nmi -disassemble %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mattr=+v8.8a -disassemble %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck %s --check-prefix=NO-NMI
[0x03,0x43,0x38,0xd5]
-# CHECK: mrs x3, ALLINT
-# NO-NMI: mrs x3, S3_0_C4_C3_0
+# CHECK: mrs x3, ALLINT
+# NO-NMI: mrs x3, S3_0_C4_C3_0
[0x06,0x43,0x18,0xd5]
-# CHECK: msr ALLINT, x6
-# NO-NMI: msr S3_0_C4_C3_0, x6
+# CHECK: msr ALLINT, x6
+# NO-NMI: msr S3_0_C4_C3_0, x6
[0x1f,0x40,0x01,0xd5]
-# CHECK: msr ALLINT, #0
-# NO-NMI: msr S0_1_C4_C0_0, xzr
+# CHECK: msr ALLINT, #0
+# NO-NMI: msr S0_1_C4_C0_0, xzr
[0x1f,0x41,0x01,0xd5]
-# CHECK: msr ALLINT, #1
-# NO-NMI: msr S0_1_C4_C1_0, xzr
+# CHECK: msr ALLINT, #1
+# NO-NMI: msr S0_1_C4_C1_0, xzr
# Regression test for a defect, where the bit-pattern, which should have allowed
# only ALLSTATE, allowed SPSel (and others).
[0xbf,0x51,0x00,0xd5]
-# CHECK: msr S0_0_C5_C1_5, xzr
-# NO-NMI: msr S0_0_C5_C1_5, xzr
+# CHECK: msr S0_0_C5_C1_5, xzr
+# NO-NMI: msr S0_0_C5_C1_5, xzr
[0xa7,0xc9,0x38,0xd5]
-# CHECK: mrs x7, ICC_NMIAR1_EL1
-# NO-NMI: mrs x7, S3_0_C12_C9_5
+# CHECK: mrs x7, ICC_NMIAR1_EL1
+# NO-NMI: mrs x7, S3_0_C12_C9_5
>From 202e15bc7c5f6f537adf8f5b8c3d5a0b900bb8ba Mon Sep 17 00:00:00 2001
From: Marian Lukac <Marian.Lukac at arm.com>
Date: Wed, 11 Mar 2026 21:22:02 +0000
Subject: [PATCH 03/12] Fix codegen for system reg move instructions, add
checks to parser to prevent incorrect system registers from being matched and
change tests to match new implementation
---
.../Target/AArch64/AArch64ISelDAGToDAG.cpp | 6 ++--
.../Target/AArch64/Utils/AArch64BaseInfo.cpp | 15 ++++++----
llvm/test/MC/AArch64/arm64-system-encoding.s | 22 +++++++++++---
llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s | 9 ++++++
llvm/test/MC/AArch64/armv9-mrrs.s | 8 +++++
llvm/test/MC/AArch64/armv9-msrr-diagnostics.s | 10 +++++++
llvm/test/MC/AArch64/armv9-msrr.s | 8 +++++
llvm/test/MC/AArch64/basic-a64-instructions.s | 4 ---
.../MC/Disassembler/AArch64/armv8.2a-uao.txt | 8 ++---
.../MC/Disassembler/AArch64/armv8.4a-dit.txt | 4 +--
.../AArch64/armv8.5a-dataproc.txt | 4 +--
.../MC/Disassembler/AArch64/armv8.5a-mte.txt | 2 +-
.../MC/Disassembler/AArch64/armv8.5a-sb.txt | 4 +--
.../MC/Disassembler/AArch64/armv8.5a-ssbs.txt | 8 ++---
.../MC/Disassembler/AArch64/armv8.7a-wfxt.txt | 6 ++--
.../MC/Disassembler/AArch64/armv8.7a-xs.txt | 29 ++++++++++---------
.../MC/Disassembler/AArch64/armv8.8a-nmi.txt | 12 ++------
.../AArch64/basic-a64-instructions.txt | 4 ---
18 files changed, 104 insertions(+), 59 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 092b6bf00396d..00b2ae8478ae1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -4155,8 +4155,10 @@ static int getIntOperandFromRegisterString(StringRef RegString) {
(void)AllIntFields;
// Need to combine the integer fields of the string into a single value
- // based on the bit encoding of MRS/MSR instruction.
- return (Ops[0] << 14) | (Ops[1] << 11) | (Ops[2] << 7) |
+ // based on the bit encoding of MRS/MSR instruction. We also mask Ops[0], as
+ // top bit as it is implicitly assumed to be 1 for MRS/MSR instruction and is
+ // not part of the encoding.
+ return ((Ops[0] & 0x1) << 14) | (Ops[1] << 11) | (Ops[2] << 7) |
(Ops[3] << 3) | (Ops[4]);
}
diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
index 556d2c32569b4..451c63707f956 100644
--- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
+++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
@@ -175,21 +175,26 @@ uint32_t AArch64SysReg::parseGenericRegister(StringRef Name) {
Ops[3].getAsInteger(10, CRn);
Ops[4].getAsInteger(10, CRm);
Ops[5].getAsInteger(10, Op2);
- Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
+ if (Op0 < 2)
+ return -1; // Op0 must be 2 or 3 for a valid system register.
+
+ // Top bit of Op0 is assumed to be 1.
+ Bits = ((Op0 & 0x1) << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
return Bits;
}
std::string AArch64SysReg::genericRegisterString(uint32_t Bits) {
- assert(Bits < 0x10000);
- uint32_t Op0 = (Bits >> 14) & 0x3;
+ assert(Bits < 0x8000);
+ uint32_t Op0 = (Bits >> 14) & 0x1;
uint32_t Op1 = (Bits >> 11) & 0x7;
uint32_t CRn = (Bits >> 7) & 0xf;
uint32_t CRm = (Bits >> 3) & 0xf;
uint32_t Op2 = Bits & 0x7;
- return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +
- utostr(CRm) + "_" + utostr(Op2);
+ // Add the top bit of Op0 back in.
+ return "S" + utostr(Op0 | 0x2) + "_" + utostr(Op1) + "_C" + utostr(CRn) +
+ "_C" + utostr(CRm) + "_" + utostr(Op2);
}
namespace llvm {
diff --git a/llvm/test/MC/AArch64/arm64-system-encoding.s b/llvm/test/MC/AArch64/arm64-system-encoding.s
index d38f3ac9871fe..762b64e109a08 100644
--- a/llvm/test/MC/AArch64/arm64-system-encoding.s
+++ b/llvm/test/MC/AArch64/arm64-system-encoding.s
@@ -165,8 +165,6 @@ foo:
msr TCR2_EL12, x3
msr TCR2_EL2, x3
msr S3_2_C11_C6_4, x1
- msr S0_0_C0_C0_0, x0
- msr S1_2_C3_C4_5, x2
; CHECK: msr ACTLR_EL1, x3 ; encoding: [0x23,0x10,0x18,0xd5]
; CHECK: msr ACTLR_EL12, x3 ; encoding: [0x23,0x10,0x1d,0xd5]
; CHECK: msr ACTLR_EL2, x3 ; encoding: [0x23,0x10,0x1c,0xd5]
@@ -274,8 +272,15 @@ foo:
; CHECK: msr TCR2_EL12, x3 ; encoding: [0x63,0x20,0x1d,0xd5]
; CHECK: msr TCR2_EL2, x3 ; encoding: [0x63,0x20,0x1c,0xd5]
; CHECK: msr S3_2_C11_C6_4, x1 ; encoding: [0x81,0xb6,0x1a,0xd5]
-; CHECK: msr S0_0_C0_C0_0, x0 ; encoding: [0x00,0x00,0x00,0xd5]
-; CHECK: msr S1_2_C3_C4_5, x2 ; encoding: [0xa2,0x34,0x0a,0xd5]
+
+// Invalid System register encodings
+ msr S0_0_C0_C0_0, x0
+ msr S1_2_C3_C4_5, x2
+ msr S4_2_C3_C4_5, x2
+; CHECK-ERRORS: :[[@LINE-3]]:7: error: expected writable system register or pstate
+; CHECK-ERRORS: :[[@LINE-3]]:7: error: expected writable system register or pstate
+; CHECK-ERRORS: :[[@LINE-3]]:7: error: expected writable system register or pstate
+
// Readonly system registers: writing to them gives an error
msr CURRENTEL, x3
@@ -764,3 +769,12 @@ foo:
; CHECK: mrs x0, AFSR1_EL1 ; encoding: [0x20,0x51,0x38,0xd5]
; CHECK: mrs x0, AFSR0_EL1 ; encoding: [0x00,0x51,0x38,0xd5]
; CHECK: mrs x0, REVIDR_EL1 ; encoding: [0xc0,0x00,0x38,0xd5]
+
+// Invalid System register encodings
+ mrs x3, S0_0_C0_C0_0
+ mrs x3, S1_2_C3_C4_5
+ mrs x3, S4_2_C3_C4_5
+; CHECK-ERRORS: :[[@LINE-3]]:11: error: expected readable system register
+; CHECK-ERRORS: :[[@LINE-3]]:11: error: expected readable system register
+; CHECK-ERRORS: :[[@LINE-3]]:11: error: expected readable system register
+
diff --git a/llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s b/llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s
index 4eb8861784653..cec724624b830 100644
--- a/llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s
+++ b/llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s
@@ -28,3 +28,12 @@ mrrs S3_0_c2_c0_1
mrrs S3_0_c2_c0_1, x0, x1
// CHECK-ERROR: error: expected first even register of a consecutive same-size even/odd register pair
+
+mrrs x0, x1, S0_0_c2_c0_1
+// CHECK-ERROR: error: expected readable system register
+
+mrrs x0, x1, S1_0_c2_c0_1
+// CHECK-ERROR: error: expected readable system register
+
+mrrs x0, x1, S4_0_c2_c0_1
+// CHECK-ERROR: error: expected readable system register
diff --git a/llvm/test/MC/AArch64/armv9-mrrs.s b/llvm/test/MC/AArch64/armv9-mrrs.s
index 253ae15708683..26bee51a30e8b 100644
--- a/llvm/test/MC/AArch64/armv9-mrrs.s
+++ b/llvm/test/MC/AArch64/armv9-mrrs.s
@@ -188,3 +188,11 @@ msrr VTTBR_EL2, x24, x25
msrr VTTBR_EL2, x26, x27
// CHECK-INST: msrr VTTBR_EL2, x26, x27
// CHECK-ENCODING: encoding: [0x1a,0x21,0x5c,0xd5]
+
+msrr S2_0_c2_c0_1, x26, x27
+// CHECK-INST: msrr S2_0_C2_C0_1, x26, x27
+// CHECK-ENCODING: encoding: [0x3a,0x20,0x50,0xd5]
+
+msrr S3_0_c2_c0_1, x26, x27
+// CHECK-INST: msrr TTBR1_EL1, x26, x27
+// CHECK-ENCODING: encoding: [0x3a,0x20,0x58,0xd5]
diff --git a/llvm/test/MC/AArch64/armv9-msrr-diagnostics.s b/llvm/test/MC/AArch64/armv9-msrr-diagnostics.s
index d49a3ee68b63f..cf52afcb05b49 100644
--- a/llvm/test/MC/AArch64/armv9-msrr-diagnostics.s
+++ b/llvm/test/MC/AArch64/armv9-msrr-diagnostics.s
@@ -28,3 +28,13 @@ msrr S3_0_c2_c0_1
msrr x0, x1, S3_0_c2_c0_1
// CHECK-ERROR: error: expected first even register of a consecutive same-size even/odd register pair
+
+msrr S0_0_c2_c0_1, x26, x27
+// CHECK-ERROR: error: expected writable system register or pstate
+
+
+msrr S1_0_c2_c0_1, x26, x27
+// CHECK-ERROR: error: expected writable system register or pstate
+
+msrr S4_0_c2_c0_1, x26, x27
+// CHECK-ERROR: error: expected writable system register or pstate
diff --git a/llvm/test/MC/AArch64/armv9-msrr.s b/llvm/test/MC/AArch64/armv9-msrr.s
index 3b2be6fdeea69..3e117bfb8f5d0 100644
--- a/llvm/test/MC/AArch64/armv9-msrr.s
+++ b/llvm/test/MC/AArch64/armv9-msrr.s
@@ -100,3 +100,11 @@ msrr VTTBR_EL2, x24, x25
msrr VTTBR_EL2, x26, x27
// CHECK-INST: msrr VTTBR_EL2, x26, x27
// CHECK-ENCODING: encoding: [0x1a,0x21,0x5c,0xd5]
+
+msrr S2_0_c2_c0_1, x26, x27
+// CHECK-INST: msrr S2_0_C2_C0_1, x26, x27
+// CHECK-ENCODING: encoding: [0x3a,0x20,0x50,0xd5]
+
+msrr S3_0_c2_c0_1, x26, x27
+// CHECK-INST: msrr TTBR1_EL1, x26, x27
+// CHECK-ENCODING: encoding: [0x3a,0x20,0x58,0xd5]
diff --git a/llvm/test/MC/AArch64/basic-a64-instructions.s b/llvm/test/MC/AArch64/basic-a64-instructions.s
index b2ec5b6ac3678..8bd86ccc214ab 100644
--- a/llvm/test/MC/AArch64/basic-a64-instructions.s
+++ b/llvm/test/MC/AArch64/basic-a64-instructions.s
@@ -4939,16 +4939,12 @@ _func:
mrs x12, s3_7_c15_c1_5
mrs x13, s3_2_c11_c15_7
- mrs x14, s1_3_c9_c2_1
msr s3_0_c15_c0_0, x12
msr s3_7_c11_c13_7, x5
- msr s1_3_c9_c2_1, x4
// CHECK: mrs x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}} // encoding: [0xac,0xf1,0x3f,0xd5]
// CHECK: mrs x13, {{s3_2_c11_c15_7|S3_2_C11_C15_7}} // encoding: [0xed,0xbf,0x3a,0xd5]
-// CHECK: mrs x14, {{s1_3_c9_c2_1|S1_3_C9_C2_1}} // encoding: [0x2e,0x92,0x2b,0xd5]
// CHECK: msr {{s3_0_c15_c0_0|S3_0_C15_C0_0}}, x12 // encoding: [0x0c,0xf0,0x18,0xd5]
// CHECK: msr {{s3_7_c11_c13_7|S3_7_C11_C13_7}}, x5 // encoding: [0xe5,0xbd,0x1f,0xd5]
-// CHECK: msr {{s1_3_c9_c2_1|S1_3_C9_C2_1}}, x4 // encoding: [0x24,0x92,0x0b,0xd5]
//------------------------------------------------------------------------------
// Unconditional branch (immediate)
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.2a-uao.txt b/llvm/test/MC/Disassembler/AArch64/armv8.2a-uao.txt
index 2e45be4b342fe..25bf009a33dfe 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.2a-uao.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.2a-uao.txt
@@ -1,16 +1,16 @@
# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple aarch64-none-linux-gnu --disassemble < %s 2>&1 | FileCheck --check-prefix=NO_V82A %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu --disassemble < %s 2>&1 | FileCheck --check-prefix=NO_V82A %s
[0x7f,0x40,0x00,0xd5]
# CHECK: msr UAO, #0
-# NO_V82A: msr S0_0_C4_C0_3, xzr
+# NO_V82A: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x7f,0x41,0x00,0xd5]
# CHECK: msr UAO, #1
-# NO_V82A: msr S0_0_C4_C1_3, xzr
+# NO_V82A: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x7f,0x4f,0x00,0xd5]
# CHECK: msr UAO, #15
-# NO_V82A: msr S0_0_C4_C15_3, xzr
+# NO_V82A: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x81,0x42,0x18,0xd5]
# CHECK: msr UAO, x1
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt b/llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt
index b923ed8515ffa..b12fdf66faad5 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt
@@ -1,11 +1,11 @@
# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
[0x5f,0x41,0x03,0xd5]
# CHECK: msr DIT, #1
-# CHECK-NO-V84: msr S0_3_C4_C1_2, xzr
+# CHECK-NO-V84: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xa0,0x42,0x1b,0xd5]
# CHECK: msr DIT, x0
# CHECK-NO-V84: msr S3_3_C4_C2_5, x0
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-dataproc.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-dataproc.txt
index 96eb158d5a3a0..81d5b39912b20 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-dataproc.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-dataproc.txt
@@ -5,10 +5,10 @@
# Flag manipulation
[0x3f,0x40,0x00,0xd5]
# CHECK: xaflag
-# CHECK-NOV85: msr S0_0_C4_C0_1, xzr
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x5f,0x40,0x00,0xd5]
# CHECK: axflag
-# CHECK-NOV85: msr S0_0_C4_C0_2, xzr
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
index 2f9859ee248c9..af42c6e177141 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
@@ -474,7 +474,7 @@
[0x9f,0x40,0x03,0xd5]
# CHECK: msr TCO, #0
-# NOMTE: msr S0_3_C4_C0_4, xzr
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xe0,0x42,0x1b,0xd5]
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt
index d3d7e8e6112f2..4e5fff66eb6f2 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt
@@ -1,10 +1,10 @@
# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+sb -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+v8.5a -disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=-sb -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+# RUN: not llvm-mc -triple=aarch64-none-linux-gnu -mattr=-sb -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
# New reg
0xff 0x30 0x03 0xd5
# CHECK: sb
-# NOSB: msr S0_3_C3_C0_7, xzr
+# NOSB: :[[@LINE-2]]:1: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt
index 2ff24ee8c567f..ca4f0063a6b57 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt
@@ -1,14 +1,14 @@
# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple=aarch64 -mattr=+ssbs -disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s --check-prefix=NOSPECID
+# RUN: not llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID
# RUN: llvm-mc -triple=aarch64 -mcpu=cortex-a76 -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mcpu=cortex-a76ae -disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s | FileCheck %s --check-prefix=NOSPECID
-# RUN: llvm-mc -triple=aarch64 -mattr=-ssbs -disassemble < %s | FileCheck %s --check-prefix=NOSPECID
+# RUN: not llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID
+# RUN: not llvm-mc -triple=aarch64 -mattr=-ssbs -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID
[0x3f 0x41 0x03 0xd5]
# CHECK: msr SSBS, #1
-# NOSPECID: msr S0_3_C4_C1_1, xzr
+# NOSPECID: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xc3 0x42 0x1b 0xd5]
# CHECK: msr SSBS, x3
# NOSPECID: msr S3_3_C4_C2_6, x3
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt b/llvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt
index 58ce8e9aa7316..e00727a99fb6f 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt
@@ -1,12 +1,12 @@
# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple=aarch64 -mattr=+wfxt -disassemble %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mattr=+v8.7a -disassemble %s | FileCheck %s
-# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck --check-prefix=CHECK-NO-WFxT %s
+# RUN: not llvm-mc -triple=aarch64 -disassemble %s 2>&1 | FileCheck --check-prefix=CHECK-NO-WFxT %s
[0x11,0x10,0x03,0xd5]
# CHECK: wfet x17
-# CHECK-NO-WFxT: msr S0_3_C1_C0_0, x17
+# CHECK-NO-WFxT: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x23,0x10,0x03,0xd5]
# CHECK: wfit x3
-# CHECK-NO-WFxT: msr S0_3_C1_C0_1, x3
+# CHECK-NO-WFxT: :[[@LINE-2]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt b/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
index 7bf36abe68e29..0fafc59aa6295 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
@@ -1,30 +1,33 @@
# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
-# RUN: llvm-mc -triple=aarch64 -mattr=+v8.4a,+xs -disassemble %s | FileCheck %s
-# RUN: llvm-mc -triple=aarch64 -mattr=+v8.7a -disassemble %s | FileCheck %s
-# RUN: llvm-mc -triple=aarch64 -mattr=+v8.4a -disassemble %s | FileCheck --check-prefix=CHECK-NO-XS %s
+# RUN: not llvm-mc -triple=aarch64 -mattr=+v8.4a,+xs -disassemble %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=aarch64 -mattr=+v8.7a -disassemble %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=aarch64 -mattr=+v8.4a -disassemble %s 2>&1 | FileCheck --check-prefix=CHECK-NO-XS %s
[0x3f,0x32,0x03,0xd5]
# CHECK: dsb oshnxs
-# CHECK-NO-XS: msr S0_3_C3_C2_1, xzr
+# CHECK-NO-XS: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x3f,0x36,0x03,0xd5]
# CHECK: dsb nshnxs
-# CHECK-NO-XS: msr S0_3_C3_C6_1, xzr
+# CHECK-NO-XS: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x3f,0x3a,0x03,0xd5]
# CHECK: dsb ishnxs
-# CHECK-NO-XS: msr S0_3_C3_C10_1, xzr
+# CHECK-NO-XS: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x3f,0x3e,0x03,0xd5]
# CHECK: dsb synxs
-# CHECK-NO-XS: msr S0_3_C3_C14_1, xzr
+# CHECK-NO-XS: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x3f,0x30,0x03,0xd5]
-# CHECK: msr S0_3_C3_C0_1, xzr
-# CHECK-NO-XS: msr S0_3_C3_C0_1, xzr
+# CHECK: :[[@LINE-1]]:2: warning: invalid instruction encoding
+# CHECK-NO-XS: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
[0x3f,0x35,0x03,0xd5]
-# CHECK: msr S0_3_C3_C5_1, xzr
-# CHECK-NO-XS: msr S0_3_C3_C5_1, xzr
+# CHECK: :[[@LINE-1]]:2: warning: invalid instruction encoding
+# CHECK-NO-XS: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
[0x3f,0x3f,0x03,0xd5]
-# CHECK: msr S0_3_C3_C15_1, xzr
-# CHECK-NO-XS: msr S0_3_C3_C15_1, xzr
+# CHECK: :[[@LINE-1]]:2: warning: invalid instruction encoding
+# CHECK-NO-XS: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
[0x21,0x90,0x0c,0xd5]
# CHECK: tlbi ipas2e1isnxs, x1
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt b/llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt
index ec124010a527d..d03edbd135e44 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple=aarch64 -mattr=+nmi -disassemble %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mattr=+v8.8a -disassemble %s | FileCheck %s
-# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck %s --check-prefix=NO-NMI
+# RUN: not llvm-mc -triple=aarch64 -disassemble %s 2>&1| FileCheck %s --check-prefix=NO-NMI
[0x03,0x43,0x38,0xd5]
@@ -14,17 +14,11 @@
[0x1f,0x40,0x01,0xd5]
# CHECK: msr ALLINT, #0
-# NO-NMI: msr S0_1_C4_C0_0, xzr
+# NO-NMI: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x1f,0x41,0x01,0xd5]
# CHECK: msr ALLINT, #1
-# NO-NMI: msr S0_1_C4_C1_0, xzr
-
-# Regression test for a defect, where the bit-pattern, which should have allowed
-# only ALLSTATE, allowed SPSel (and others).
-[0xbf,0x51,0x00,0xd5]
-# CHECK: msr S0_0_C5_C1_5, xzr
-# NO-NMI: msr S0_0_C5_C1_5, xzr
+# NO-NMI: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0xa7,0xc9,0x38,0xd5]
# CHECK: mrs x7, ICC_NMIAR1_EL1
diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
index 5ffabfc692ad1..08ab86c14a69d 100644
--- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
+++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
@@ -4412,16 +4412,12 @@
# CHECK: mrs x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}}
# CHECK: mrs x13, {{s3_2_c11_c15_7|S3_2_C11_C15_7}}
-# CHECK: mrs xzr, {{s0_0_c4_c0_0|S0_0_C4_C0_0}}
# CHECK: msr {{s3_0_c15_c0_0|S3_0_C15_C0_0}}, x12
# CHECK: msr {{s3_7_c11_c13_7|S3_7_C11_C13_7}}, x5
-# CHECK: msr {{s0_0_c4_c0_0|S0_0_C4_C0_0}}, xzr
0xac 0xf1 0x3f 0xd5
0xed 0xbf 0x3a 0xd5
-0x1f 0x40 0x20 0xd5
0x0c 0xf0 0x18 0xd5
0xe5 0xbd 0x1f 0xd5
-0x1f 0x40 0x00 0xd5
#------------------------------------------------------------------------------
# Test and branch (immediate)
>From d5d9f737d505b7b850fcb2659f516778b7c56396 Mon Sep 17 00:00:00 2001
From: Marian Lukac <Marian.Lukac at arm.com>
Date: Wed, 11 Mar 2026 21:38:15 +0000
Subject: [PATCH 04/12] Adjust test
---
.../Disassembler/AArch64/armv8.5a-dataproc.txt | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-dataproc.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-dataproc.txt
index 81d5b39912b20..706c2bdd631ca 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-dataproc.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-dataproc.txt
@@ -2,16 +2,6 @@
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.5a --disassemble < %s | FileCheck %s
# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.5a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOV85
-# Flag manipulation
-[0x3f,0x40,0x00,0xd5]
-# CHECK: xaflag
-# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
-[0x5f,0x40,0x00,0xd5]
-# CHECK: axflag
-# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
-
-
-
# FP-to-int rounding, scalar
[0x20,0x40,0x28,0x1e]
# CHECK: frint32z s0, s1
@@ -75,3 +65,11 @@
[0xe6,0xf8,0x21,0x6e]
# CHECK: frint64x v6.4s, v7.4s
# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
+# Flag manipulation
+[0x3f,0x40,0x00,0xd5]
+# CHECK: xaflag
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
+[0x5f,0x40,0x00,0xd5]
+# CHECK: axflag
+# CHECK-NOV85: :[[@LINE-2]]:2: warning: invalid instruction encoding
>From 61dc6c9a2a32f6002cf7952acbfa8cc7ba7eb588 Mon Sep 17 00:00:00 2001
From: Marian Lukac <Marian.Lukac at arm.com>
Date: Wed, 11 Mar 2026 22:26:59 +0000
Subject: [PATCH 05/12] Remove extra checklines
---
.../MC/Disassembler/AArch64/armv8.7a-xs.txt | 80 -------------------
1 file changed, 80 deletions(-)
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt b/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
index 0fafc59aa6295..a86a9148d70d9 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
@@ -125,38 +125,6 @@
[0xe1,0x97,0x08,0xd5]
# CHECK: tlbi vaale1nxs, x1
# CHECK-NO-XS: sys #0, c9, c7, #7, x1
-# CHECK_NO_XS: sys #4, c9, c0, #1, x1
-# CHECK_NO_XS: sys #4, c9, c0, #5, x1
-# CHECK_NO_XS: sys #0, c9, c3, #0
-# CHECK_NO_XS: sys #4, c9, c3, #0
-# CHECK_NO_XS: sys #6, c9, c3, #0
-# CHECK_NO_XS: sys #0, c9, c3, #1, x1
-# CHECK_NO_XS: sys #4, c9, c3, #1, x1
-# CHECK_NO_XS: sys #6, c9, c3, #1, x1
-# CHECK_NO_XS: sys #0, c9, c3, #2, x1
-# CHECK_NO_XS: sys #0, c9, c3, #3, x1
-# CHECK_NO_XS: sys #4, c9, c3, #4
-# CHECK_NO_XS: sys #0, c9, c3, #5, x1
-# CHECK_NO_XS: sys #4, c9, c3, #5, x1
-# CHECK_NO_XS: sys #6, c9, c3, #5, x1
-# CHECK_NO_XS: sys #4, c9, c3, #6
-# CHECK_NO_XS: sys #0, c9, c3, #7, x1
-# CHECK_NO_XS: sys #4, c9, c4, #1, x1
-# CHECK_NO_XS: sys #4, c9, c4, #5, x1
-# CHECK_NO_XS: sys #0, c9, c7, #0
-# CHECK_NO_XS: sys #4, c9, c7, #0
-# CHECK_NO_XS: sys #6, c9, c7, #0
-# CHECK_NO_XS: sys #0, c9, c7, #1, x1
-# CHECK_NO_XS: sys #4, c9, c7, #1, x1
-# CHECK_NO_XS: sys #6, c9, c7, #1, x1
-# CHECK_NO_XS: sys #0, c9, c7, #2, x1
-# CHECK_NO_XS: sys #0, c9, c7, #3, x1
-# CHECK_NO_XS: sys #4, c9, c7, #4
-# CHECK_NO_XS: sys #0, c9, c7, #5, x1
-# CHECK_NO_XS: sys #4, c9, c7, #5, x1
-# CHECK_NO_XS: sys #6, c9, c7, #5, x1
-# CHECK_NO_XS: sys #4, c9, c7, #6
-# CHECK_NO_XS: sys #0, c9, c7, #7, x1
[0x1f,0x91,0x08,0xd5]
# CHECK: tlbi vmalle1osnxs
@@ -296,51 +264,3 @@
[0xa1,0x95,0x0e,0xd5]
# CHECK: tlbi rvale3osnxs, x1
# CHECK-NO-XS: sys #6, c9, c5, #5, x1
-# CHECK_NO_XS: sys #0, c9, c1, #0
-# CHECK_NO_XS: sys #0, c9, c1, #1, x1
-# CHECK_NO_XS: sys #0, c9, c1, #2, x1
-# CHECK_NO_XS: sys #0, c9, c1, #3, x1
-# CHECK_NO_XS: sys #0, c9, c1, #5, x1
-# CHECK_NO_XS: sys #0, c9, c1, #7, x1
-# CHECK_NO_XS: sys #4, c9, c4, #0, x1
-# CHECK_NO_XS: sys #4, c9, c4, #4, x1
-# CHECK_NO_XS: sys #4, c9, c1, #1, x1
-# CHECK_NO_XS: sys #4, c9, c1, #5, x1
-# CHECK_NO_XS: sys #4, c9, c1, #6
-# CHECK_NO_XS: sys #6, c9, c1, #1, x1
-# CHECK_NO_XS: sys #6, c9, c1, #5, x1
-# CHECK_NO_XS: sys #4, c9, c1, #0
-# CHECK_NO_XS: sys #4, c9, c1, #4
-# CHECK_NO_XS: sys #6, c9, c1, #0
-# CHECK_NO_XS: sys #0, c9, c6, #1, x1
-# CHECK_NO_XS: sys #0, c9, c6, #3, x1
-# CHECK_NO_XS: sys #0, c9, c6, #5, x1
-# CHECK_NO_XS: sys #0, c9, c6, #7, x1
-# CHECK_NO_XS: sys #0, c9, c2, #1, x1
-# CHECK_NO_XS: sys #0, c9, c2, #3, x1
-# CHECK_NO_XS: sys #0, c9, c2, #5, x1
-# CHECK_NO_XS: sys #0, c9, c2, #7, x1
-# CHECK_NO_XS: sys #0, c9, c5, #1, x1
-# CHECK_NO_XS: sys #0, c9, c5, #3, x1
-# CHECK_NO_XS: sys #0, c9, c5, #5, x1
-# CHECK_NO_XS: sys #0, c9, c5, #7, x1
-# CHECK_NO_XS: sys #4, c9, c0, #2, x1
-# CHECK_NO_XS: sys #4, c9, c0, #6, x1
-# CHECK_NO_XS: sys #4, c9, c4, #2, x1
-# CHECK_NO_XS: sys #4, c9, c4, #6, x1
-# CHECK_NO_XS: sys #4, c9, c4, #3, x1
-# CHECK_NO_XS: sys #4, c9, c4, #7, x1
-# CHECK_NO_XS: sys #4, c9, c6, #1, x1
-# CHECK_NO_XS: sys #4, c9, c6, #5, x1
-# CHECK_NO_XS: sys #4, c9, c2, #1, x1
-# CHECK_NO_XS: sys #4, c9, c2, #5, x1
-# CHECK_NO_XS: sys #4, c9, c5, #1, x1
-# CHECK_NO_XS: sys #4, c9, c5, #5, x1
-# CHECK_NO_XS: sys #6, c9, c6, #1, x1
-# CHECK_NO_XS: sys #6, c9, c6, #5, x1
-# CHECK_NO_XS: sys #6, c9, c2, #1, x1
-# CHECK_NO_XS: sys #6, c9, c2, #5, x1
-# CHECK_NO_XS: sys #6, c9, c5, #1, x1
-# CHECK_NO_XS: sys #6, c9, c5, #5, x1
-# CHECK_NO_XS: sys #0, c9, c1, #0
-# CHECK_NO_XS: sys #4, c9, c0, #1, x1
>From 8c6be5f3e1cdf470dc242b9f1be274c2075a71f2 Mon Sep 17 00:00:00 2001
From: Marian Lukac <Marian.Lukac at arm.com>
Date: Wed, 11 Mar 2026 20:54:38 +0000
Subject: [PATCH 06/12] comment move
---
llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
index af42c6e177141..24b9ff1ae6786 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
@@ -501,9 +501,7 @@
[0x27,0x56,0x18,0xd5]
# CHECK: msr TFSRE0_EL1, x7
# NOMTE: msr S3_0_C5_C6_1, x7
+# GMID_EL1 is read only
[0x88,0x00,0x19,0xd5]
# CHECK: msr S3_1_C0_C0_4, x8
# NOMTE: msr S3_1_C0_C0_4, x8
-
-# GMID_EL1 is read only
-
>From b19a2c301a1e1413e4083406843aae0643e7ebae Mon Sep 17 00:00:00 2001
From: Marian Lukac <Marian.Lukac at arm.com>
Date: Wed, 11 Mar 2026 22:40:45 +0000
Subject: [PATCH 07/12] Fix failing tests
---
.../test/CodeGen/AArch64/aarch64-sysreg128.ll | 10 +-
llvm/test/CodeGen/AArch64/special-reg.ll | 6 +-
.../MC/Disassembler/AArch64/armv8.5a-mte.txt | 126 +++++++++---------
.../MC/Disassembler/AArch64/armv8.5a-sb.txt | 2 +-
.../MC/Disassembler/AArch64/armv8.7a-xs.txt | 24 ++--
.../MC/Disassembler/AArch64/armv8.8a-nmi.txt | 15 +--
6 files changed, 88 insertions(+), 95 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/aarch64-sysreg128.ll b/llvm/test/CodeGen/AArch64/aarch64-sysreg128.ll
index 7f20b5e5ee4df..b5fc00f3e3207 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-sysreg128.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-sysreg128.ll
@@ -5,12 +5,12 @@
define i128 @test_rsr128() #0 {
; CHECK-LE-LABEL: test_rsr128:
; CHECK-LE: // %bb.0: // %entry
-; CHECK-LE-NEXT: mrrs x0, x1, S1_2_C3_C4_5
+; CHECK-LE-NEXT: mrrs x0, x1, S3_2_C3_C4_5
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: test_rsr128:
; CHECK-BE: // %bb.0: // %entry
-; CHECK-BE-NEXT: mrrs x2, x3, S1_2_C3_C4_5
+; CHECK-BE-NEXT: mrrs x2, x3, S3_2_C3_C4_5
; CHECK-BE-NEXT: mov x0, x3
; CHECK-BE-NEXT: mov x1, x2
; CHECK-BE-NEXT: ret
@@ -26,14 +26,14 @@ define void @test_wsr128(i128 noundef %v) #0 {
; CHECK-LE: // %bb.0: // %entry
; CHECK-LE-NEXT: // kill: def $x1 killed $x1 killed $x0_x1 def $x0_x1
; CHECK-LE-NEXT: // kill: def $x0 killed $x0 killed $x0_x1 def $x0_x1
-; CHECK-LE-NEXT: msrr S1_2_C3_C4_5, x0, x1
+; CHECK-LE-NEXT: msrr S3_2_C3_C4_5, x0, x1
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: test_wsr128:
; CHECK-BE: // %bb.0: // %entry
; CHECK-BE-NEXT: mov x2, x1
; CHECK-BE-NEXT: mov x3, x0
-; CHECK-BE-NEXT: msrr S1_2_C3_C4_5, x2, x3
+; CHECK-BE-NEXT: msrr S3_2_C3_C4_5, x2, x3
; CHECK-BE-NEXT: ret
entry:
call void @llvm.write_register.i128(metadata !1, i128 %v)
@@ -45,4 +45,4 @@ declare void @llvm.write_register.i128(metadata, i128) #1
attributes #0 = { noinline nounwind }
attributes #1 = { nounwind }
-!1 = !{!"1:2:3:4:5"}
+!1 = !{!"3:2:3:4:5"}
diff --git a/llvm/test/CodeGen/AArch64/special-reg.ll b/llvm/test/CodeGen/AArch64/special-reg.ll
index 7c02d0b2e1de3..81add608083d6 100644
--- a/llvm/test/CodeGen/AArch64/special-reg.ll
+++ b/llvm/test/CodeGen/AArch64/special-reg.ll
@@ -3,7 +3,7 @@
define i64 @read_encoded_register() nounwind {
entry:
; CHECK-LABEL: read_encoded_register:
-; CHECK: mrs x0, S1_2_C3_C4_5
+; CHECK: mrs x0, S3_2_C3_C4_5
%reg = call i64 @llvm.read_register.i64(metadata !0)
ret i64 %reg
}
@@ -19,7 +19,7 @@ entry:
define void @write_encoded_register(i64 %x) nounwind {
entry:
; CHECK-LABEL: write_encoded_register:
-; CHECK: msr S1_2_C3_C4_5, x0
+; CHECK: msr S3_2_C3_C4_5, x0
call void @llvm.write_register.i64(metadata !0, i64 %x)
ret void
}
@@ -43,6 +43,6 @@ entry:
declare i64 @llvm.read_register.i64(metadata) nounwind
declare void @llvm.write_register.i64(metadata, i64) nounwind
-!0 = !{!"1:2:3:4:5"}
+!0 = !{!"3:2:3:4:5"}
!1 = !{!"daif"}
!2 = !{!"daifset"}
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
index 24b9ff1ae6786..75e013eff2250 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
@@ -383,7 +383,67 @@
# CHECK: stzgm xzr, [x2]
# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
+[0x9f,0x40,0x03,0xd5]
+# CHECK: msr TCO, #0
+# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0xe0,0x42,0x1b,0xd5]
+# CHECK: msr TCO, x0
+# NOMTE: msr S3_3_C4_C2_7, x0
+[0xc1,0x10,0x18,0xd5]
+# CHECK: msr GCR_EL1, x1
+# NOMTE: msr S3_0_C1_C0_6, x1
+[0xa2,0x10,0x18,0xd5]
+# CHECK: msr RGSR_EL1, x2
+# NOMTE: msr S3_0_C1_C0_5, x2
+[0x03,0x56,0x18,0xd5]
+# CHECK: msr TFSR_EL1, x3
+# NOMTE: msr S3_0_C5_C6_0, x3
+[0x04,0x56,0x1c,0xd5]
+# CHECK: msr TFSR_EL2, x4
+# NOMTE: msr S3_4_C5_C6_0, x4
+[0x05,0x56,0x1e,0xd5]
+# CHECK: msr TFSR_EL3, x5
+# NOMTE: msr S3_6_C5_C6_0, x5
+[0x06,0x56,0x1d,0xd5]
+# CHECK: msr TFSR_EL12, x6
+# NOMTE: msr S3_5_C5_C6_0, x6
+[0x27,0x56,0x18,0xd5]
+# CHECK: msr TFSRE0_EL1, x7
+# NOMTE: msr S3_0_C5_C6_1, x7
+# GMID_EL1 is read only
+[0x88,0x00,0x19,0xd5]
+# CHECK: msr S3_1_C0_C0_4, x8
+# NOMTE: msr S3_1_C0_C0_4, x8
+
+[0xe0,0x42,0x3b,0xd5]
+# CHECK: mrs x0, TCO
+# NOMTE: mrs x0, S3_3_C4_C2_7
+[0xc1,0x10,0x38,0xd5]
+# CHECK: mrs x1, GCR_EL1
+# NOMTE: mrs x1, S3_0_C1_C0_6
+[0xa2,0x10,0x38,0xd5]
+# CHECK: mrs x2, RGSR_EL1
+# NOMTE: mrs x2, S3_0_C1_C0_5
+[0x03,0x56,0x38,0xd5]
+# CHECK: mrs x3, TFSR_EL1
+# NOMTE: mrs x3, S3_0_C5_C6_0
+[0x04,0x56,0x3c,0xd5]
+# CHECK: mrs x4, TFSR_EL2
+# NOMTE: mrs x4, S3_4_C5_C6_0
+[0x05,0x56,0x3e,0xd5]
+# CHECK: mrs x5, TFSR_EL3
+# NOMTE: mrs x5, S3_6_C5_C6_0
+[0x06,0x56,0x3d,0xd5]
+# CHECK: mrs x6, TFSR_EL12
+# NOMTE: mrs x6, S3_5_C5_C6_0
+[0x27,0x56,0x38,0xd5]
+# CHECK: mrs x7, TFSRE0_EL1
+# NOMTE: mrs x7, S3_0_C5_C6_1
+[0x88,0x00,0x39,0xd5]
+# CHECK: mrs x8, GMID_EL1
+# NOMTE: mrs x8, S3_1_C0_C0_4
[0x60,0x76,0x08,0xd5]
# CHECK: dc igvac, x0
@@ -439,69 +499,3 @@
[0x91,0x74,0x0b,0xd5]
# CHECK: dc gzva, x17
# NOMTE: sys #3, c7, c4, #4, x17
-
-
-
-[0xe0,0x42,0x3b,0xd5]
-# CHECK: mrs x0, TCO
-# NOMTE: mrs x0, S3_3_C4_C2_7
-[0xc1,0x10,0x38,0xd5]
-# CHECK: mrs x1, GCR_EL1
-# NOMTE: mrs x1, S3_0_C1_C0_6
-[0xa2,0x10,0x38,0xd5]
-# CHECK: mrs x2, RGSR_EL1
-# NOMTE: mrs x2, S3_0_C1_C0_5
-[0x03,0x56,0x38,0xd5]
-# CHECK: mrs x3, TFSR_EL1
-# NOMTE: mrs x3, S3_0_C5_C6_0
-[0x04,0x56,0x3c,0xd5]
-# CHECK: mrs x4, TFSR_EL2
-# NOMTE: mrs x4, S3_4_C5_C6_0
-[0x05,0x56,0x3e,0xd5]
-# CHECK: mrs x5, TFSR_EL3
-# NOMTE: mrs x5, S3_6_C5_C6_0
-[0x06,0x56,0x3d,0xd5]
-# CHECK: mrs x6, TFSR_EL12
-# NOMTE: mrs x6, S3_5_C5_C6_0
-[0x27,0x56,0x38,0xd5]
-# CHECK: mrs x7, TFSRE0_EL1
-# NOMTE: mrs x7, S3_0_C5_C6_1
-[0x88,0x00,0x39,0xd5]
-# CHECK: mrs x8, GMID_EL1
-# NOMTE: mrs x8, S3_1_C0_C0_4
-
-
-
-[0x9f,0x40,0x03,0xd5]
-# CHECK: msr TCO, #0
-# NOMTE: :[[@LINE-2]]:2: warning: invalid instruction encoding
-
-
-[0xe0,0x42,0x1b,0xd5]
-# CHECK: msr TCO, x0
-# NOMTE: msr S3_3_C4_C2_7, x0
-[0xc1,0x10,0x18,0xd5]
-# CHECK: msr GCR_EL1, x1
-# NOMTE: msr S3_0_C1_C0_6, x1
-[0xa2,0x10,0x18,0xd5]
-# CHECK: msr RGSR_EL1, x2
-# NOMTE: msr S3_0_C1_C0_5, x2
-[0x03,0x56,0x18,0xd5]
-# CHECK: msr TFSR_EL1, x3
-# NOMTE: msr S3_0_C5_C6_0, x3
-[0x04,0x56,0x1c,0xd5]
-# CHECK: msr TFSR_EL2, x4
-# NOMTE: msr S3_4_C5_C6_0, x4
-[0x05,0x56,0x1e,0xd5]
-# CHECK: msr TFSR_EL3, x5
-# NOMTE: msr S3_6_C5_C6_0, x5
-[0x06,0x56,0x1d,0xd5]
-# CHECK: msr TFSR_EL12, x6
-# NOMTE: msr S3_5_C5_C6_0, x6
-[0x27,0x56,0x18,0xd5]
-# CHECK: msr TFSRE0_EL1, x7
-# NOMTE: msr S3_0_C5_C6_1, x7
-# GMID_EL1 is read only
-[0x88,0x00,0x19,0xd5]
-# CHECK: msr S3_1_C0_C0_4, x8
-# NOMTE: msr S3_1_C0_C0_4, x8
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt
index 4e5fff66eb6f2..be6fb013ea857 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+sb -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+v8.5a -disassemble < %s | FileCheck %s
-# RUN: not llvm-mc -triple=aarch64-none-linux-gnu -mattr=-sb -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=-sb -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
# New reg
0xff 0x30 0x03 0xd5
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt b/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
index a86a9148d70d9..c05d9dda33efb 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
@@ -3,6 +3,18 @@
# RUN: not llvm-mc -triple=aarch64 -mattr=+v8.7a -disassemble %s 2>&1 | FileCheck %s
# RUN: not llvm-mc -triple=aarch64 -mattr=+v8.4a -disassemble %s 2>&1 | FileCheck --check-prefix=CHECK-NO-XS %s
+[0x3f,0x30,0x03,0xd5]
+# CHECK: :[[@LINE-1]]:2: warning: invalid instruction encoding
+# CHECK-NO-XS: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x3f,0x35,0x03,0xd5]
+# CHECK: :[[@LINE-1]]:2: warning: invalid instruction encoding
+# CHECK-NO-XS: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x3f,0x3f,0x03,0xd5]
+# CHECK: :[[@LINE-1]]:2: warning: invalid instruction encoding
+# CHECK-NO-XS: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
[0x3f,0x32,0x03,0xd5]
# CHECK: dsb oshnxs
# CHECK-NO-XS: :[[@LINE-2]]:2: warning: invalid instruction encoding
@@ -16,18 +28,6 @@
# CHECK: dsb synxs
# CHECK-NO-XS: :[[@LINE-2]]:2: warning: invalid instruction encoding
-[0x3f,0x30,0x03,0xd5]
-# CHECK: :[[@LINE-1]]:2: warning: invalid instruction encoding
-# CHECK-NO-XS: :[[@LINE-2]]:2: warning: invalid instruction encoding
-
-[0x3f,0x35,0x03,0xd5]
-# CHECK: :[[@LINE-1]]:2: warning: invalid instruction encoding
-# CHECK-NO-XS: :[[@LINE-2]]:2: warning: invalid instruction encoding
-
-[0x3f,0x3f,0x03,0xd5]
-# CHECK: :[[@LINE-1]]:2: warning: invalid instruction encoding
-# CHECK-NO-XS: :[[@LINE-2]]:2: warning: invalid instruction encoding
-
[0x21,0x90,0x0c,0xd5]
# CHECK: tlbi ipas2e1isnxs, x1
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt b/llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt
index d03edbd135e44..e739420ecd736 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt
@@ -3,6 +3,13 @@
# RUN: llvm-mc -triple=aarch64 -mattr=+v8.8a -disassemble %s | FileCheck %s
# RUN: not llvm-mc -triple=aarch64 -disassemble %s 2>&1| FileCheck %s --check-prefix=NO-NMI
+[0x1f,0x40,0x01,0xd5]
+# CHECK: msr ALLINT, #0
+# NO-NMI: :[[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x1f,0x41,0x01,0xd5]
+# CHECK: msr ALLINT, #1
+# NO-NMI: :[[@LINE-2]]:2: warning: invalid instruction encoding
[0x03,0x43,0x38,0xd5]
# CHECK: mrs x3, ALLINT
@@ -12,14 +19,6 @@
# CHECK: msr ALLINT, x6
# NO-NMI: msr S3_0_C4_C3_0, x6
-[0x1f,0x40,0x01,0xd5]
-# CHECK: msr ALLINT, #0
-# NO-NMI: :[[@LINE-2]]:2: warning: invalid instruction encoding
-
-[0x1f,0x41,0x01,0xd5]
-# CHECK: msr ALLINT, #1
-# NO-NMI: :[[@LINE-2]]:2: warning: invalid instruction encoding
-
[0xa7,0xc9,0x38,0xd5]
# CHECK: mrs x7, ICC_NMIAR1_EL1
# NO-NMI: mrs x7, S3_0_C12_C9_5
>From 2ecbe9fef227959b58c143ea6216056eaf858e39 Mon Sep 17 00:00:00 2001
From: Marian Lukac <Marian.Lukac at arm.com>
Date: Thu, 12 Mar 2026 13:32:07 +0000
Subject: [PATCH 08/12] fix test
---
llvm/test/MC/AArch64/armv9-mrrs.s | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/llvm/test/MC/AArch64/armv9-mrrs.s b/llvm/test/MC/AArch64/armv9-mrrs.s
index 26bee51a30e8b..b22cfb7d17c19 100644
--- a/llvm/test/MC/AArch64/armv9-mrrs.s
+++ b/llvm/test/MC/AArch64/armv9-mrrs.s
@@ -189,10 +189,10 @@ msrr VTTBR_EL2, x26, x27
// CHECK-INST: msrr VTTBR_EL2, x26, x27
// CHECK-ENCODING: encoding: [0x1a,0x21,0x5c,0xd5]
-msrr S2_0_c2_c0_1, x26, x27
-// CHECK-INST: msrr S2_0_C2_C0_1, x26, x27
-// CHECK-ENCODING: encoding: [0x3a,0x20,0x50,0xd5]
+mrrs x0, x1, S2_0_c2_c0_1
+// CHECK-INST: mrrs x0, x1, S2_0_C2_C0_1
+// CHECK-ENCODING: encoding: [0x20,0x20,0x70,0xd5]
-msrr S3_0_c2_c0_1, x26, x27
-// CHECK-INST: msrr TTBR1_EL1, x26, x27
-// CHECK-ENCODING: encoding: [0x3a,0x20,0x58,0xd5]
+mrrs x0, x1, S3_0_c2_c0_1
+// CHECK-INST: mrrs x0, x1, TTBR1_EL1
+// CHECK-ENCODING: encoding: [0x20,0x20,0x78,0xd5]
>From 73e8faf82d138b6648f01ec5b7cc34e8ed5a15c5 Mon Sep 17 00:00:00 2001
From: Marian Lukac <Marian.Lukac at arm.com>
Date: Thu, 12 Mar 2026 13:35:39 +0000
Subject: [PATCH 09/12] adjlst
---
llvm/test/MC/AArch64/armv9-mrrs.s | 6 +++---
llvm/test/MC/AArch64/armv9-msrr.s | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/llvm/test/MC/AArch64/armv9-mrrs.s b/llvm/test/MC/AArch64/armv9-mrrs.s
index b22cfb7d17c19..478c37a7e2d83 100644
--- a/llvm/test/MC/AArch64/armv9-mrrs.s
+++ b/llvm/test/MC/AArch64/armv9-mrrs.s
@@ -193,6 +193,6 @@ mrrs x0, x1, S2_0_c2_c0_1
// CHECK-INST: mrrs x0, x1, S2_0_C2_C0_1
// CHECK-ENCODING: encoding: [0x20,0x20,0x70,0xd5]
-mrrs x0, x1, S3_0_c2_c0_1
-// CHECK-INST: mrrs x0, x1, TTBR1_EL1
-// CHECK-ENCODING: encoding: [0x20,0x20,0x78,0xd5]
+mrrs x0, x1, S3_1_c2_c0_1
+// CHECK-INST: mrrs x0, x1, S3_1_C2_C0_1
+// CHECK-ENCODING: encoding: [0x20,0x20,0x79,0xd5]
diff --git a/llvm/test/MC/AArch64/armv9-msrr.s b/llvm/test/MC/AArch64/armv9-msrr.s
index 3e117bfb8f5d0..f2dd1b5927463 100644
--- a/llvm/test/MC/AArch64/armv9-msrr.s
+++ b/llvm/test/MC/AArch64/armv9-msrr.s
@@ -105,6 +105,6 @@ msrr S2_0_c2_c0_1, x26, x27
// CHECK-INST: msrr S2_0_C2_C0_1, x26, x27
// CHECK-ENCODING: encoding: [0x3a,0x20,0x50,0xd5]
-msrr S3_0_c2_c0_1, x26, x27
-// CHECK-INST: msrr TTBR1_EL1, x26, x27
-// CHECK-ENCODING: encoding: [0x3a,0x20,0x58,0xd5]
+msrr S3_1_c2_c0_1, x26, x27
+// CHECK-INST: msrr S3_1_C2_C0_1, x26, x27
+// CHECK-ENCODING: encoding: [0x3a,0x20,0x59,0xd5]
>From 120a7c57a18d2c1de90f59ca944ff3cb5373ddfc Mon Sep 17 00:00:00 2001
From: Marian Lukac <Marian.Lukac at arm.com>
Date: Fri, 13 Mar 2026 18:10:29 +0000
Subject: [PATCH 10/12] Fixed codegen and added more thorough testing
---
.../Target/AArch64/AArch64ISelDAGToDAG.cpp | 4 ++-
.../CodeGen/AArch64/arm64-invalid-sys-reg.ll | 30 ++++++++++++++++
.../AArch64/arm64-named-reg-notareg.ll | 13 -------
llvm/test/CodeGen/AArch64/special-reg.ll | 35 +++++++++++++------
llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s | 16 ++++++++-
llvm/test/MC/AArch64/armv9-mrrs.s | 30 ++++++++++++----
llvm/test/MC/AArch64/armv9-msrr-diagnostics.s | 15 +++++++-
llvm/test/MC/AArch64/armv9-msrr.s | 26 ++++++++++++++
8 files changed, 136 insertions(+), 33 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/arm64-invalid-sys-reg.ll
delete mode 100644 llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 00b2ae8478ae1..df1e7a12483b7 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -4153,6 +4153,9 @@ static int getIntOperandFromRegisterString(StringRef RegString) {
assert(AllIntFields &&
"Unexpected non-integer value in special register string.");
(void)AllIntFields;
+
+ if (Ops[0] < 2 || Ops[1] > 7 || Ops[2] > 15 || Ops[3] > 15 || Ops[4] > 7)
+ return -1;
// Need to combine the integer fields of the string into a single value
// based on the bit encoding of MRS/MSR instruction. We also mask Ops[0], as
@@ -4185,7 +4188,6 @@ bool AArch64DAGToDAGISel::tryReadRegister(SDNode *N) {
Imm = TheReg->Encoding;
else
Imm = AArch64SysReg::parseGenericRegister(RegString->getString());
-
if (Imm == -1) {
// Still no match, see if this is "pc" or give up.
if (!ReadIs128Bit && RegString->getString() == "pc") {
diff --git a/llvm/test/CodeGen/AArch64/arm64-invalid-sys-reg.ll b/llvm/test/CodeGen/AArch64/arm64-invalid-sys-reg.ll
new file mode 100644
index 0000000000000..993a4d64c181d
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/arm64-invalid-sys-reg.ll
@@ -0,0 +1,30 @@
+; RUN: not llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s
+; RUN: not llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s
+
+define i32 @get_stack() nounwind {
+entry:
+; CHECK: error: <unknown>:0:0: invalid register "notareg" for llvm.read_register
+ %sp = call i32 @llvm.read_register.i32(metadata !0)
+ ret i32 %sp
+}
+
+define i64 @read_invalid() nounwind {
+; CHECK: error: <unknown>:0:0: invalid register "1:2:3:4:5" for llvm.read_register
+entry:
+ %reg = call i64 @llvm.read_register.i64(metadata !1)
+ ret i64 %reg
+}
+
+define void @write_invalid(i64 %x) nounwind {
+; CHECK: error: <unknown>:0:0: invalid register "1:2:3:4:5" for llvm.write_register
+entry:
+ call void @llvm.write_register.i64(metadata !1, i64 %x)
+ ret void
+}
+
+declare i32 @llvm.reac_register.i32(metadata) nounwind
+declare void @llvm.write_register.i64(metadata, i64) nounwind
+
+!0 = !{!"notareg\00"}
+!1 = !{!"1:2:3:4:5"}
+
diff --git a/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll b/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll
deleted file mode 100644
index b671026251da8..0000000000000
--- a/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll
+++ /dev/null
@@ -1,13 +0,0 @@
-; RUN: not llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s
-; RUN: not llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s
-
-define i32 @get_stack() nounwind {
-entry:
-; CHECK: error: <unknown>:0:0: invalid register "notareg" for llvm.read_register
- %sp = call i32 @llvm.read_register.i32(metadata !0)
- ret i32 %sp
-}
-
-declare i32 @llvm.read_register.i32(metadata) nounwind
-
-!0 = !{!"notareg\00"}
diff --git a/llvm/test/CodeGen/AArch64/special-reg.ll b/llvm/test/CodeGen/AArch64/special-reg.ll
index 81add608083d6..1e27e6a89db2b 100644
--- a/llvm/test/CodeGen/AArch64/special-reg.ll
+++ b/llvm/test/CodeGen/AArch64/special-reg.ll
@@ -1,41 +1,54 @@
-; RUN: llc < %s -mtriple=aarch64 -mcpu=cortex-a57 2>&1 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc %s -mtriple=aarch64 -mcpu=cortex-a57 2>&1 | FileCheck %s
+
+
define i64 @read_encoded_register() nounwind {
-entry:
; CHECK-LABEL: read_encoded_register:
-; CHECK: mrs x0, S3_2_C3_C4_5
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mrs x0, S3_2_C3_C4_5
+; CHECK-NEXT: ret
+entry:
%reg = call i64 @llvm.read_register.i64(metadata !0)
ret i64 %reg
}
define i64 @read_daif() nounwind {
-entry:
; CHECK-LABEL: read_daif:
-; CHECK: mrs x0, DAIF
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mrs x0, DAIF
+; CHECK-NEXT: ret
+entry:
%reg = call i64 @llvm.read_register.i64(metadata !1)
ret i64 %reg
}
define void @write_encoded_register(i64 %x) nounwind {
-entry:
; CHECK-LABEL: write_encoded_register:
-; CHECK: msr S3_2_C3_C4_5, x0
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: msr S3_2_C3_C4_5, x0
+; CHECK-NEXT: ret
+entry:
call void @llvm.write_register.i64(metadata !0, i64 %x)
ret void
}
define void @write_daif(i64 %x) nounwind {
-entry:
; CHECK-LABEL: write_daif:
-; CHECK: msr DAIF, x0
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: msr DAIF, x0
+; CHECK-NEXT: ret
+entry:
call void @llvm.write_register.i64(metadata !1, i64 %x)
ret void
}
define void @write_daifset() nounwind {
-entry:
; CHECK-LABEL: write_daifset:
-; CHECK: msr DAIFSet, #2
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: msr DAIFSet, #2
+; CHECK-NEXT: ret
+entry:
call void @llvm.write_register.i64(metadata !2, i64 2)
ret void
}
diff --git a/llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s b/llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s
index cec724624b830..8945d11ff789f 100644
--- a/llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s
+++ b/llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s
@@ -29,11 +29,25 @@ mrrs S3_0_c2_c0_1
mrrs S3_0_c2_c0_1, x0, x1
// CHECK-ERROR: error: expected first even register of a consecutive same-size even/odd register pair
+// Test invalid system register name
+
mrrs x0, x1, S0_0_c2_c0_1
// CHECK-ERROR: error: expected readable system register
+mrrs x0, x1, S4_0_c2_c0_1
+// CHECK-ERROR: error: expected readable system register
+
mrrs x0, x1, S1_0_c2_c0_1
// CHECK-ERROR: error: expected readable system register
-mrrs x0, x1, S4_0_c2_c0_1
+mrrs x0, x1, S2_8_c2_c0_1
+// CHECK-ERROR: error: expected readable system register
+
+mrrs x0, x1, S2_0_c16_c0_1
+// CHECK-ERROR: error: expected readable system register
+
+mrrs x0, x1, S2_0_c0_c16_1
+// CHECK-ERROR: error: expected readable system register
+
+mrrs x0, x1, S2_0_c0_c0_8
// CHECK-ERROR: error: expected readable system register
diff --git a/llvm/test/MC/AArch64/armv9-mrrs.s b/llvm/test/MC/AArch64/armv9-mrrs.s
index 478c37a7e2d83..d0d917fb9f502 100644
--- a/llvm/test/MC/AArch64/armv9-mrrs.s
+++ b/llvm/test/MC/AArch64/armv9-mrrs.s
@@ -189,10 +189,28 @@ msrr VTTBR_EL2, x26, x27
// CHECK-INST: msrr VTTBR_EL2, x26, x27
// CHECK-ENCODING: encoding: [0x1a,0x21,0x5c,0xd5]
-mrrs x0, x1, S2_0_c2_c0_1
-// CHECK-INST: mrrs x0, x1, S2_0_C2_C0_1
-// CHECK-ENCODING: encoding: [0x20,0x20,0x70,0xd5]
+// Test generic register assembly
-mrrs x0, x1, S3_1_c2_c0_1
-// CHECK-INST: mrrs x0, x1, S3_1_C2_C0_1
-// CHECK-ENCODING: encoding: [0x20,0x20,0x79,0xd5]
+mrrs x0, x1, S2_0_C0_C0_0
+// CHECK-INST: mrrs x0, x1, S2_0_C0_C0_0
+// CHECK-ENCODING: encoding: [0x00,0x00,0x70,0xd5]
+
+mrrs x0, x1, S3_0_C0_C0_0
+// CHECK-INST: mrrs x0, x1, MIDR_EL1
+// CHECK-ENCODING: encoding: [0x00,0x00,0x78,0xd5]
+
+mrrs x0, x1, S2_7_C0_C0_0
+// CHECK-INST: mrrs x0, x1, S2_7_C0_C0_0
+// CHECK-ENCODING: encoding: [0x00,0x00,0x77,0xd5]
+
+mrrs x0, x1, S2_0_C15_C0_0
+// CHECK-INST: mrrs x0, x1, S2_0_C15_C0_0
+// CHECK-ENCODING: encoding: [0x00,0xf0,0x70,0xd5]
+
+mrrs x0, x1, S2_0_C0_C15_0
+// CHECK-INST: mrrs x0, x1, S2_0_C0_C15_0
+// CHECK-ENCODING: encoding: [0x00,0x0f,0x70,0xd5]
+
+mrrs x0, x1, S2_0_C0_C0_7
+// CHECK-INST: mrrs x0, x1, DBGWCR0_EL1
+// CHECK-ENCODING: encoding: [0xe0,0x00,0x70,0xd5]
diff --git a/llvm/test/MC/AArch64/armv9-msrr-diagnostics.s b/llvm/test/MC/AArch64/armv9-msrr-diagnostics.s
index cf52afcb05b49..3fc343f247f48 100644
--- a/llvm/test/MC/AArch64/armv9-msrr-diagnostics.s
+++ b/llvm/test/MC/AArch64/armv9-msrr-diagnostics.s
@@ -29,12 +29,25 @@ msrr S3_0_c2_c0_1
msrr x0, x1, S3_0_c2_c0_1
// CHECK-ERROR: error: expected first even register of a consecutive same-size even/odd register pair
+// Test invalid system register name
+
msrr S0_0_c2_c0_1, x26, x27
// CHECK-ERROR: error: expected writable system register or pstate
-
msrr S1_0_c2_c0_1, x26, x27
// CHECK-ERROR: error: expected writable system register or pstate
msrr S4_0_c2_c0_1, x26, x27
// CHECK-ERROR: error: expected writable system register or pstate
+
+msrr S2_8_c2_c0_1, x26, x27
+// CHECK-ERROR: error: expected writable system register or pstate
+
+msrr S2_0_c16_c0_1, x26, x27
+// CHECK-ERROR: error: expected writable system register or pstate
+
+msrr S2_0_c0_c16_1, x26, x27
+// CHECK-ERROR: error: expected writable system register or pstate
+
+msrr S2_0_c0_c0_8, x26, x27
+// CHECK-ERROR: error: expected writable system register or pstate
diff --git a/llvm/test/MC/AArch64/armv9-msrr.s b/llvm/test/MC/AArch64/armv9-msrr.s
index f2dd1b5927463..b61b3a4b7c418 100644
--- a/llvm/test/MC/AArch64/armv9-msrr.s
+++ b/llvm/test/MC/AArch64/armv9-msrr.s
@@ -108,3 +108,29 @@ msrr S2_0_c2_c0_1, x26, x27
msrr S3_1_c2_c0_1, x26, x27
// CHECK-INST: msrr S3_1_C2_C0_1, x26, x27
// CHECK-ENCODING: encoding: [0x3a,0x20,0x59,0xd5]
+
+// Test generic register assembly
+
+msrr S2_0_C0_C0_0, x0, x1
+// CHECK-INST: msrr S2_0_C0_C0_0, x0, x1
+// CHECK-ENCODING: encoding: [0x00,0x00,0x50,0xd5]
+
+msrr S3_0_C0_C0_0, x0, x1
+// CHECK-INST: msrr S3_0_C0_C0_0, x0, x1
+// CHECK-ENCODING: encoding: [0x00,0x00,0x58,0xd5]
+
+msrr S2_7_C0_C0_0, x0, x1
+// CHECK-INST: msrr S2_7_C0_C0_0, x0, x1
+// CHECK-ENCODING: encoding: [0x00,0x00,0x57,0xd5]
+
+msrr S2_0_C15_C0_0, x0, x1
+// CHECK-INST: msrr S2_0_C15_C0_0, x0, x1
+// CHECK-ENCODING: encoding: [0x00,0xf0,0x50,0xd5]
+
+msrr S2_0_C0_C15_0, x0, x1
+// CHECK-INST: msrr S2_0_C0_C15_0, x0, x1
+// CHECK-ENCODING: encoding: [0x00,0x0f,0x50,0xd5]
+
+msrr S2_0_C0_C0_7, x0, x1
+// CHECK-INST: msrr DBGWCR0_EL1, x0, x1
+// CHECK-ENCODING: encoding: [0xe0,0x00,0x50,0xd5]
>From 8c77e55ecb0f1ddcbf3fadf2c2141cff68e93d4a Mon Sep 17 00:00:00 2001
From: Marian Lukac <Marian.Lukac at arm.com>
Date: Fri, 13 Mar 2026 18:20:57 +0000
Subject: [PATCH 11/12] Fix
---
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 2 +-
llvm/test/MC/AArch64/armv9-msrr.s | 8 --------
2 files changed, 1 insertion(+), 9 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index df1e7a12483b7..6aa60fc30a144 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -4153,7 +4153,7 @@ static int getIntOperandFromRegisterString(StringRef RegString) {
assert(AllIntFields &&
"Unexpected non-integer value in special register string.");
(void)AllIntFields;
-
+
if (Ops[0] < 2 || Ops[1] > 7 || Ops[2] > 15 || Ops[3] > 15 || Ops[4] > 7)
return -1;
diff --git a/llvm/test/MC/AArch64/armv9-msrr.s b/llvm/test/MC/AArch64/armv9-msrr.s
index b61b3a4b7c418..8080cd5e87d7e 100644
--- a/llvm/test/MC/AArch64/armv9-msrr.s
+++ b/llvm/test/MC/AArch64/armv9-msrr.s
@@ -101,14 +101,6 @@ msrr VTTBR_EL2, x26, x27
// CHECK-INST: msrr VTTBR_EL2, x26, x27
// CHECK-ENCODING: encoding: [0x1a,0x21,0x5c,0xd5]
-msrr S2_0_c2_c0_1, x26, x27
-// CHECK-INST: msrr S2_0_C2_C0_1, x26, x27
-// CHECK-ENCODING: encoding: [0x3a,0x20,0x50,0xd5]
-
-msrr S3_1_c2_c0_1, x26, x27
-// CHECK-INST: msrr S3_1_C2_C0_1, x26, x27
-// CHECK-ENCODING: encoding: [0x3a,0x20,0x59,0xd5]
-
// Test generic register assembly
msrr S2_0_C0_C0_0, x0, x1
>From f51f1206fc395148fd1b45cdccdd28dca374c68a Mon Sep 17 00:00:00 2001
From: Marian Lukac <Marian.Lukac at arm.com>
Date: Tue, 24 Mar 2026 13:44:10 +0000
Subject: [PATCH 12/12] fix
---
llvm/test/CodeGen/AArch64/special-reg.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/special-reg.ll b/llvm/test/CodeGen/AArch64/special-reg.ll
index 1e27e6a89db2b..9e68aa3453aa2 100644
--- a/llvm/test/CodeGen/AArch64/special-reg.ll
+++ b/llvm/test/CodeGen/AArch64/special-reg.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc %s -mtriple=aarch64 -mcpu=cortex-a57 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -mcpu=cortex-a57 2>&1 | FileCheck %s
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