[llvm] [AArch64][GlobalISel] Add patterns for scalar sqdmlal/sqdmlsl (PR #187246)
Joshua Rodriguez via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 24 04:57:36 PDT 2026
https://github.com/JoshdRod updated https://github.com/llvm/llvm-project/pull/187246
>From bbb8ab50228d32b29c05a0c6b005bc36e545ae7a Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Wed, 18 Mar 2026 12:07:08 +0000
Subject: [PATCH 1/5] [AArch64][GlobalISel] Add patterns for scalar
sqdmlal/sqdmlsl
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 8 ++++++++
llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp | 1 +
2 files changed, 9 insertions(+)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 84566946260c3..004edb988bf33 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -6631,10 +6631,18 @@ def : Pat<(f64 (AArch64sqadd FPR64:$Rd,
(AArch64sqdmull FPR32:$Rn, FPR32:$Rm))),
(SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
+def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
+ (int_aarch64_neon_sqdmulls_scalar FPR32:$Rn, FPR32:$Rm))),
+ (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
+
def : Pat<(f64 (AArch64sqsub FPR64:$Rd,
(AArch64sqdmull FPR32:$Rn, FPR32:$Rm))),
(SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
+def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
+ (int_aarch64_neon_sqdmulls_scalar FPR32:$Rn, FPR32:$Rm))),
+ (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
+
//===----------------------------------------------------------------------===//
// Advanced SIMD two scalar instructions.
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index 03f714cddec83..ca881b8dbb008 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -621,6 +621,7 @@ static bool isFPIntrinsic(const MachineRegisterInfo &MRI,
case Intrinsic::aarch64_neon_sqrdmulh:
case Intrinsic::aarch64_neon_sqadd:
case Intrinsic::aarch64_neon_sqsub:
+ case Intrinsic::aarch64_neon_sqdmulls_scalar:
case Intrinsic::aarch64_neon_srshl:
case Intrinsic::aarch64_neon_urshl:
case Intrinsic::aarch64_neon_sqshl:
>From cb33664d1ab2432bb180301526899e59c8d73128 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Wed, 18 Mar 2026 14:40:03 +0000
Subject: [PATCH 2/5] [AArch64][GlobalISel] Update test checks
---
llvm/test/CodeGen/AArch64/arm64-vmul.ll | 106 ++++++++++++++++--------
1 file changed, 70 insertions(+), 36 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-vmul.ll b/llvm/test/CodeGen/AArch64/arm64-vmul.ll
index 4a3687d3a9fd4..ebc99d91d700a 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vmul.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vmul.ll
@@ -19,8 +19,6 @@
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fmla_indexed_scalar_4s_strict
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fmla_indexed_scalar_2d_strict
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqdmulh_lane_1s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqdmlal_lane_1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqdmlsl_lane_1d
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for scalar_fmls_from_extract_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for scalar_fmls_from_extract_v2f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for scalar_fmls_from_extract_v2f64
@@ -29,8 +27,6 @@
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fmls_with_fneg_before_extract_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fmls_with_fneg_before_extract_v4f32_1
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fmls_with_fneg_before_extract_v2f64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqdmlal_d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqdmlsl_d
define <8 x i16> @smull8h(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: smull8h:
@@ -1793,14 +1789,24 @@ define i32 @sqsub_lane1_sqdmull4s(i32 %A, <4 x i16> %B, <4 x i16> %C) nounwind {
}
define i64 @sqdmlal_lane_1d(i64 %A, i32 %B, <2 x i32> %C) nounwind {
-; CHECK-LABEL: sqdmlal_lane_1d:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov s1, w1
-; CHECK-NEXT: fmov d2, x0
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: sqdmlal d2, s1, v0.s[1]
-; CHECK-NEXT: fmov x0, d2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sqdmlal_lane_1d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov s1, w1
+; CHECK-SD-NEXT: fmov d2, x0
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: sqdmlal d2, s1, v0.s[1]
+; CHECK-SD-NEXT: fmov x0, d2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sqdmlal_lane_1d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: fmov s1, w1
+; CHECK-GI-NEXT: fmov d2, x0
+; CHECK-GI-NEXT: mov s0, v0.s[1]
+; CHECK-GI-NEXT: sqdmlal d2, s1, s0
+; CHECK-GI-NEXT: fmov x0, d2
+; CHECK-GI-NEXT: ret
%rhs = extractelement <2 x i32> %C, i32 1
%prod = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %B, i32 %rhs)
%res = call i64 @llvm.aarch64.neon.sqadd.i64(i64 %A, i64 %prod)
@@ -1810,14 +1816,24 @@ declare i64 @llvm.aarch64.neon.sqdmulls.scalar(i32, i32)
declare i64 @llvm.aarch64.neon.sqadd.i64(i64, i64)
define i64 @sqdmlsl_lane_1d(i64 %A, i32 %B, <2 x i32> %C) nounwind {
-; CHECK-LABEL: sqdmlsl_lane_1d:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov s1, w1
-; CHECK-NEXT: fmov d2, x0
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: sqdmlsl d2, s1, v0.s[1]
-; CHECK-NEXT: fmov x0, d2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sqdmlsl_lane_1d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov s1, w1
+; CHECK-SD-NEXT: fmov d2, x0
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: sqdmlsl d2, s1, v0.s[1]
+; CHECK-SD-NEXT: fmov x0, d2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sqdmlsl_lane_1d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: fmov s1, w1
+; CHECK-GI-NEXT: fmov d2, x0
+; CHECK-GI-NEXT: mov s0, v0.s[1]
+; CHECK-GI-NEXT: sqdmlsl d2, s1, s0
+; CHECK-GI-NEXT: fmov x0, d2
+; CHECK-GI-NEXT: ret
%rhs = extractelement <2 x i32> %C, i32 1
%prod = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %B, i32 %rhs)
%res = call i64 @llvm.aarch64.neon.sqsub.i64(i64 %A, i64 %prod)
@@ -3201,14 +3217,23 @@ define i32 @sqdmlal_s(i16 %A, i16 %B, i32 %C) nounwind {
}
define i64 @sqdmlal_d(i32 %A, i32 %B, i64 %C) nounwind {
-; CHECK-LABEL: sqdmlal_d:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov s0, w1
-; CHECK-NEXT: fmov s1, w0
-; CHECK-NEXT: fmov d2, x2
-; CHECK-NEXT: sqdmlal d2, s1, s0
-; CHECK-NEXT: fmov x0, d2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sqdmlal_d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov s0, w1
+; CHECK-SD-NEXT: fmov s1, w0
+; CHECK-SD-NEXT: fmov d2, x2
+; CHECK-SD-NEXT: sqdmlal d2, s1, s0
+; CHECK-SD-NEXT: fmov x0, d2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sqdmlal_d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov s0, w0
+; CHECK-GI-NEXT: fmov s1, w1
+; CHECK-GI-NEXT: fmov d2, x2
+; CHECK-GI-NEXT: sqdmlal d2, s0, s1
+; CHECK-GI-NEXT: fmov x0, d2
+; CHECK-GI-NEXT: ret
%tmp4 = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %A, i32 %B)
%tmp5 = call i64 @llvm.aarch64.neon.sqadd.i64(i64 %C, i64 %tmp4)
ret i64 %tmp5
@@ -3241,14 +3266,23 @@ define i32 @sqdmlsl_s(i16 %A, i16 %B, i32 %C) nounwind {
}
define i64 @sqdmlsl_d(i32 %A, i32 %B, i64 %C) nounwind {
-; CHECK-LABEL: sqdmlsl_d:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov s0, w1
-; CHECK-NEXT: fmov s1, w0
-; CHECK-NEXT: fmov d2, x2
-; CHECK-NEXT: sqdmlsl d2, s1, s0
-; CHECK-NEXT: fmov x0, d2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sqdmlsl_d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov s0, w1
+; CHECK-SD-NEXT: fmov s1, w0
+; CHECK-SD-NEXT: fmov d2, x2
+; CHECK-SD-NEXT: sqdmlsl d2, s1, s0
+; CHECK-SD-NEXT: fmov x0, d2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sqdmlsl_d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov s0, w0
+; CHECK-GI-NEXT: fmov s1, w1
+; CHECK-GI-NEXT: fmov d2, x2
+; CHECK-GI-NEXT: sqdmlsl d2, s0, s1
+; CHECK-GI-NEXT: fmov x0, d2
+; CHECK-GI-NEXT: ret
%tmp4 = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %A, i32 %B)
%tmp5 = call i64 @llvm.aarch64.neon.sqsub.i64(i64 %C, i64 %tmp4)
ret i64 %tmp5
>From 768c475ea907069faf6aba688e4edc1c9528e519 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Thu, 19 Mar 2026 10:44:07 +0000
Subject: [PATCH 3/5] [AArch64][GlobalISel] Add pattern to lower
aarch64.neon.sqdmulls.scalar
SDAG was able to lower this intrinsic because it was turned into an AArch64sqdmull ISD node before instruction selection. As aarch64.neon.sqdmull and aarch64.neon.sqdmulls.scalar are two different LLVM intrinsics, we need two separate patterns to lower them correctly.
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 4 ++++
llvm/test/CodeGen/AArch64/arm64-int-neon.ll | 1 -
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 004edb988bf33..aa5d8b81013f6 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -9056,6 +9056,10 @@ def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
VectorIndexS:$idx)),
(SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
+def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
+ (i32 FPR32:$Rm)),
+ (SQDMULLi32 FPR32:$Rn, FPR32:$Rm)>;
+
//----------------------------------------------------------------------------
// AdvSIMD scalar shift instructions
//----------------------------------------------------------------------------
diff --git a/llvm/test/CodeGen/AArch64/arm64-int-neon.ll b/llvm/test/CodeGen/AArch64/arm64-int-neon.ll
index 309a17798b13c..46ad69c3cd58c 100644
--- a/llvm/test/CodeGen/AArch64/arm64-int-neon.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-int-neon.ll
@@ -10,7 +10,6 @@
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqadd_s64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqsub_s32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqsub_s64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqdmulls_scalar
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqdmulh_scalar
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqabs_s32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqabs_s64
>From 98cf90e3d233031c8f5b690824766a2ef5d5f752 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Thu, 19 Mar 2026 13:43:45 +0000
Subject: [PATCH 4/5] [AArch64][GlobalISel] Select lane index sqdmlal when
vector_extract of v4i32 present
SQDMLALv1i64_indexed takes in an index of a vector as its final operand, meaning it doesn't need to extract the element in a separate instruction.
This only works when the vector to extract from is a v4i32. Currently, extracting from a v2i32 doesn't work, and I'm unsure why.
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index aa5d8b81013f6..e6493c418730c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -9060,6 +9060,12 @@ def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
(i32 FPR32:$Rm)),
(SQDMULLi32 FPR32:$Rn, FPR32:$Rm)>;
+def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
+ (int_aarch64_neon_sqdmulls_scalar FPR32:$Rn,
+ (vector_extract (v4i32 V128:$Vm),
+ VectorIndexS:$idx)))),
+ (SQDMLALv1i64_indexed FPR64:$Rd, FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
+
//----------------------------------------------------------------------------
// AdvSIMD scalar shift instructions
//----------------------------------------------------------------------------
>From 35e650eec144abcd4b5073055e71528ee74e0e3b Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Tue, 24 Mar 2026 11:57:16 +0000
Subject: [PATCH 5/5] [AArch64][GlobalISel] Add test for v4i32 vector extract
sqdmlal/sqdmlsl
1. Tests only test v4i32 versions of the intrinsic, as v2i32 currently doesn't work.
2. GlobalISel currently generates poor code in the sqdmlsl case. To fix, the sqdmlalvi64_indexed pattern needs to be copied over for sqdmlsl.
---
llvm/test/CodeGen/AArch64/arm64-vmul.ll | 48 +++++++++++++++++++++----
1 file changed, 42 insertions(+), 6 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-vmul.ll b/llvm/test/CodeGen/AArch64/arm64-vmul.ll
index ebc99d91d700a..013850b540a2e 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vmul.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vmul.ll
@@ -1788,8 +1788,8 @@ define i32 @sqsub_lane1_sqdmull4s(i32 %A, <4 x i16> %B, <4 x i16> %C) nounwind {
ret i32 %res
}
-define i64 @sqdmlal_lane_1d(i64 %A, i32 %B, <2 x i32> %C) nounwind {
-; CHECK-SD-LABEL: sqdmlal_lane_1d:
+define i64 @sqdmlal_lane_1d_v2i32(i64 %A, i32 %B, <2 x i32> %C) nounwind {
+; CHECK-SD-LABEL: sqdmlal_lane_1d_v2i32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fmov s1, w1
; CHECK-SD-NEXT: fmov d2, x0
@@ -1798,7 +1798,7 @@ define i64 @sqdmlal_lane_1d(i64 %A, i32 %B, <2 x i32> %C) nounwind {
; CHECK-SD-NEXT: fmov x0, d2
; CHECK-SD-NEXT: ret
;
-; CHECK-GI-LABEL: sqdmlal_lane_1d:
+; CHECK-GI-LABEL: sqdmlal_lane_1d_v2i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: fmov s1, w1
@@ -1815,8 +1815,8 @@ define i64 @sqdmlal_lane_1d(i64 %A, i32 %B, <2 x i32> %C) nounwind {
declare i64 @llvm.aarch64.neon.sqdmulls.scalar(i32, i32)
declare i64 @llvm.aarch64.neon.sqadd.i64(i64, i64)
-define i64 @sqdmlsl_lane_1d(i64 %A, i32 %B, <2 x i32> %C) nounwind {
-; CHECK-SD-LABEL: sqdmlsl_lane_1d:
+define i64 @sqdmlsl_lane_1d_v2i32(i64 %A, i32 %B, <2 x i32> %C) nounwind {
+; CHECK-SD-LABEL: sqdmlsl_lane_1d_v2i32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fmov s1, w1
; CHECK-SD-NEXT: fmov d2, x0
@@ -1825,7 +1825,7 @@ define i64 @sqdmlsl_lane_1d(i64 %A, i32 %B, <2 x i32> %C) nounwind {
; CHECK-SD-NEXT: fmov x0, d2
; CHECK-SD-NEXT: ret
;
-; CHECK-GI-LABEL: sqdmlsl_lane_1d:
+; CHECK-GI-LABEL: sqdmlsl_lane_1d_v2i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: fmov s1, w1
@@ -1841,6 +1841,42 @@ define i64 @sqdmlsl_lane_1d(i64 %A, i32 %B, <2 x i32> %C) nounwind {
}
declare i64 @llvm.aarch64.neon.sqsub.i64(i64, i64)
+define i64 @sqdmlal_lane_1d_v4i32(i64 %A, i32 %B, <4 x i32> %C) nounwind {
+; CHECK-LABEL: sqdmlal_lane_1d_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s1, w1
+; CHECK-NEXT: fmov d2, x0
+; CHECK-NEXT: sqdmlal d2, s1, v0.s[1]
+; CHECK-NEXT: fmov x0, d2
+; CHECK-NEXT: ret
+ %rhs = extractelement <4 x i32> %C, i32 1
+ %prod = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %B, i32 %rhs)
+ %res = call i64 @llvm.aarch64.neon.sqadd.i64(i64 %A, i64 %prod)
+ ret i64 %res
+}
+
+define i64 @sqdmlsl_lane_1d_v4i32(i64 %A, i32 %B, <4 x i32> %C) nounwind {
+; CHECK-SD-LABEL: sqdmlsl_lane_1d_v4i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fmov s1, w1
+; CHECK-SD-NEXT: fmov d2, x0
+; CHECK-SD-NEXT: sqdmlsl d2, s1, v0.s[1]
+; CHECK-SD-NEXT: fmov x0, d2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sqdmlsl_lane_1d_v4i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov s0, v0.s[1]
+; CHECK-GI-NEXT: fmov s1, w1
+; CHECK-GI-NEXT: fmov d2, x0
+; CHECK-GI-NEXT: sqdmlsl d2, s1, s0
+; CHECK-GI-NEXT: fmov x0, d2
+; CHECK-GI-NEXT: ret
+ %rhs = extractelement <4 x i32> %C, i32 1
+ %prod = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %B, i32 %rhs)
+ %res = call i64 @llvm.aarch64.neon.sqsub.i64(i64 %A, i64 %prod)
+ ret i64 %res
+}
define <4 x i32> @umlal_lane_4s(<4 x i16> %A, <4 x i16> %B, <4 x i32> %C) nounwind {
; CHECK-LABEL: umlal_lane_4s:
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