[llvm] [AMDGPU] Disable DPP reduction path for 64-bit values (PR #188175)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Aaditya (easyonaadit)

<details>
<summary>Changes</summary>

Implementations for 64-bit value reductions are
still WIP.
Disable the code path to stop crashing.

---
Full diff: https://github.com/llvm/llvm-project/pull/188175.diff


1 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+2-1) 


``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index d0fceb6717c38..9c3f6b5d80172 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5964,7 +5964,8 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
     bool IsWave32 = ST.isWave32();
     unsigned MovOpcForExec = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
     unsigned ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
-    if (Stratergy == WAVE_REDUCE_STRATEGY::ITERATIVE ||
+    /// TODO: Implement wave reduction for 64-bit values.
+    if (!is32BitOpc || Stratergy == WAVE_REDUCE_STRATEGY::ITERATIVE ||
         !ST.hasDPP()) { // If target doesn't support DPP operations, default to
                         // iterative stratergy
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/188175