[llvm] [AMDGPU][SILowerSGPRSpills] Correct insertion of IMPLICIT_DEF in loop headers (PR #186348)

[via llvm-commits]

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@@ -0,0 +1,117 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR-SPILL %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -start-before=si-lower-sgpr-spills -stop-after=regallocfast,1 -verify-machineinstrs %s -o - | FileCheck -check-prefix=WWM-REGALLOC %s
+
+
+# When SGPR spills to a virtual VGPR lane occur in both a loop header and the latch,
+# the IMPLICIT_DEF for the lane VGPR must be placed in the preheader (not the header).
+# Establish that the virtual VGPR is live-in to the header and wwm regallocfast inserts
+# a restore, preserving the latch writes.
+
+---
+name:            sgpr_spill_loop_header_and_latch_implicit_def_in_preheader
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    4
+stack:
+  - { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
+machineFunctionInfo:
+  isEntryFunction: false
+  scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
+  stackPtrOffsetReg: '$sgpr32'
+  frameOffsetReg: '$sgpr33'
+  hasSpilledSGPRs: true
+body:             |
+  ; SGPR-SPILL-LABEL: name: sgpr_spill_loop_header_and_latch_implicit_def_in_preheader
+  ; SGPR-SPILL: bb.0:
+  ; SGPR-SPILL-NEXT:   successors: %bb.1(0x80000000)
+  ; SGPR-SPILL-NEXT:   liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
+  ; SGPR-SPILL-NEXT: {{  $}}
+  ; SGPR-SPILL-NEXT:   S_NOP 0
+  ; SGPR-SPILL-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; SGPR-SPILL-NEXT:   S_BRANCH %bb.1
+  ; SGPR-SPILL-NEXT: {{  $}}
+  ; SGPR-SPILL-NEXT: bb.1:
+  ; SGPR-SPILL-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
+  ; SGPR-SPILL-NEXT:   liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
+  ; SGPR-SPILL-NEXT: {{  $}}
+  ; SGPR-SPILL-NEXT:   $sgpr10 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0
+  ; SGPR-SPILL-NEXT:   S_CMP_EQ_U32 $sgpr11, 0, implicit-def $scc
+  ; SGPR-SPILL-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr10, 0, [[DEF]]
+  ; SGPR-SPILL-NEXT:   S_CBRANCH_SCC1 %bb.2, implicit killed $scc
+  ; SGPR-SPILL-NEXT:   S_BRANCH %bb.3
+  ; SGPR-SPILL-NEXT: {{  $}}
+  ; SGPR-SPILL-NEXT: bb.2:
+  ; SGPR-SPILL-NEXT:   successors: %bb.1(0x80000000)
+  ; SGPR-SPILL-NEXT:   liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
+  ; SGPR-SPILL-NEXT: {{  $}}
+  ; SGPR-SPILL-NEXT:   $sgpr10 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0
+  ; SGPR-SPILL-NEXT:   $sgpr10 = S_MOV_B32 1
+  ; SGPR-SPILL-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr10, 0, [[DEF]]
+  ; SGPR-SPILL-NEXT:   S_BRANCH %bb.1
+  ; SGPR-SPILL-NEXT: {{  $}}
+  ; SGPR-SPILL-NEXT: bb.3:
+  ; SGPR-SPILL-NEXT:   liveins: $sgpr30_sgpr31
+  ; SGPR-SPILL-NEXT: {{  $}}
+  ; SGPR-SPILL-NEXT:   S_SETPC_B64 $sgpr30_sgpr31
+  ;
+  ; WWM-REGALLOC-LABEL: name: sgpr_spill_loop_header_and_latch_implicit_def_in_preheader
+  ; WWM-REGALLOC: bb.0:
+  ; WWM-REGALLOC-NEXT:   successors: %bb.1(0x80000000)
+  ; WWM-REGALLOC-NEXT:   liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
+  ; WWM-REGALLOC-NEXT: {{  $}}
+  ; WWM-REGALLOC-NEXT:   S_NOP 0
+  ; WWM-REGALLOC-NEXT:   renamable $vgpr63 = IMPLICIT_DEF
+  ; WWM-REGALLOC-NEXT:   S_BRANCH %bb.1
+  ; WWM-REGALLOC-NEXT: {{  $}}
+  ; WWM-REGALLOC-NEXT: bb.1:
+  ; WWM-REGALLOC-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
+  ; WWM-REGALLOC-NEXT:   liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
+  ; WWM-REGALLOC-NEXT: {{  $}}
+  ; WWM-REGALLOC-NEXT:   $vgpr63 = SI_SPILL_WWM_V32_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5)
+  ; WWM-REGALLOC-NEXT:   $sgpr10 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 0
+  ; WWM-REGALLOC-NEXT:   S_CMP_EQ_U32 $sgpr11, 0, implicit-def $scc
+  ; WWM-REGALLOC-NEXT:   $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr10, 0, $vgpr63
+  ; WWM-REGALLOC-NEXT:   SI_SPILL_WWM_V32_SAVE killed $vgpr63, %stack.1, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5)
+  ; WWM-REGALLOC-NEXT:   S_CBRANCH_SCC1 %bb.2, implicit killed $scc
+  ; WWM-REGALLOC-NEXT:   S_BRANCH %bb.3
+  ; WWM-REGALLOC-NEXT: {{  $}}
+  ; WWM-REGALLOC-NEXT: bb.2:
+  ; WWM-REGALLOC-NEXT:   successors: %bb.1(0x80000000)
+  ; WWM-REGALLOC-NEXT:   liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
+  ; WWM-REGALLOC-NEXT: {{  $}}
+  ; WWM-REGALLOC-NEXT:   $vgpr63 = SI_SPILL_WWM_V32_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5)
+  ; WWM-REGALLOC-NEXT:   dead $sgpr10 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 0
+  ; WWM-REGALLOC-NEXT:   $sgpr10 = S_MOV_B32 1
+  ; WWM-REGALLOC-NEXT:   $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr10, 0, $vgpr63
+  ; WWM-REGALLOC-NEXT:   SI_SPILL_WWM_V32_SAVE killed $vgpr63, %stack.1, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5)
+  ; WWM-REGALLOC-NEXT:   S_BRANCH %bb.1
+  ; WWM-REGALLOC-NEXT: {{  $}}
+  ; WWM-REGALLOC-NEXT: bb.3:
+  ; WWM-REGALLOC-NEXT:   liveins: $sgpr30_sgpr31
+  ; WWM-REGALLOC-NEXT: {{  $}}
+  ; WWM-REGALLOC-NEXT:   S_SETPC_B64 killed $sgpr30_sgpr31
+
+
+  bb.0:
+    liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
+    S_NOP 0
+    S_BRANCH %bb.1
+  bb.1:
+    liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
+    renamable $sgpr10 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
----------------
ruiling wrote:

I guess the case for the spilled register, it looks like a phi with poison value from loop preheader in LLVM IR, right?

https://github.com/llvm/llvm-project/pull/186348