[llvm] 063109f - [NewPM] Adds a port for AArch64MIPeepholeOpt (#187515)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 20 09:17:39 PDT 2026
Author: Anshul Nigham
Date: 2026-03-20T09:17:34-07:00
New Revision: 063109f758aa61fbd783b16957aeda775c810159
URL: https://github.com/llvm/llvm-project/commit/063109f758aa61fbd783b16957aeda775c810159
DIFF: https://github.com/llvm/llvm-project/commit/063109f758aa61fbd783b16957aeda775c810159.diff
LOG: [NewPM] Adds a port for AArch64MIPeepholeOpt (#187515)
Adds a port for AArch64MIPeepholeOpt
- Refactored lib/Target/AArch64/AArch64MIPeepholeOpt.cpp to extract base
logic as Impl
- Renamed existing pass with "Legacy" suffix and updated references
- Added NewPM pass AArch64MIPeepholeOptPass
- Updated tests
Added:
Modified:
llvm/lib/Target/AArch64/AArch64.h
llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
llvm/lib/Target/AArch64/AArch64PassRegistry.def
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/test/CodeGen/AArch64/addsub-24bit-imm.mir
llvm/test/CodeGen/AArch64/peephole-csel.mir
llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir
llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
llvm/test/CodeGen/AArch64/peephole-movd.mir
llvm/test/CodeGen/AArch64/peephole-orr.mir
llvm/test/CodeGen/AArch64/peephole-sxtw.mir
llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h
index 4e478658c26af..745ff3f85aa2b 100644
--- a/llvm/lib/Target/AArch64/AArch64.h
+++ b/llvm/lib/Target/AArch64/AArch64.h
@@ -56,7 +56,7 @@ FunctionPass *createFalkorHWPFFixPass();
FunctionPass *createFalkorMarkStridedAccessesPass();
FunctionPass *createAArch64PointerAuthPass();
FunctionPass *createAArch64BranchTargetsPass();
-FunctionPass *createAArch64MIPeepholeOptPass();
+FunctionPass *createAArch64MIPeepholeOptLegacyPass();
FunctionPass *createAArch64PostCoalescerPass();
FunctionPass *createAArch64CleanupLocalDynamicTLSPass();
@@ -97,7 +97,7 @@ void initializeAArch64DeadRegisterDefinitionsLegacyPass(PassRegistry &);
void initializeAArch64ExpandPseudoLegacyPass(PassRegistry &);
void initializeAArch64LoadStoreOptLegacyPass(PassRegistry &);
void initializeAArch64LowerHomogeneousPrologEpilogPass(PassRegistry &);
-void initializeAArch64MIPeepholeOptPass(PassRegistry &);
+void initializeAArch64MIPeepholeOptLegacyPass(PassRegistry &);
void initializeAArch64O0PreLegalizerCombinerPass(PassRegistry &);
void initializeAArch64PostCoalescerPass(PassRegistry &);
void initializeAArch64PostLegalizerCombinerPass(PassRegistry &);
@@ -175,6 +175,13 @@ class AArch64ExpandPseudoPass : public PassInfoMixin<AArch64ExpandPseudoPass> {
MachineFunctionAnalysisManager &MFAM);
};
+class AArch64MIPeepholeOptPass
+ : public PassInfoMixin<AArch64MIPeepholeOptPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+
class AArch64ConditionOptimizerPass
: public PassInfoMixin<AArch64ConditionOptimizerPass> {
public:
diff --git a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
index 398273babe1b1..900f22abcf8b0 100644
--- a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
@@ -81,16 +81,18 @@ using namespace llvm;
namespace {
-struct AArch64MIPeepholeOpt : public MachineFunctionPass {
- static char ID;
-
- AArch64MIPeepholeOpt() : MachineFunctionPass(ID) {}
-
+class AArch64MIPeepholeOptImpl {
+public:
const AArch64InstrInfo *TII;
const AArch64RegisterInfo *TRI;
MachineLoopInfo *MLI;
MachineRegisterInfo *MRI;
+ explicit AArch64MIPeepholeOptImpl(MachineLoopInfo &MLI) : MLI(&MLI) {}
+
+ bool run(MachineFunction &MF);
+
+private:
using OpcodePair = std::pair<unsigned, unsigned>;
template <typename T>
using SplitAndOpcFunc =
@@ -141,6 +143,13 @@ struct AArch64MIPeepholeOpt : public MachineFunctionPass {
bool visitFMOVDr(MachineInstr &MI);
bool visitUBFMXri(MachineInstr &MI);
bool visitCopy(MachineInstr &MI);
+};
+
+struct AArch64MIPeepholeOptLegacy : public MachineFunctionPass {
+ static char ID;
+
+ AArch64MIPeepholeOptLegacy() : MachineFunctionPass(ID) {}
+
bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override {
@@ -154,11 +163,11 @@ struct AArch64MIPeepholeOpt : public MachineFunctionPass {
}
};
-char AArch64MIPeepholeOpt::ID = 0;
+char AArch64MIPeepholeOptLegacy::ID = 0;
} // end anonymous namespace
-INITIALIZE_PASS(AArch64MIPeepholeOpt, "aarch64-mi-peephole-opt",
+INITIALIZE_PASS(AArch64MIPeepholeOptLegacy, "aarch64-mi-peephole-opt",
"AArch64 MI Peephole Optimization", false, false)
template <typename T>
@@ -222,9 +231,10 @@ static bool splitDisjointBitmaskImm(T Imm, unsigned RegSize, T &Imm1Enc,
}
template <typename T>
-bool AArch64MIPeepholeOpt::trySplitLogicalImm(unsigned Opc, MachineInstr &MI,
- SplitStrategy Strategy,
- unsigned OtherOpc) {
+bool AArch64MIPeepholeOptImpl::trySplitLogicalImm(unsigned Opc,
+ MachineInstr &MI,
+ SplitStrategy Strategy,
+ unsigned OtherOpc) {
// Try below transformations.
//
// MOVi32imm + (ANDS?|EOR|ORR)Wrr ==> (AND|EOR|ORR)Wri + (ANDS?|EOR|ORR)Wri
@@ -277,7 +287,7 @@ bool AArch64MIPeepholeOpt::trySplitLogicalImm(unsigned Opc, MachineInstr &MI,
});
}
-bool AArch64MIPeepholeOpt::visitORR(MachineInstr &MI) {
+bool AArch64MIPeepholeOptImpl::visitORR(MachineInstr &MI) {
// Check this ORR comes from below zero-extend pattern.
//
// def : Pat<(i64 (zext GPR32:$src)),
@@ -341,7 +351,7 @@ bool AArch64MIPeepholeOpt::visitORR(MachineInstr &MI) {
return true;
}
-bool AArch64MIPeepholeOpt::visitCSEL(MachineInstr &MI) {
+bool AArch64MIPeepholeOptImpl::visitCSEL(MachineInstr &MI) {
// Replace CSEL with MOV when both inputs are the same register.
if (MI.getOperand(1).getReg() != MI.getOperand(2).getReg())
return false;
@@ -361,7 +371,7 @@ bool AArch64MIPeepholeOpt::visitCSEL(MachineInstr &MI) {
return true;
}
-bool AArch64MIPeepholeOpt::visitINSERT(MachineInstr &MI) {
+bool AArch64MIPeepholeOptImpl::visitINSERT(MachineInstr &MI) {
// Check this INSERT_SUBREG comes from below zero-extend pattern.
//
// From %reg = INSERT_SUBREG %reg(tied-def 0), %subreg, subidx
@@ -426,8 +436,8 @@ static bool splitAddSubImm(T Imm, unsigned RegSize, T &Imm0, T &Imm1) {
}
template <typename T>
-bool AArch64MIPeepholeOpt::visitADDSUB(
- unsigned PosOpc, unsigned NegOpc, MachineInstr &MI) {
+bool AArch64MIPeepholeOptImpl::visitADDSUB(unsigned PosOpc, unsigned NegOpc,
+ MachineInstr &MI) {
// Try below transformation.
//
// ADDWrr X, MOVi32imm ==> ADDWri + ADDWri
@@ -475,8 +485,9 @@ bool AArch64MIPeepholeOpt::visitADDSUB(
}
template <typename T>
-bool AArch64MIPeepholeOpt::visitADDSSUBS(
- OpcodePair PosOpcs, OpcodePair NegOpcs, MachineInstr &MI) {
+bool AArch64MIPeepholeOptImpl::visitADDSSUBS(OpcodePair PosOpcs,
+ OpcodePair NegOpcs,
+ MachineInstr &MI) {
// Try the same transformation as ADDSUB but with additional requirement
// that the condition code usages are only for Equal and Not Equal
@@ -522,9 +533,9 @@ bool AArch64MIPeepholeOpt::visitADDSSUBS(
// Checks if the corresponding MOV immediate instruction is applicable for
// this peephole optimization.
-bool AArch64MIPeepholeOpt::checkMovImmInstr(MachineInstr &MI,
- MachineInstr *&MovMI,
- MachineInstr *&SubregToRegMI) {
+bool AArch64MIPeepholeOptImpl::checkMovImmInstr(MachineInstr &MI,
+ MachineInstr *&MovMI,
+ MachineInstr *&SubregToRegMI) {
// Check whether current MBB is in loop and the AND is loop invariant.
MachineBasicBlock *MBB = MI.getParent();
MachineLoop *L = MLI->getLoopFor(MBB);
@@ -561,9 +572,9 @@ bool AArch64MIPeepholeOpt::checkMovImmInstr(MachineInstr &MI,
}
template <typename T>
-bool AArch64MIPeepholeOpt::splitTwoPartImm(
- MachineInstr &MI,
- SplitAndOpcFunc<T> SplitAndOpc, BuildMIFunc BuildInstr) {
+bool AArch64MIPeepholeOptImpl::splitTwoPartImm(MachineInstr &MI,
+ SplitAndOpcFunc<T> SplitAndOpc,
+ BuildMIFunc BuildInstr) {
unsigned RegSize = sizeof(T) * 8;
assert((RegSize == 32 || RegSize == 64) &&
"Invalid RegSize for legal immediate peephole optimization");
@@ -641,7 +652,7 @@ bool AArch64MIPeepholeOpt::splitTwoPartImm(
return true;
}
-bool AArch64MIPeepholeOpt::visitINSviGPR(MachineInstr &MI, unsigned Opc) {
+bool AArch64MIPeepholeOptImpl::visitINSviGPR(MachineInstr &MI, unsigned Opc) {
// Check if this INSvi[X]gpr comes from COPY of a source FPR128
//
// From
@@ -741,7 +752,7 @@ static bool is64bitDefwithZeroHigh64bit(MachineInstr *MI,
return MI->getOpcode() > TargetOpcode::GENERIC_OP_END;
}
-bool AArch64MIPeepholeOpt::visitINSvi64lane(MachineInstr &MI) {
+bool AArch64MIPeepholeOptImpl::visitINSvi64lane(MachineInstr &MI) {
// Check the MI for low 64-bits sets zero for high 64-bits implicitly.
// We are expecting below case.
//
@@ -791,7 +802,7 @@ bool AArch64MIPeepholeOpt::visitINSvi64lane(MachineInstr &MI) {
return true;
}
-bool AArch64MIPeepholeOpt::visitFMOVDr(MachineInstr &MI) {
+bool AArch64MIPeepholeOptImpl::visitFMOVDr(MachineInstr &MI) {
// An FMOVDr sets the high 64-bits to zero implicitly, similar to ORR for GPR.
MachineInstr *Low64MI = MRI->getUniqueVRegDef(MI.getOperand(1).getReg());
if (!Low64MI || !is64bitDefwithZeroHigh64bit(Low64MI, MRI, TII))
@@ -810,7 +821,7 @@ bool AArch64MIPeepholeOpt::visitFMOVDr(MachineInstr &MI) {
return true;
}
-bool AArch64MIPeepholeOpt::visitUBFMXri(MachineInstr &MI) {
+bool AArch64MIPeepholeOptImpl::visitUBFMXri(MachineInstr &MI) {
// Check if the instruction is equivalent to a 32 bit LSR or LSL alias of
// UBFM, and replace the UBFMXri instruction with its 32 bit variant, UBFMWri.
int64_t Immr = MI.getOperand(2).getImm();
@@ -863,7 +874,7 @@ bool AArch64MIPeepholeOpt::visitUBFMXri(MachineInstr &MI) {
// Across a basic-block we might have in i32 extract from a value that only
// operates on upper bits (for example a sxtw). We can replace the COPY with a
// new version skipping the sxtw.
-bool AArch64MIPeepholeOpt::visitCopy(MachineInstr &MI) {
+bool AArch64MIPeepholeOptImpl::visitCopy(MachineInstr &MI) {
Register InputReg = MI.getOperand(1).getReg();
if (MI.getOperand(1).getSubReg() != AArch64::sub_32 ||
!MRI->hasOneNonDBGUse(InputReg))
@@ -925,14 +936,10 @@ bool AArch64MIPeepholeOpt::visitCopy(MachineInstr &MI) {
return true;
}
-bool AArch64MIPeepholeOpt::runOnMachineFunction(MachineFunction &MF) {
- if (skipFunction(MF.getFunction()))
- return false;
-
+bool AArch64MIPeepholeOptImpl::run(MachineFunction &MF) {
TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
TRI = static_cast<const AArch64RegisterInfo *>(
MF.getSubtarget().getRegisterInfo());
- MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
MRI = &MF.getRegInfo();
assert(MRI->isSSA() && "Expected to be run on SSA form!");
@@ -1049,6 +1056,26 @@ bool AArch64MIPeepholeOpt::runOnMachineFunction(MachineFunction &MF) {
return Changed;
}
-FunctionPass *llvm::createAArch64MIPeepholeOptPass() {
- return new AArch64MIPeepholeOpt();
+bool AArch64MIPeepholeOptLegacy::runOnMachineFunction(MachineFunction &MF) {
+ if (skipFunction(MF.getFunction()))
+ return false;
+
+ MachineLoopInfo &MLI = getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+ return AArch64MIPeepholeOptImpl(MLI).run(MF);
+}
+
+FunctionPass *llvm::createAArch64MIPeepholeOptLegacyPass() {
+ return new AArch64MIPeepholeOptLegacy();
+}
+
+PreservedAnalyses
+AArch64MIPeepholeOptPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ MachineLoopInfo &MLI = MFAM.getResult<MachineLoopAnalysis>(MF);
+ const bool Changed = AArch64MIPeepholeOptImpl(MLI).run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+ PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ return PA;
}
diff --git a/llvm/lib/Target/AArch64/AArch64PassRegistry.def b/llvm/lib/Target/AArch64/AArch64PassRegistry.def
index 22a238297073f..7ef8a8adb1d4f 100644
--- a/llvm/lib/Target/AArch64/AArch64PassRegistry.def
+++ b/llvm/lib/Target/AArch64/AArch64PassRegistry.def
@@ -34,5 +34,6 @@ MACHINE_FUNCTION_PASS("aarch64-expand-pseudo", AArch64ExpandPseudoPass())
MACHINE_FUNCTION_PASS("aarch64-fix-cortex-a53-835769", AArch64A53Fix835769Pass())
MACHINE_FUNCTION_PASS("aarch64-jump-tables", AArch64CompressJumpTablesPass())
MACHINE_FUNCTION_PASS("aarch64-ldst-opt", AArch64LoadStoreOptPass())
+MACHINE_FUNCTION_PASS("aarch64-mi-peephole-opt", AArch64MIPeepholeOptPass())
MACHINE_FUNCTION_PASS("aarch64-simd-scalar", AArch64AdvSIMDScalarPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 439715cd67ecc..327ed0ca650b4 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -255,7 +255,7 @@ LLVMInitializeAArch64Target() {
initializeAArch64DeadRegisterDefinitionsLegacyPass(PR);
initializeAArch64ExpandPseudoLegacyPass(PR);
initializeAArch64LoadStoreOptLegacyPass(PR);
- initializeAArch64MIPeepholeOptPass(PR);
+ initializeAArch64MIPeepholeOptLegacyPass(PR);
initializeAArch64SIMDInstrOptPass(PR);
initializeAArch64O0PreLegalizerCombinerPass(PR);
initializeAArch64PreLegalizerCombinerPass(PR);
@@ -812,7 +812,7 @@ void AArch64PassConfig::addMachineSSAOptimization() {
TargetPassConfig::addMachineSSAOptimization();
if (TM->getOptLevel() != CodeGenOptLevel::None)
- addPass(createAArch64MIPeepholeOptPass());
+ addPass(createAArch64MIPeepholeOptLegacyPass());
}
bool AArch64PassConfig::addILPOpts() {
diff --git a/llvm/test/CodeGen/AArch64/addsub-24bit-imm.mir b/llvm/test/CodeGen/AArch64/addsub-24bit-imm.mir
index 8f01a17568cda..53316ff4b77a9 100644
--- a/llvm/test/CodeGen/AArch64/addsub-24bit-imm.mir
+++ b/llvm/test/CodeGen/AArch64/addsub-24bit-imm.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -passes=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux %s | FileCheck %s
# Main intention is to verify machine instructions have valid register classes.
# Use of UBFM[W|X]ri is used as an arbitrary instruction that requires GPR[32|64]RegClass.
diff --git a/llvm/test/CodeGen/AArch64/peephole-csel.mir b/llvm/test/CodeGen/AArch64/peephole-csel.mir
index d424dc05c801c..debf6c1893827 100644
--- a/llvm/test/CodeGen/AArch64/peephole-csel.mir
+++ b/llvm/test/CodeGen/AArch64/peephole-csel.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -o - -mtriple=aarch64-unknown-linux -run-pass=aarch64-mi-peephole-opt -verify-machineinstrs | FileCheck %s
+# RUN: llc %s -o - -mtriple=aarch64-unknown-linux -passes=aarch64-mi-peephole-opt | FileCheck %s
---
name: peephole_cselxr_same
diff --git a/llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir b/llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir
index 4b3d1e0af73fa..14e3bb899356e 100644
--- a/llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir
+++ b/llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -passes=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux %s | FileCheck %s
--- |
define i64 @loop2(i32 noundef %width) {
diff --git a/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir b/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
index a68eda11d5ca1..c43396708b238 100644
--- a/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
+++ b/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-mi-peephole-opt -mtriple=aarch64-unknown-linux -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -passes=aarch64-mi-peephole-opt -mtriple=aarch64-unknown-linux -o - %s | FileCheck %s
--- |
define void @insert_vec_v6i64_uaddlv_from_v4i32(ptr %0) {
entry:
diff --git a/llvm/test/CodeGen/AArch64/peephole-movd.mir b/llvm/test/CodeGen/AArch64/peephole-movd.mir
index 3e4224dc29f38..4fcac459426e8 100644
--- a/llvm/test/CodeGen/AArch64/peephole-movd.mir
+++ b/llvm/test/CodeGen/AArch64/peephole-movd.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -passes=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux %s | FileCheck %s
---
name: remove_kill_flags
diff --git a/llvm/test/CodeGen/AArch64/peephole-orr.mir b/llvm/test/CodeGen/AArch64/peephole-orr.mir
index f718328ecf2d6..1036973772602 100644
--- a/llvm/test/CodeGen/AArch64/peephole-orr.mir
+++ b/llvm/test/CodeGen/AArch64/peephole-orr.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -passes=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux %s | FileCheck %s
---
name: copy_fpr128_gpr32
body: |
diff --git a/llvm/test/CodeGen/AArch64/peephole-sxtw.mir b/llvm/test/CodeGen/AArch64/peephole-sxtw.mir
index a71c6bc09eb2d..1f2fbe16ed59f 100644
--- a/llvm/test/CodeGen/AArch64/peephole-sxtw.mir
+++ b/llvm/test/CodeGen/AArch64/peephole-sxtw.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -passes=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux %s | FileCheck %s
---
name: removeSxtw
diff --git a/llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir b/llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir
index 2ec7ec94e2ebb..f4ed51bf7a009 100644
--- a/llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir
+++ b/llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=aarch64 -run-pass aarch64-mi-peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64 -passes=aarch64-mi-peephole-opt -o - %s | FileCheck %s
---
name: test1
# CHECK-LABEL: name: test1
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