[llvm] Add VDS encoding for gfx13 (PR #187693)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 20 05:50:51 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Mariusz Sikora (mariusz-sikora-at-amd)
<details>
<summary>Changes</summary>
---
Patch is 136.07 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/187693.diff
3 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/DSInstructions.td (+180-150)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_vds.s (+1987)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_vds_alias.s (+147)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index d8a84509a8082..48a8d2325af33 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -1392,12 +1392,12 @@ let SubtargetPredicate = HasGFX950Insts in {
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
-// Base ENC_DS for GFX6, GFX7, GFX10, GFX11, GFX12.
+// Base ENC_DS for GFX6, GFX7, GFX10, GFX11, GFX12, GFX13.
//===----------------------------------------------------------------------===//
-class Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<8> op, DS_Pseudo ps, int ef,
- string opName = ps.Mnemonic,
- bit hasGDS = true>
+class Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12_gfx13<bits<8> op, DS_Pseudo ps, int ef,
+ string opName = ps.Mnemonic,
+ bit hasGDS = true>
: DS_Real<ps, opName>, SIMCInstr <ps.PseudoInstr, ef> {
let Inst{7-0} = !if(ps.has_offset0, offset0, 0);
@@ -1414,63 +1414,82 @@ class Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<8> op, DS_Pseudo ps, int ef,
}
//===----------------------------------------------------------------------===//
-// GFX12.
+// GFX12, GFX13.
//===----------------------------------------------------------------------===//
multiclass DS_Real_gfx12<bits<8> op,
DS_Pseudo ps = !cast<DS_Pseudo>(NAME),
string name = !tolower(NAME)> {
- let AssemblerPredicate = isGFX12Plus in {
+ let AssemblerPredicate = isGFX12Only in {
let DecoderNamespace = "GFX12" in
def _gfx12 :
- Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, ps, SIEncodingFamily.GFX12,
- name, /*hasGDS=*/false>;
+ Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12_gfx13<op, ps, SIEncodingFamily.GFX12,
+ name, /*hasGDS=*/false>;
if !ne(ps.Mnemonic, name) then
def : AMDGPUMnemonicAlias<ps.Mnemonic, name>;
} // End AssemblerPredicate
}
+multiclass DS_Real_gfx13<bits<8> op,
+ DS_Pseudo ps = !cast<DS_Pseudo>(NAME),
+ string name = !tolower(NAME)> {
+ let AssemblerPredicate = isGFX13Only, DecoderNamespace = "GFX13" in
+ def _gfx13 :
+ Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12_gfx13<op, ps,
+ SIEncodingFamily.GFX13,
+ name, /*hasGDS=*/false>;
+ if !ne(ps.Mnemonic, name) then
+ def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX13Only]>;
+}
+
// Helper to avoid repeating the pseudo-name if we only need to set
// the gfx12 name.
multiclass DS_Real_gfx12_with_name<bits<8> op, string name> {
defm "" : DS_Real_gfx12<op, !cast<DS_Pseudo>(NAME#"_gfx9"), name>;
}
-defm DS_MIN_F32 : DS_Real_gfx12_with_name<0x012, "ds_min_num_f32">;
-defm DS_MAX_F32 : DS_Real_gfx12_with_name<0x013, "ds_max_num_f32">;
-defm DS_MIN_RTN_F32 : DS_Real_gfx12_with_name<0x032, "ds_min_num_rtn_f32">;
-defm DS_MAX_RTN_F32 : DS_Real_gfx12_with_name<0x033, "ds_max_num_rtn_f32">;
-defm DS_MIN_F64 : DS_Real_gfx12_with_name<0x052, "ds_min_num_f64">;
-defm DS_MAX_F64 : DS_Real_gfx12_with_name<0x053, "ds_max_num_f64">;
-defm DS_MIN_RTN_F64 : DS_Real_gfx12_with_name<0x072, "ds_min_num_rtn_f64">;
-defm DS_MAX_RTN_F64 : DS_Real_gfx12_with_name<0x073, "ds_max_num_rtn_f64">;
-defm DS_COND_SUB_U32 : DS_Real_gfx12<0x098>;
-defm DS_SUB_CLAMP_U32 : DS_Real_gfx12<0x099>;
-defm DS_COND_SUB_RTN_U32 : DS_Real_gfx12<0x0a8>;
-defm DS_SUB_CLAMP_RTN_U32 : DS_Real_gfx12<0x0a9>;
-defm DS_PK_ADD_F16 : DS_Real_gfx12<0x09a>;
-defm DS_PK_ADD_RTN_F16 : DS_Real_gfx12<0x0aa>;
-defm DS_PK_ADD_BF16 : DS_Real_gfx12<0x09b>;
-defm DS_PK_ADD_RTN_BF16 : DS_Real_gfx12<0x0ab>;
-defm DS_BPERMUTE_FI_B32 : DS_Real_gfx12<0x0cd>;
-
-defm DS_LOAD_TR4_B64 : DS_Real_gfx12<0x0fa>;
-defm DS_LOAD_TR6_B96 : DS_Real_gfx12<0x0fb>;
-defm DS_LOAD_TR16_B128 : DS_Real_gfx12<0x0fc>;
-defm DS_LOAD_TR8_B64 : DS_Real_gfx12<0x0fd>;
+multiclass DS_Real_gfx12_gfx13<bits<8> op, DS_Pseudo ps = !cast<DS_Pseudo>(NAME), string name = !tolower(NAME)> :
+ DS_Real_gfx12<op, ps, name>, DS_Real_gfx13<op, ps, name>;
+
+multiclass DS_Real_gfx12_gfx13_with_name<bits<8> op, string name> {
+ defm "" : DS_Real_gfx12_gfx13<op, !cast<DS_Pseudo>(NAME#"_gfx9"), name>;
+}
+
+defm DS_MIN_F32 : DS_Real_gfx12_gfx13_with_name<0x012, "ds_min_num_f32">;
+defm DS_MAX_F32 : DS_Real_gfx12_gfx13_with_name<0x013, "ds_max_num_f32">;
+defm DS_MIN_RTN_F32 : DS_Real_gfx12_gfx13_with_name<0x032, "ds_min_num_rtn_f32">;
+defm DS_MAX_RTN_F32 : DS_Real_gfx12_gfx13_with_name<0x033, "ds_max_num_rtn_f32">;
+defm DS_MIN_F64 : DS_Real_gfx12_gfx13_with_name<0x052, "ds_min_num_f64">;
+defm DS_MAX_F64 : DS_Real_gfx12_gfx13_with_name<0x053, "ds_max_num_f64">;
+defm DS_MIN_RTN_F64 : DS_Real_gfx12_gfx13_with_name<0x072, "ds_min_num_rtn_f64">;
+defm DS_MAX_RTN_F64 : DS_Real_gfx12_gfx13_with_name<0x073, "ds_max_num_rtn_f64">;
+defm DS_COND_SUB_U32 : DS_Real_gfx12_gfx13<0x098>;
+defm DS_SUB_CLAMP_U32 : DS_Real_gfx12_gfx13<0x099>;
+defm DS_COND_SUB_RTN_U32 : DS_Real_gfx12_gfx13<0x0a8>;
+defm DS_SUB_CLAMP_RTN_U32 : DS_Real_gfx12_gfx13<0x0a9>;
+defm DS_PK_ADD_F16 : DS_Real_gfx12_gfx13<0x09a>;
+defm DS_PK_ADD_RTN_F16 : DS_Real_gfx12_gfx13<0x0aa>;
+defm DS_PK_ADD_BF16 : DS_Real_gfx12_gfx13<0x09b>;
+defm DS_PK_ADD_RTN_BF16 : DS_Real_gfx12_gfx13<0x0ab>;
+defm DS_BPERMUTE_FI_B32 : DS_Real_gfx12_gfx13<0x0cd>;
+
+defm DS_LOAD_TR4_B64 : DS_Real_gfx12_gfx13<0x0fa>;
+defm DS_LOAD_TR6_B96 : DS_Real_gfx12_gfx13<0x0fb>;
+defm DS_LOAD_TR16_B128 : DS_Real_gfx12_gfx13<0x0fc>;
+defm DS_LOAD_TR8_B64 : DS_Real_gfx12_gfx13<0x0fd>;
defm DS_BVH_STACK_RTN_B32 : DS_Real_gfx12<0x0e0, DS_BVH_STACK_RTN_B32,
"ds_bvh_stack_push4_pop1_rtn_b32">;
defm DS_BVH_STACK_PUSH8_POP1_RTN_B32 : DS_Real_gfx12<0x0e1>;
defm DS_BVH_STACK_PUSH8_POP2_RTN_B64 : DS_Real_gfx12<0x0e2>;
-defm DS_ADD_F64 : DS_Real_gfx12<0x054>;
-defm DS_ADD_RTN_F64 : DS_Real_gfx12<0x074>;
+defm DS_ADD_F64 : DS_Real_gfx12_gfx13<0x054>;
+defm DS_ADD_RTN_F64 : DS_Real_gfx12_gfx13<0x074>;
let AssemblerPredicate = HasLdsBarrierArriveAtomic in {
-defm DS_ATOMIC_ASYNC_BARRIER_ARRIVE_B64 : DS_Real_gfx12<0x056>;
-defm DS_ATOMIC_BARRIER_ARRIVE_RTN_B64 : DS_Real_gfx12<0x075>;
+defm DS_ATOMIC_ASYNC_BARRIER_ARRIVE_B64 : DS_Real_gfx12_gfx13<0x056>;
+defm DS_ATOMIC_BARRIER_ARRIVE_RTN_B64 : DS_Real_gfx12_gfx13<0x075>;
}
// New aliases added in GFX12 without renaming the instructions.
@@ -1500,8 +1519,8 @@ multiclass DS_Real_gfx11<bits<8> op, DS_Pseudo ps = !cast<DS_Pseudo>(NAME#"_gfx9
let AssemblerPredicate = isGFX11Only in {
let DecoderNamespace = "GFX11" in
def _gfx11 :
- Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, ps, SIEncodingFamily.GFX11,
- name>;
+ Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12_gfx13<op, ps, SIEncodingFamily.GFX11,
+ name>;
if !ne(ps.Mnemonic, name) then
def : AMDGPUMnemonicAlias<ps.Mnemonic, name>;
} // End AssemblerPredicate
@@ -1513,56 +1532,63 @@ multiclass DS_Real_gfx11_gfx12<bits<8> op,
: DS_Real_gfx11<op, ps, name>,
DS_Real_gfx12<op, ps, name>;
-defm DS_WRITE_B32 : DS_Real_gfx11_gfx12<0x00d, "ds_store_b32">;
-defm DS_WRITE2_B32 : DS_Real_gfx11_gfx12<0x00e, "ds_store_2addr_b32">;
-defm DS_WRITE2ST64_B32 : DS_Real_gfx11_gfx12<0x00f, "ds_store_2addr_stride64_b32">;
-defm DS_WRITE_B8 : DS_Real_gfx11_gfx12<0x01e, "ds_store_b8">;
-defm DS_WRITE_B16 : DS_Real_gfx11_gfx12<0x01f, "ds_store_b16">;
-defm DS_WRXCHG_RTN_B32 : DS_Real_gfx11_gfx12<0x02d, "ds_storexchg_rtn_b32">;
-defm DS_WRXCHG2_RTN_B32 : DS_Real_gfx11_gfx12<0x02e, "ds_storexchg_2addr_rtn_b32">;
-defm DS_WRXCHG2ST64_RTN_B32 : DS_Real_gfx11_gfx12<0x02f, "ds_storexchg_2addr_stride64_rtn_b32">;
-defm DS_READ_B32 : DS_Real_gfx11_gfx12<0x036, "ds_load_b32">;
-defm DS_READ2_B32 : DS_Real_gfx11_gfx12<0x037, "ds_load_2addr_b32">;
-defm DS_READ2ST64_B32 : DS_Real_gfx11_gfx12<0x038, "ds_load_2addr_stride64_b32">;
-defm DS_READ_I8 : DS_Real_gfx11_gfx12<0x039, "ds_load_i8">;
-defm DS_READ_U8 : DS_Real_gfx11_gfx12<0x03a, "ds_load_u8">;
-defm DS_READ_I16 : DS_Real_gfx11_gfx12<0x03b, "ds_load_i16">;
-defm DS_READ_U16 : DS_Real_gfx11_gfx12<0x03c, "ds_load_u16">;
-defm DS_WRITE_B64 : DS_Real_gfx11_gfx12<0x04d, "ds_store_b64">;
-defm DS_WRITE2_B64 : DS_Real_gfx11_gfx12<0x04e, "ds_store_2addr_b64">;
-defm DS_WRITE2ST64_B64 : DS_Real_gfx11_gfx12<0x04f, "ds_store_2addr_stride64_b64">;
-defm DS_WRXCHG_RTN_B64 : DS_Real_gfx11_gfx12<0x06d, "ds_storexchg_rtn_b64">;
-defm DS_WRXCHG2_RTN_B64 : DS_Real_gfx11_gfx12<0x06e, "ds_storexchg_2addr_rtn_b64">;
-defm DS_WRXCHG2ST64_RTN_B64 : DS_Real_gfx11_gfx12<0x06f, "ds_storexchg_2addr_stride64_rtn_b64">;
-defm DS_READ_B64 : DS_Real_gfx11_gfx12<0x076, "ds_load_b64">;
-defm DS_READ2_B64 : DS_Real_gfx11_gfx12<0x077, "ds_load_2addr_b64">;
-defm DS_READ2ST64_B64 : DS_Real_gfx11_gfx12<0x078, "ds_load_2addr_stride64_b64">;
-defm DS_WRITE_B8_D16_HI : DS_Real_gfx11_gfx12<0x0a0, "ds_store_b8_d16_hi", DS_WRITE_B8_D16_HI>;
-defm DS_WRITE_B16_D16_HI : DS_Real_gfx11_gfx12<0x0a1, "ds_store_b16_d16_hi", DS_WRITE_B16_D16_HI>;
-defm DS_READ_U8_D16 : DS_Real_gfx11_gfx12<0x0a2, "ds_load_u8_d16", DS_READ_U8_D16>;
-defm DS_READ_U8_D16_HI : DS_Real_gfx11_gfx12<0x0a3, "ds_load_u8_d16_hi", DS_READ_U8_D16_HI>;
-defm DS_READ_I8_D16 : DS_Real_gfx11_gfx12<0x0a4, "ds_load_i8_d16", DS_READ_I8_D16>;
-defm DS_READ_I8_D16_HI : DS_Real_gfx11_gfx12<0x0a5, "ds_load_i8_d16_hi", DS_READ_I8_D16_HI>;
-defm DS_READ_U16_D16 : DS_Real_gfx11_gfx12<0x0a6, "ds_load_u16_d16", DS_READ_U16_D16>;
-defm DS_READ_U16_D16_HI : DS_Real_gfx11_gfx12<0x0a7, "ds_load_u16_d16_hi", DS_READ_U16_D16_HI>;
-defm DS_WRITE_ADDTID_B32 : DS_Real_gfx11_gfx12<0x0b0, "ds_store_addtid_b32", DS_WRITE_ADDTID_B32>;
-defm DS_READ_ADDTID_B32 : DS_Real_gfx11_gfx12<0x0b1, "ds_load_addtid_b32", DS_READ_ADDTID_B32>;
-defm DS_WRITE_B96 : DS_Real_gfx11_gfx12<0x0de, "ds_store_b96">;
-defm DS_WRITE_B128 : DS_Real_gfx11_gfx12<0x0df, "ds_store_b128">;
-defm DS_READ_B96 : DS_Real_gfx11_gfx12<0x0fe, "ds_load_b96">;
-defm DS_READ_B128 : DS_Real_gfx11_gfx12<0x0ff, "ds_load_b128">;
+multiclass DS_Real_gfx11_gfx12_gfx13<bits<8> op,
+ string name = !tolower(NAME),
+ DS_Pseudo ps = !cast<DS_Pseudo>(NAME#"_gfx9")>
+ : DS_Real_gfx11<op, ps, name>,
+ DS_Real_gfx12<op, ps, name>,
+ DS_Real_gfx13<op, ps, name>;
+
+defm DS_WRITE_B32 : DS_Real_gfx11_gfx12_gfx13<0x00d, "ds_store_b32">;
+defm DS_WRITE2_B32 : DS_Real_gfx11_gfx12_gfx13<0x00e, "ds_store_2addr_b32">;
+defm DS_WRITE2ST64_B32 : DS_Real_gfx11_gfx12_gfx13<0x00f, "ds_store_2addr_stride64_b32">;
+defm DS_WRITE_B8 : DS_Real_gfx11_gfx12_gfx13<0x01e, "ds_store_b8">;
+defm DS_WRITE_B16 : DS_Real_gfx11_gfx12_gfx13<0x01f, "ds_store_b16">;
+defm DS_WRXCHG_RTN_B32 : DS_Real_gfx11_gfx12_gfx13<0x02d, "ds_storexchg_rtn_b32">;
+defm DS_WRXCHG2_RTN_B32 : DS_Real_gfx11_gfx12_gfx13<0x02e, "ds_storexchg_2addr_rtn_b32">;
+defm DS_WRXCHG2ST64_RTN_B32 : DS_Real_gfx11_gfx12_gfx13<0x02f, "ds_storexchg_2addr_stride64_rtn_b32">;
+defm DS_READ_B32 : DS_Real_gfx11_gfx12_gfx13<0x036, "ds_load_b32">;
+defm DS_READ2_B32 : DS_Real_gfx11_gfx12_gfx13<0x037, "ds_load_2addr_b32">;
+defm DS_READ2ST64_B32 : DS_Real_gfx11_gfx12_gfx13<0x038, "ds_load_2addr_stride64_b32">;
+defm DS_READ_I8 : DS_Real_gfx11_gfx12_gfx13<0x039, "ds_load_i8">;
+defm DS_READ_U8 : DS_Real_gfx11_gfx12_gfx13<0x03a, "ds_load_u8">;
+defm DS_READ_I16 : DS_Real_gfx11_gfx12_gfx13<0x03b, "ds_load_i16">;
+defm DS_READ_U16 : DS_Real_gfx11_gfx12_gfx13<0x03c, "ds_load_u16">;
+defm DS_WRITE_B64 : DS_Real_gfx11_gfx12_gfx13<0x04d, "ds_store_b64">;
+defm DS_WRITE2_B64 : DS_Real_gfx11_gfx12_gfx13<0x04e, "ds_store_2addr_b64">;
+defm DS_WRITE2ST64_B64 : DS_Real_gfx11_gfx12_gfx13<0x04f, "ds_store_2addr_stride64_b64">;
+defm DS_WRXCHG_RTN_B64 : DS_Real_gfx11_gfx12_gfx13<0x06d, "ds_storexchg_rtn_b64">;
+defm DS_WRXCHG2_RTN_B64 : DS_Real_gfx11_gfx12_gfx13<0x06e, "ds_storexchg_2addr_rtn_b64">;
+defm DS_WRXCHG2ST64_RTN_B64 : DS_Real_gfx11_gfx12_gfx13<0x06f, "ds_storexchg_2addr_stride64_rtn_b64">;
+defm DS_READ_B64 : DS_Real_gfx11_gfx12_gfx13<0x076, "ds_load_b64">;
+defm DS_READ2_B64 : DS_Real_gfx11_gfx12_gfx13<0x077, "ds_load_2addr_b64">;
+defm DS_READ2ST64_B64 : DS_Real_gfx11_gfx12_gfx13<0x078, "ds_load_2addr_stride64_b64">;
+defm DS_WRITE_B8_D16_HI : DS_Real_gfx11_gfx12_gfx13<0x0a0, "ds_store_b8_d16_hi", DS_WRITE_B8_D16_HI>;
+defm DS_WRITE_B16_D16_HI : DS_Real_gfx11_gfx12_gfx13<0x0a1, "ds_store_b16_d16_hi", DS_WRITE_B16_D16_HI>;
+defm DS_READ_U8_D16 : DS_Real_gfx11_gfx12_gfx13<0x0a2, "ds_load_u8_d16", DS_READ_U8_D16>;
+defm DS_READ_U8_D16_HI : DS_Real_gfx11_gfx12_gfx13<0x0a3, "ds_load_u8_d16_hi", DS_READ_U8_D16_HI>;
+defm DS_READ_I8_D16 : DS_Real_gfx11_gfx12_gfx13<0x0a4, "ds_load_i8_d16", DS_READ_I8_D16>;
+defm DS_READ_I8_D16_HI : DS_Real_gfx11_gfx12_gfx13<0x0a5, "ds_load_i8_d16_hi", DS_READ_I8_D16_HI>;
+defm DS_READ_U16_D16 : DS_Real_gfx11_gfx12_gfx13<0x0a6, "ds_load_u16_d16", DS_READ_U16_D16>;
+defm DS_READ_U16_D16_HI : DS_Real_gfx11_gfx12_gfx13<0x0a7, "ds_load_u16_d16_hi", DS_READ_U16_D16_HI>;
+defm DS_WRITE_ADDTID_B32 : DS_Real_gfx11_gfx12_gfx13<0x0b0, "ds_store_addtid_b32", DS_WRITE_ADDTID_B32>;
+defm DS_READ_ADDTID_B32 : DS_Real_gfx11_gfx12_gfx13<0x0b1, "ds_load_addtid_b32", DS_READ_ADDTID_B32>;
+defm DS_WRITE_B96 : DS_Real_gfx11_gfx12_gfx13<0x0de, "ds_store_b96">;
+defm DS_WRITE_B128 : DS_Real_gfx11_gfx12_gfx13<0x0df, "ds_store_b128">;
+defm DS_READ_B96 : DS_Real_gfx11_gfx12_gfx13<0x0fe, "ds_load_b96">;
+defm DS_READ_B128 : DS_Real_gfx11_gfx12_gfx13<0x0ff, "ds_load_b128">;
// DS_CMPST_* are renamed to DS_CMPSTORE_* in GFX11, but also the data operands (src and cmp) are swapped
// comparing to pre-GFX11.
// Note: the mnemonic alias is not generated to avoid a potential ambiguity due to the semantics change.
-defm DS_CMPSTORE_B32 : DS_Real_gfx11_gfx12<0x010>;
+defm DS_CMPSTORE_B32 : DS_Real_gfx11_gfx12_gfx13<0x010>;
defm DS_CMPSTORE_F32 : DS_Real_gfx11<0x011>;
-defm DS_CMPSTORE_RTN_B32 : DS_Real_gfx11_gfx12<0x030>;
+defm DS_CMPSTORE_RTN_B32 : DS_Real_gfx11_gfx12_gfx13<0x030>;
defm DS_CMPSTORE_RTN_F32 : DS_Real_gfx11<0x031>;
-defm DS_CMPSTORE_B64 : DS_Real_gfx11_gfx12<0x050>;
+defm DS_CMPSTORE_B64 : DS_Real_gfx11_gfx12_gfx13<0x050>;
defm DS_CMPSTORE_F64 : DS_Real_gfx11<0x051>;
-defm DS_CMPSTORE_RTN_B64 : DS_Real_gfx11_gfx12<0x070>;
+defm DS_CMPSTORE_RTN_B64 : DS_Real_gfx11_gfx12_gfx13<0x070>;
defm DS_CMPSTORE_RTN_F64 : DS_Real_gfx11<0x071>;
defm DS_ADD_RTN_F32 : DS_Real_gfx11_gfx12<0x079>;
@@ -1576,12 +1602,15 @@ defm DS_BVH_STACK_RTN_B32 : DS_Real_gfx11<0x0ad, DS_BVH_STACK_RTN
let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
multiclass DS_Real_gfx10<bits<8> op, DS_Pseudo ps = !cast<DS_Pseudo>(NAME)> {
- def _gfx10 : Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op,
+ def _gfx10 : Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12_gfx13<op,
ps, SIEncodingFamily.GFX10>;
}
} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10"
-defm DS_ADD_RTN_F32 : DS_Real_gfx10<0x055, DS_ADD_RTN_F32_gfx9>;
+multiclass DS_Real_gfx10_gfx13<bits<8> op, DS_Pseudo ps = !cast<DS_Pseudo>(NAME)> :
+ DS_Real_gfx10<op, ps>, DS_Real_gfx13<op, ps>;
+
+defm DS_ADD_RTN_F32 : DS_Real_gfx10_gfx13<0x055, DS_ADD_RTN_F32_gfx9>;
defm DS_WRITE_B8_D16_HI : DS_Real_gfx10<0x0a0>;
defm DS_WRITE_B16_D16_HI : DS_Real_gfx10<0x0a1>;
defm DS_READ_U8_D16 : DS_Real_gfx10<0x0a2>;
@@ -1594,38 +1623,39 @@ defm DS_WRITE_ADDTID_B32 : DS_Real_gfx10<0x0b0>;
defm DS_READ_ADDTID_B32 : DS_Real_gfx10<0x0b1>;
//===----------------------------------------------------------------------===//
-// GFX10, GFX11, GFX12.
+// GFX10, GFX11, GFX12, GFX13.
//===----------------------------------------------------------------------===//
-multiclass DS_Real_gfx10_gfx11_gfx12<bits<8> op, DS_Pseudo ps = !cast<DS_Pseudo>(NAME#"_gfx9")> :
+multiclass DS_Real_gfx10_gfx11_gfx12_gfx13<bits<8> op, DS_Pseudo ps = !cast<DS_Pseudo>(NAME#"_gfx9")> :
DS_Real_gfx10<op, ps>,
DS_Real_gfx11<op, ps>,
- DS_Real_gfx12<op, ps>;
+ DS_Real_gfx12<op, ps>,
+ DS_Real_gfx13<op, ps>;
multiclass DS_Real_gfx10_gfx11<bits<8> op, DS_Pseudo ps = !cast<DS_Pseudo>(NAME#"_gfx9")> :
DS_Real_gfx10<op, ps>, DS_Real_gfx11<op, ps>;
-defm DS_ADD_F32 : DS_Real_gfx10_gfx11_gfx12<0x015>;
+defm DS_ADD_F32 : DS_Real_gfx10_gfx11_gfx12_gfx13<0x015>;
defm DS_ADD_SRC2_F32 : DS_Real_gfx10<0x095>;
-defm DS_PERMUTE_B32 : DS_Real_gfx10_gfx11_gfx12<0x0b2, DS_PERMUTE_B32>;
-defm DS_BPERMUTE_B32 : DS_Real_gfx10_gfx11_gfx12<0x0b3, DS_BPERMUTE_B32>;
+defm DS_PERMUTE_B32 : DS_Real_gfx10_gfx11_gfx12_gfx13<0x0b2, DS_PERMUTE_B32>;
+defm DS_BPERMUTE_B32 : DS_Real_gfx10_gfx11_gfx12_gfx13<0x0b3, DS_BPERMUTE_B32>;
//===----------------------------------------------------------------------===//
-// GFX7, GFX10, GFX11, GFX12.
+// GFX7, GFX10, GFX11, GFX12, GFX13.
//===----------------------------------------------------------------------===//
let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in {
multiclass DS_Real_gfx7<bits<8> op, DS_Pseudo ps> {
- def _gfx7 : Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op,
+ def _gfx7 : Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12_gfx13<op,
ps, SIEncodingFamily.SI>;
}
} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7"
-multiclass DS_Real_gfx7_gfx10_gfx11_gfx12<bits<8> op,
+multiclass DS_Real_gfx7_gfx10_gfx11_gfx12_gfx13<bits<8> op,
DS_Pseudo ps_gfx6 = !cast<DS_Pseudo>(NAME),
DS_Pseudo ps_gfx9 = !cast<DS_Pseudo>(NAME#"_gfx9")> :
DS_Real_gfx7<op, ps_gfx6>,
- DS_Real_gfx10_gfx11_gfx12<op, ps_gfx9>;
+ DS_Real_gfx10_gfx11_gfx12_gfx13<op, ps_gfx9>;
multiclass DS_Real_gfx7_gfx10_gfx11<bits<8> op,
DS_Pseudo ps_gfx6 = !cast<DS_Pseudo>(NAME),
@@ -1640,7 +1670,7 @@ multiclass DS_Real_gfx7_gfx10<bits<8> op,
// FIXME-GFX7: Add tests when upstreaming this part.
defm DS_GWS_SEMA_RELEASE_ALL : DS_Real_gfx7_gfx10_gfx11<0x018, DS_GWS_SEMA_RELEASE_ALL, DS_GWS_SEMA_RELEASE_ALL>;
defm DS_WRAP_RTN_B32 : DS_Real_gfx7_gfx10_gfx11<0x034>;
-defm DS_CONDXCHG32_RTN_B64 : DS_Real_gfx7_gfx10_gfx11_gfx12<0x07e>;
+defm DS_CONDXCHG32_RTN_B64 : DS_Real_gfx7_gfx10_gfx11_gfx12_gfx13<0x07e>;
defm DS_WRITE_B96 : DS_Real_gfx7_gfx10<0x0de>;
defm DS_WRITE_B128 : DS_Real_gfx7_gfx10<0x0df>;
defm DS_READ_B96 : DS_Real_gfx7_gfx10<0x0fe>;
@@ -1652,16 +1682,16 @@ defm DS_READ_B128 : DS_Real_gfx7_gfx10<0x0ff>;
let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
multiclass DS_Real_gfx6_gfx7<bits<8> op, DS_Pseudo ps> {
- def _gfx6_gfx7 : Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op,
+ def _gfx6_gfx7 : Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12_gfx13<op,
ps, SIEncodingFamily.SI>;
}
} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/187693
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