[llvm] b91c5a7 - [AMDGPU] Test saturated f32 to i8 conversion on vectors (#187487)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 19 06:49:04 PDT 2026
Author: Jay Foad
Date: 2026-03-19T13:48:58Z
New Revision: b91c5a7701e1922b0bb8e21fed8222215c78c5d0
URL: https://github.com/llvm/llvm-project/commit/b91c5a7701e1922b0bb8e21fed8222215c78c5d0
DIFF: https://github.com/llvm/llvm-project/commit/b91c5a7701e1922b0bb8e21fed8222215c78c5d0.diff
LOG: [AMDGPU] Test saturated f32 to i8 conversion on vectors (#187487)
Added:
Modified:
llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
index 78d95778e6a4d..f3d45efebe3fc 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
@@ -3466,3 +3466,204 @@ define <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
%x = call <8 x i64> @llvm.fptosi.sat.v8f16.v8i64(<8 x half> %f)
ret <8 x i64> %x
}
+
+;
+; Float to signed 8-bit
+;
+
+define <4 x i8> @test_signed_v4f32_v4i8(<4 x float> %f) {
+; GFX7-ISEL-LABEL: test_signed_v4f32_v4i8:
+; GFX7-ISEL: ; %bb.0:
+; GFX7-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX7-ISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX7-ISEL-NEXT: s_movk_i32 s4, 0xff80
+; GFX7-ISEL-NEXT: v_mov_b32_e32 v4, 0x7f
+; GFX7-ISEL-NEXT: v_med3_i32 v3, v3, s4, v4
+; GFX7-ISEL-NEXT: v_med3_i32 v2, v2, s4, v4
+; GFX7-ISEL-NEXT: v_med3_i32 v1, v1, s4, v4
+; GFX7-ISEL-NEXT: v_med3_i32 v0, v0, s4, v4
+; GFX7-ISEL-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX7-ISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX7-ISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX7-ISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-ISEL-NEXT: v_or_b32_e32 v3, v2, v3
+; GFX7-ISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-ISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX7-ISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX7-ISEL-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX7-ISEL-NEXT: v_and_b32_e32 v2, 0xffff, v3
+; GFX7-ISEL-NEXT: v_bfe_u32 v3, v3, 8, 8
+; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-GI-LABEL: test_signed_v4f32_v4i8:
+; GFX7-GI: ; %bb.0:
+; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX7-GI-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX7-GI-NEXT: v_mov_b32_e32 v4, 0x7f
+; GFX7-GI-NEXT: v_mov_b32_e32 v5, 0xffffff80
+; GFX7-GI-NEXT: v_med3_i32 v0, v0, v5, v4
+; GFX7-GI-NEXT: v_med3_i32 v1, v1, v5, v4
+; GFX7-GI-NEXT: v_med3_i32 v2, v2, v5, v4
+; GFX7-GI-NEXT: v_med3_i32 v3, v3, v5, v4
+; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: test_signed_v4f32_v4i8:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX9-NEXT: s_movk_i32 s4, 0xff80
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x7f
+; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX9-NEXT: v_med3_i32 v3, v3, s4, v4
+; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3
+; GFX9-NEXT: v_med3_i32 v2, v2, s4, v4
+; GFX9-NEXT: v_med3_i32 v1, v1, s4, v4
+; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
+; GFX9-NEXT: v_med3_i32 v0, v0, s4, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_signed_v4f32_v4i8:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: s_movk_i32 s0, 0xff80
+; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_med3_i32 v3, v3, s0, 0x7f
+; GFX11-FAKE16-NEXT: v_med3_i32 v2, v2, s0, 0x7f
+; GFX11-FAKE16-NEXT: v_med3_i32 v1, v1, s0, 0x7f
+; GFX11-FAKE16-NEXT: v_med3_i32 v0, v0, s0, 0x7f
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_signed_v4f32_v4i8:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: s_movk_i32 s0, 0xff80
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v0
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX11-TRUE16-NEXT: v_med3_i32 v3, v3, s0, 0x7f
+; GFX11-TRUE16-NEXT: v_med3_i32 v2, v2, s0, 0x7f
+; GFX11-TRUE16-NEXT: v_med3_i32 v1, v1, s0, 0x7f
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v3.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_med3_i32 v2, v4, s0, 0x7f
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: test_signed_v4f32_v4i8:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX12-FAKE16-NEXT: s_movk_i32 s0, 0xff80
+; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_med3_i32 v3, v3, s0, 0x7f
+; GFX12-FAKE16-NEXT: v_med3_i32 v2, v2, s0, 0x7f
+; GFX12-FAKE16-NEXT: v_med3_i32 v1, v1, s0, 0x7f
+; GFX12-FAKE16-NEXT: v_med3_i32 v0, v0, s0, 0x7f
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v1
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: test_signed_v4f32_v4i8:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX12-TRUE16-NEXT: s_movk_i32 s0, 0xff80
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v0
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_med3_i32 v3, v3, s0, 0x7f
+; GFX12-TRUE16-NEXT: v_med3_i32 v2, v2, s0, 0x7f
+; GFX12-TRUE16-NEXT: v_med3_i32 v1, v1, s0, 0x7f
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v3.l
+; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
+; GFX12-TRUE16-NEXT: v_med3_i32 v2, v4, s0, 0x7f
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX12-TRUE16-NEXT: v_or_b16 v2.h, v0.h, v0.l
+; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.h
+; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GI-LABEL: test_signed_v4f32_v4i8:
+; GFX12-GI: ; %bb.0:
+; GFX12-GI-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GI-NEXT: s_wait_expcnt 0x0
+; GFX12-GI-NEXT: s_wait_samplecnt 0x0
+; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GI-NEXT: s_wait_kmcnt 0x0
+; GFX12-GI-NEXT: v_mov_b32_e32 v4, 0xffffff80
+; GFX12-GI-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX12-GI-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX12-GI-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX12-GI-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX12-GI-NEXT: v_med3_i32 v0, v0, v4, 0x7f
+; GFX12-GI-NEXT: v_med3_i32 v1, v1, v4, 0x7f
+; GFX12-GI-NEXT: v_med3_i32 v2, v2, v4, 0x7f
+; GFX12-GI-NEXT: v_med3_i32 v3, v3, v4, 0x7f
+; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
+ %x = call <4 x i8> @llvm.fptosi.sat.v4f32.v4i8(<4 x float> %f)
+ ret <4 x i8> %x
+}
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
index 7fc6c13f3136c..d6c6bc6fd47ea 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
@@ -3266,3 +3266,178 @@ define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
%x = call <8 x i64> @llvm.fptoui.sat.v8f16.v8i64(<8 x half> %f)
ret <8 x i64> %x
}
+
+;
+; Float to unsigned 8-bit
+;
+
+define <4 x i8> @test_unsigned_v4f32_v4i8(<4 x float> %f) {
+; GFX7-ISEL-LABEL: test_unsigned_v4f32_v4i8:
+; GFX7-ISEL: ; %bb.0:
+; GFX7-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX7-ISEL-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX7-ISEL-NEXT: v_min_u32_e32 v1, 0xff, v1
+; GFX7-ISEL-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX7-ISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX7-ISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-ISEL-NEXT: v_min_u32_e32 v1, 0xff, v2
+; GFX7-ISEL-NEXT: v_min_u32_e32 v2, 0xff, v3
+; GFX7-ISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX7-ISEL-NEXT: v_or_b32_e32 v2, v1, v2
+; GFX7-ISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX7-ISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-ISEL-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX7-ISEL-NEXT: v_bfe_u32 v3, v2, 8, 8
+; GFX7-ISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-GI-LABEL: test_unsigned_v4f32_v4i8:
+; GFX7-GI: ; %bb.0:
+; GFX7-GI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX7-GI-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX7-GI-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX7-GI-NEXT: v_min_u32_e32 v1, 0xff, v1
+; GFX7-GI-NEXT: v_min_u32_e32 v2, 0xff, v2
+; GFX7-GI-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX7-GI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: test_unsigned_v4f32_v4i8:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: s_movk_i32 s4, 0xff
+; GFX9-NEXT: v_min_u32_sdwa v3, v3, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_min_u32_e32 v2, 0xff, v2
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_min_u32_sdwa v1, v1, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_unsigned_v4f32_v4i8:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_unsigned_v4f32_v4i8:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v1
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v2, 0xff, v2
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v3.l
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v4
+; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: test_unsigned_v4f32_v4i8:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX12-FAKE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-FAKE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX12-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v1
+; GFX12-FAKE16-NEXT: v_min_u32_e32 v2, 0xff, v2
+; GFX12-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v1
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: test_unsigned_v4f32_v4i8:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v1
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v2, 0xff, v2
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v3.l
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v4
+; GFX12-TRUE16-NEXT: v_or_b16 v2.h, v2.l, v1.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.h
+; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GI-LABEL: test_unsigned_v4f32_v4i8:
+; GFX12-GI: ; %bb.0:
+; GFX12-GI-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GI-NEXT: s_wait_expcnt 0x0
+; GFX12-GI-NEXT: s_wait_samplecnt 0x0
+; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GI-NEXT: s_wait_kmcnt 0x0
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX12-GI-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX12-GI-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX12-GI-NEXT: v_min_u32_e32 v1, 0xff, v1
+; GFX12-GI-NEXT: v_min_u32_e32 v2, 0xff, v2
+; GFX12-GI-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
+ %x = call <4 x i8> @llvm.fptoui.sat.v4f32.v4i8(<4 x float> %f)
+ ret <4 x i8> %x
+}
More information about the llvm-commits
mailing list